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ORCIDRolf Drechsler
Person information
- affiliation: University of Bremen, Institute of Computer Science
- affiliation: German Research Centre for Artificial Intelligence (DFKI), Bremen
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2020 – today
- 2023
[j148]Sören Tempel
, Vladimir Herdt, Rolf Drechsler:
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. 10(11): 9544-9555 (2023)- [j147]Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler:
Impact of sneak paths on in-memory logic design in memristive crossbars. it Inf. Technol. 65(1-2): 29-39 (2023) - [c674]Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC 2023: 19-25 - [c673]Rune Krauss, Mehran Goli, Rolf Drechsler:
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. ASP-DAC 2023: 423-428 - [c672]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC 2023: 683-689 - [c671]Tim Meywerk, Vladimir Herdt, Rolf Drechsler:
Coverage-Guided Fuzzing for Plan-Based Robotics. ICAART (2) 2023: 106-114 - [c670]Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler:
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. ISQED 2023: 1-8 - [c669]Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler:
Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED 2023: 1-7 - [d3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. Zenodo, 2023
- [i21]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - 2022
- [j146]Vladimir Herdt, Rolf Drechsler:
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. 65(1) (2022) - [j145]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. 14(4): 195-198 (2022) - [j144]Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications. J. Electron. Test. 38(2): 145-163 (2022) - [j143]Saman Fröhlich, Rolf Drechsler:
Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits. it Inf. Technol. 64(3): 99-107 (2022) - [j142]Robert Wille, Rolf Drechsler:
Introduction to the Special Issue on Design Automation for Quantum Computing. ACM J. Emerg. Technol. Comput. Syst. 18(1): 10:1-10:2 (2022) - [j141]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Parallel Computing of Graph-based Functions in ReRAM. ACM J. Emerg. Technol. Comput. Syst. 18(2): 41:1-41:24 (2022) - [j140]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. 126: 102456 (2022) - [j139]F. Lalchhandama, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
CoMIC: Complementary Memristor based in-memory computing in 3D architecture. J. Syst. Archit. 126: 102480 (2022) - [j138]Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
Feed-Forward learning algorithm for resistive memories. J. Syst. Archit. 131: 102730 (2022) - [j137]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. 133: 102757 (2022) - [j136]Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler:
Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems 90: 104487 (2022) - [j135]Mehran Goli, Rolf Drechsler:
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1181-1185 (2022) - [j134]Alireza Mahzoon, Daniel Große, Rolf Drechsler:
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1573-1586 (2022) - [c668]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC 2022: 160-165 - [c667]Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. ASP-DAC 2022: 429-435 - [c666]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA 2022: 77-82 - [c665]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Using density of training data to improve evolutionary algorithms with approximative fitness functions. CEC 2022: 1-10 - [c664]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC 2022: 1177-1182 - [c663]Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler:
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC 2022: 1183-1188 - [c662]Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz:
The Scale4Edge RISC-V Ecosystem. DATE 2022: 808-813 - [c661]Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler:
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. DATE 2022: 1123-1126 - [c660]Saman Fröhlich, Rolf Drechsler:
LiM-HDL: HDL-Based Synthesis for In-Memory Computing. DATE 2022: 1395-1400 - [c659]Rolf Drechsler, Alireza Mahzoon, Mehran Goli:
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS 2022: 1-6 - [c658]Milan Funck, Vladimir Herdt, Rolf Drechsler:
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. DDECS 2022: 14-19 - [c657]Weiyan Zhang, Mehran Goli, Rolf Drechsler:
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. DDECS 2022: 20-25 - [c656]Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler:
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. DDECS 2022: 160-165 - [c655]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. DDECS 2022: 166-171 - [c654]Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier:
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. DSD 2022: 134-141 - [c653]Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Polynomial Formal Verification of Approximate Adders. DSD 2022: 761-768 - [c652]Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler:
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. DSD 2022: 769-776 - [c651]Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler:
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. DSD 2022: 793-800 - [c650]Saman Fröhlich, Rolf Drechsler:
Generation of Verified Programs for In-Memory Computing. DSD 2022: 815-820 - [c649]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. ETS 2022: 1-2 - [c648]Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. FDL 2022: 1-8 - [c647]Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler:
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. FDL 2022: 1-6 - [c646]Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler:
3D Visualization of Symbolic Execution Traces. FDL 2022: 1-8 - [c645]Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD 2022: 1-10 - [c644]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Adapting mutation and recombination operators to range-aware relations in real-world application data. GECCO Companion 2022: 755-758 - [c643]Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler:
Mapping Quantum Circuits to 2-Dimensional Quantum Architectures. GI-Jahrestagung 2022: 1109-1120 - [c642]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI 2022: 97-103 - [c641]Pascal Pieper, Vladimir Herdt, Rolf Drechsler:
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. ACM Great Lakes Symposium on VLSI 2022: 193-197 - [c640]Rolf Drechsler, Alireza Mahzoon:
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. ICCAD 2022: 70:1-70:9 - [c639]Philipp Niemann, Rolf Drechsler:
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. ISMVL 2022: 9-14 - [c638]Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler:
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture. ISMVL 2022: 35-42 - [c637]Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Polynomial Formal Verification of Approximate Functions. ISVLSI 2022: 92-97 - [c636]Sebastian Huhn, Rolf Drechsler:
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. ITC 2022: 609-618 - [c635]Rolf Drechsler:
Fast and Exact is Doable: Polynomial Algorithms in Test and Verification. LATS 2022: 1-2 - [c634]Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt, Rolf Drechsler:
Simulation-Based Debugging of Formal Environment Models. MED 2022: 890-895 - [c633]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling. MLCAD 2022: 103-109 - [c632]Görschwin Fey, Martin Fränzle, Rolf Drechsler:
Self-Explanation in Systems of Systems. RE Workshops 2022: 85-91 - [c631]Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP 2022: 22-28 - [c630]Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler:
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. VLSI-SoC 2022: 1-6 - [c629]Rolf Drechsler, Alireza Mahzoon:
Preserving Design Hierarchy Information for Polynomial Formal Verification. VLSI-SoC 2022: 1-7 - [c628]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. VTS 2022: 1-7 - [p5]Serge Autexier, Christoph Lüth, Rolf Drechsler:
Das Bremen Ambient Assisted Living Lab und darüber hinaus - Intelligente Umgebungen, smarte Services und Künstliche Intelligenz in der Medizin für den Menschen. Künstliche Intelligenz im Gesundheitswesen 2022: 835-850 - [d2]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. Zenodo, 2022 - [i20]Mehran Goli, Rolf Drechsler:
Simulation-based Verification of SystemC-based VPs at the ESL. CoRR abs/2202.08046 (2022) - [i19]Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler:
Lower Bound Proof for the Size of BDDs representing a Shifted Addition. CoRR abs/2209.12477 (2022) - 2021
- [j133]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. 13(4): 202-205 (2021) - [j132]Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman:
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integr. 76: 40-54 (2021) - [j131]Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
An ant colony based mapping of quantum circuits to nearest neighbor architectures. Integr. 78: 11-24 (2021) - [j130]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116: 102135 (2021) - [c627]Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler:
Mutation-based Compliance Testing for RISC-V. ASP-DAC 2021: 55-60 - [c626]Mehran Goli, Rolf Drechsler:
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. ASP-DAC 2021: 67-72 - [c625]Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler:
One-pass Synthesis for Field-coupled Nanocomputing Technologies. ASP-DAC 2021: 574-580 - [c624]Muhammad Hassan, Daniel Große, Rolf Drechsler:
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. ASP-DAC 2021: 761-766 - [c623]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Prefix Adders. ATS 2021: 85-90 - [c622]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Improving Evolutionary Algorithms by Enhancing an Approximative Fitness Function through Prediction Intervals. CEC 2021: 127-135 - [c621]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Domain-driven Correlation-aware Recombination and Mutation Operators for Complex Real-world Applications. CEC 2021: 540-548 - [c620]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress. CODES+ISSS 2021: 29-30 - [c619]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. DAC 2021: 667-672 - [c618]Alireza Mahzoon, Rolf Drechsler:
Late Breaking Results: Polynomial Formal Verification of Fast Adders. DAC 2021: 1376-1377 - [c617]Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler:
Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures. DATE 2021: 200-205 - [c616]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. DATE 2021: 218-221 - [c615]Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE 2021: 1110-1115 - [c614]Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer:
Nano Security: From Nano-Electronics to Secure Systems. DATE 2021: 1334-1339 - [c613]Muhammad Hassan, Daniel Große, Rolf Drechsler:
System Level Verification of Phase-Locked Loop using Metamorphic Relations. DATE 2021: 1378-1381 - [c612]Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar:
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE 2021: 1905-1914 - [c611]Rolf Drechsler:
PolyAdd: Polynomial Formal Verification of Adder Circuits. DDECS 2021: 99-104 - [c610]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. DFT 2021: 1-6 - [c609]Philipp Niemann, Luca Müller, Rolf Drechsler:
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation. DSD 2021: 495-501 - [c608]Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD 2021: 519-526 - [c607]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. DTIS 2021: 1-4 - [c606]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. FDL 2021: 1-7 - [c605]Mehran Goli, Rolf Drechsler:
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. FDL 2021: 1-8 - [c604]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. FDL 2021: 1-7 - [c603]Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler:
ALF: a fitness-based artificial life form for evolving large-scale neural networks. GECCO Companion 2021: 225-226 - [c602]Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler:
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level. ACM Great Lakes Symposium on VLSI 2021: 321-326 - [c601]Mehran Goli, Rolf Drechsler:
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. ICCAD 2021: 1-8 - [c600]Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große:
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. ISCAS 2021: 1-5 - [c599]Philipp Niemann, Rolf Drechsler:
Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic. ISMVL 2021: 178-182 - [c598]Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Depth Optimized Synthesis of Symmetric Boolean Functions. ISVLSI 2021: 61-66 - [c597]Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler:
Polynomial word-level verification of arithmetic circuits. MEMOCODE 2021: 1-9 - [c596]Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Performance Aspects of Correctness-oriented Synthesis Flows. MODELSWARD 2021: 76-86 - [c595]Philipp Niemann, Luca Müller, Rolf Drechsler:
Finding Optimal Implementations of Non-native CNOT Gates Using SAT. RC 2021: 242-255 - [c594]Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC 2021: 1-6 - [p4]Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä:
Non-Clausal SAT and ATPG. Handbook of Satisfiability 2021: 1047-1086 - [d1]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. Zenodo, 2021 - [i18]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs. CoRR abs/2102.02645 (2021) - [i17]Rolf Drechsler:
Polynomial Circuit Verification using BDDs. CoRR abs/2104.03024 (2021) - [i16]Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler:
ALF - A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks. CoRR abs/2104.08252 (2021) - 2020
- [j129]Frank Sill Torres, Philipp Niemann, Robert Wille, Rolf Drechsler:
Near Zero-Energy Computation Using Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 16(1): 11:1-11:16 (2020) - [j128]Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler:
RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. 109: 101756 (2020) - [j127]