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ORCID10th ReCoSoC 2015: Bremen, Germany
- 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 29 - July 1, 2015. IEEE 2015, ISBN 978-1-4673-7942-7
- Stefan Werner, Dennis Heinrich, Jannik Piper, Sven Groppe
, Rico Backasch, Christopher Blochwitz, Thilo Pionteck:
Automated composition and execution of hardware-accelerated operator graphs. 1-8 - Pietro Saltarelli, Behrad Niazmand, Ranganathan Hariharan, Jaan Raik, Gert Jervan, Thomas Hollstein:
Automated minimization of concurrent online checkers for Network-on-Chips. 1-8 - Osvaldo Navarro, Tim Leiding, Michael Hübner:
Configurable cache tuning with a victim cache. 1-6 - Wolfgang Büter, Yanqiu Huang, Daniel Gregorek, Alberto García Ortiz:
A decentralised, autonomous, and congestion-aware thermal monitoring infrastructure for photonic network-on-chip. 1-8 - Boyang Du, Luca Sterpone, Lorenzo Venditti, David Merodio Codinachs:
On the design of highly reliable system-on-chip using dynamically reconfigurable FPGAs. 1-6 - Elisabeth Glocker, Qingqing Chen, Asheque M. Zaidi, Ulf Schlichtmann, Doris Schmitt-Landsiedel:
Emulation of an ASIC power and temperature monitor system for FPGA prototyping. 1-8 - Robin Bonamy, Sébastien Bilavarn, Fabrice Muller:
An energy-aware scheduler for dynamically reconfigurable multi-core systems. 1-6 - Sobhan Niknam, Arghavan Asad, Mahmood Fathy, Amir-Mohammad Rahmani:
Energy efficient 3D Hybrid processor-memory architecture for the dark silicon age. 1-8 - Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Execution modeling in self-aware FPGA-based architectures for efficient resource management. 1-8 - Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. 1-7 - Timm Friedrich, Kurt Franz Ackermann:
A flexible co-processing approach for SoC-FPGAs based on dynamic partial reconfiguration and bitstream relocation methods. 1-7 - Fynn Schwiegelshohn, Lars Gierke, Michael Hübner:
FPGA based traffic sign detection for automotive camera systems. 1-6 - Parham Haririan, Alberto García Ortiz:
A framework for hardware-based DVFS management in multicore mixed-criticality systems. 1-7 - A. Amalin Prince, Vineeth Kartha:
A framework for remote and adaptive partial reconfiguration of SoC based data acquisition systems under Linux. 1-5 - Yunfeng Ma, Leandro Soares Indrusiak:
Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip. 1-8 - Dennis Heinrich, Stefan Werner, Marc Stelzner, Christopher Blochwitz, Thilo Pionteck, Sven Groppe:
Hybrid FPGA approach for a B+ tree in a Semantic Web database system. 1-8 - Thomas Hollstein, Siavoosh Payandeh Azad, Thilo Kogge, Behrad Niazmand:
Mixed-criticality NoC partitioning based on the NoCDepend dependability technique. 1-8 - Charlotte Frenkel, Jean-Didier Legat, David Bol:
A Partial Reconfiguration-based scheme to mitigate Multiple-Bit Upsets for FPGAs in low-cost space applications. 1-7 - Wolfgang Büter, Christof Osewold, Awais Ahmed, Daniel Gregorek, Alberto García Ortiz:
Predictable photonic interconnects using an autonomous channel management and a TDMA-NoC. 1-6 - Arash Firuzan, Mehdi Modarressi, Masoud Daneshtalab:
Reconfigurable communication fabric for efficient implementation of neural networks. 1-8 - Johanna Sepúlveda, Daniel Florez, Guy Gogniat:
Reconfigurable security architecture for disrupted protection zones in NoC-based MPSoCs. 1-8 - Marco A. Z. Alves, Paulo C. Santos, Matthias Diener, Luigi Carro:
Reconfigurable Vector Extensions inside the DRAM. 1-6 - Zahra Shirmohammadi, Seyed Ghassem Miremadi:
S2AP: An efficient numerical-based crosstalk avoidance code for reliable data transfer of NoCs. 1-6 - Rolf Drechsler, Martin Fränzle, Robert Wille:
Envisioning self-verification of electronic systems. 1-6 - Rémy Druyer, Lionel Torres, Pascal Benoit, Paul-Vincent Bonzom, Patrick Le-Quéré:
A survey on security features in modern FPGAs. 1-8 - Byron Navas, Ingo Sander, Johnny Öberg:
Towards cognitive reconfigurable hardware: Self-aware learning in RTR fault-tolerant SoCs. 1-8 - Karim M. A. Ali, Rabie Ben Atitallah, Nizar Fakhfakh, Jean-Luc Dekeyser:
Using hardware parallelism for reducing power consumption in video streaming applications. 1-7 - Stefan Gehrer, Georg Sigl:
Using the reconfigurability of modern FPGAs for highly efficient PUF-based key generation. 1-6 - Christian de Schryver:
Towards run-time flexible risk management systems on hybrid platforms. 1 - Sergio Montenegro:
Design to survive. 1 - Cédric Lichtenau:
Beyond many-core: Commercial workload acceleration in high-end systems. 1 - Alberto García Ortiz, Daniel Gregorek, Eduardo de la Torre, Juha Plosila:
Message from the chairs. 1
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