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ORCID59th DAC 2022: San Francisco, CA, USA
- Rob Oshana:
DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10 - 14, 2022. ACM 2022, ISBN 978-1-4503-9142-9 - Frontmatter.
- Hanrui Wang, Jiaqi Gu, Yongshan Ding
, Zirui Li, Frederic T. Chong, David Z. Pan, Song Han:
QuantumNAT: quantum noise-aware training with noise injection, quantization and normalization. 1-6 - Cynthia Chen, Bruno Schmitt, Helena Zhang, Lev S. Bishop, Ali Javadi-Abhari:
Optimizing quantum circuit synthesis for permutations using recursion. 7-12 - Sunghye Park, Daeyeon Kim, Minhyuk Kweon, Jae-Yoon Sim, Seokhyeong Kang:
A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers. 13-18 - Hongxiang Fan, Ce Guo, Wayne Luk:
Optimizing quantum circuit placement via machine learning. 19-24 - Huanrui Yang, Xiaoxuan Yang, Neil Zhenqiang Gong, Yiran Chen:
HERO: hessian-enhanced robust optimization for unifying and improving generalization and quantization performance. 25-30 - Mohsen Imani, Ali Zakeri, Hanning Chen, Taehyun Kim, Prathyush Poduval, Hyunsei Lee, Yeseong Kim, Elaheh Sadredini, Farhad Imani:
Neural computation for robust and holographic face detection. 31-36 - Rishikanth Chandrasekaran, Kazim Ergun, Jihyun Lee, Dhanush Nanjunda, Jaeyoung Kang, Tajana Rosing:
FHDnn: communication efficient and robust federated learning for AIoT networks. 37-42 - Ruixuan Wang, Xun Jiao, X. Sharon Hu:
ODHD: one-class brain-inspired hyperdimensional computing for outlier detection. 43-48 - Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao:
High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. 49-54 - Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Automated accelerator optimization aided by graph neural networks. 55-60 - Ziyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang:
Functionality matters in netlist representation learning. 61-66 - Liancheng Jia, Yuyue Wang, Jingwen Leng, Yun Liang:
EMS: efficient memory subsystem synthesis for spatial accelerators. 67-72 - Jiliang Zhang, Lin Ding, Zhuojun Chen, Wenshang Li, Gang Qu:
DA PUF: dual-state analog PUF. 73-78 - Haocheng Ma, Qizhi Zhang, Ya Gao, Jiaji He, Yiqiang Zhao, Yier Jin:
PathFinder: side channel protection through automatic leaky paths identification and obfuscation. 79-84 - Gaurav Kolhe, Tyler David Sheaves, Kevin Immanuel Gubbi, Soheil Salehi, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan, Houman Homayoun:
LOCK&ROLL: deep-learning power side-channel attack mitigation using emerging reconfigurable devices and logic locking. 85-90 - Xiangren Chen, Bohan Yang, Yong Lu, Shouyi Yin, Shaojun Wei, Leibo Liu:
Efficient access scheme for multi-bank based NTT architecture through conflict graph. 91-96 - Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li:
InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCs. 97-102 - Yinyi Liu, Jiaqi Liu, Yuxiang Fu, Shixi Chen, Jiaxu Zhang, Jiang Xu:
PHANES: ReRAM-based photonic accelerator for deep neural networks. 103-108 - He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao:
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory. 109-114 - Liukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun, Xueqing Li, Weifeng He, Shi Xu:
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. 115-120 - Yinxiao Feng, Kaisheng Ma:
Chiplet actuary: a quantitative cost model and multi-chiplet architecture exploration. 121-126 - Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra:
PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA. 127-132 - Zheng Zhang, Tinghuan Chen, Jiaxin Huang, Meng Zhang:
A fast parameter tuning framework via transfer learning and multi-objective bayesian optimization. 133-138 - Nicholas Wendt, Todd M. Austin, Valeria Bertacco:
PriMax: maximizing DSL application performance with selective primitive acceleration. 139-144 - Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone:
Accelerating and pruning CNNs for semantic segmentation on FPGA. 145-150 - Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique:
SoftSNN: low-cost fault tolerance for spiking neural network accelerators under soft errors. 151-156 - Chun-Feng Wu, Carole-Jean Wu, Gu-Yeon Wei, David Brooks:
A joint management middleware to improve training performance of deep recommendation systems with SSDs. 157-162 - Yi Sheng, Junhuan Yang, Yawen Wu, Kevin Mao, Yiyu Shi, Jingtong Hu, Weiwen Jiang, Lei Yang:
The larger the fairer?: small neural networks can achieve fairness for edge devices. 163-168 - Mihaela Damian, Julian Oppermann, Christoph Spang, Andreas Koch:
SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processors. 169-174 - Subhash Sethumurugan, Shashank Hegde, Hari Cherupalli, John Sartori:
A scalable symbolic simulation tool for low power embedded systems. 175-180 - Ran Wei, Zhe Jiang, Xiaoran Guo, Haitao Mei, Athanasios Zolotas, Tim Kelly:
Designing critical systems with iterative automated safety analysis. 181-186 - Amrit Nagarajan, Jacob R. Stevens, Anand Raghunathan:
Efficient ensembles of graph neural networks. 187-192 - Feijie Wu, Shiqi He, Song Guo, Zhihao Qu, Haozhao Wang, Weihua Zhuang, Jie Zhang:
Sign bit is enough: a learning synchronization framework for multi-hop all-reduce with ultimate compression. 193-198 - Jiaqi Li, Min Peng, Qingan Li, Meizheng Peng, Mengting Yuan:
GLite: a fast and efficient automatic graph-level optimizer for large-scale DNNs. 199-204 - Yonggan Fu, Qixuan Yu, Meng Li, Xu Ouyang, Vikas Chandra, Yingyan Lin:
Contrastive quant: quantization makes stronger contrastive learning. 205-210 - Linghao Song, Yuze Chi, Licheng Guo, Jason Cong:
Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication. 211-216 - Jiahao Liu, Zirui Zhong, Yong Zhou, Hui Qiu, Jianbiao Xiao, Jiajing Fan, Zhaomin Zhang, Sixu Li, Yiming Xu, Siqi Yang, Weiwei Shan, Shuisheng Lin, Liang Chang, Jun Zhou:
An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection. 217-222 - Behnam Khaleghi, Uday Mallappa, Duygu Yaldiz, Haichao Yang, Monil Shah, Jaeyoung Kang, Tajana Rosing:
PatterNet: explore and exploit filter patterns for efficient deep neural networks. 223-228 - Zhuoran Song, Zhongkai Yu, Naifeng Jing, Xiaoyao Liang:
E2SR: an end-to-end video CODEC assisted system for super resolution acceleration. 229-234 - Lei Jiang, Qian Lou, Nrushad Joshi:
MATCHA: a fast and energy-efficient accelerator for fully homomorphic encryption over the torus. 235-240 - Jianqiang Wang, Pouya Mahmoody, Ferdinand Brasser, Patrick Jauernig, Ahmad-Reza Sadeghi, Donghui Yu, Dahan Pan, Yuanyuan Zhang:
VirTEE: a full backward-compatible TEE with native live migration and secure I/O. 241-246 - Gregor Haas, Aydin Aysu:
Apple vs. EMA: electromagnetic side channel attacks on apple CoreCrypto. 247-252 - Jaekang Shin, Seungkyu Choi, Jongwoo Ra, Lee-Sup Kim:
Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNN. 253-258 - Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang:
EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networks. 259-264 - Dongwoo Lew, Kyungchul Lee, Jongsun Park:
A time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor design. 265-270 - Fan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Kevin Cao, Deliang Fan:
XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method. 271-276 - Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
SWIM: selective write-verify for computing-in-memory neural accelerators. 277-282 - Xiaoming Zeng, Zhendong Wang, Yang Hu:
Enabling efficient deep convolutional neural network-based sensor fusion for autonomous driving. 283-288 - Yu-Shun Hsiao, Siva Kumar Sastry Hari, Michal Filipiuk, Timothy Tsai, Michael B. Sullivan, Vijay Janapa Reddi, Vasu Singh, Stephen W. Keckler:
Zhuyi: perception processing rate estimation for safety in autonomous vehicles. 289-294 - Yuquan He, Songyun Qu, Gangliang Lin, Cheng Liu, Lei Zhang, Ying Wang:
Processing-in-SRAM acceleration for ultra-low power visual 3D perception. 295-300 - Abdullah Al Arafat, Sudharsan Vaidhun, Kurt M. Wilson, Jinghao Sun, Zhishan Guo:
Response time analysis for dynamic priority scheduling in ROS2. 301-306 - Jiwon Kim, Seunghyeok Jeon, Jaehyun Kim, Hojung Cha:
Voltage prediction of drone battery reflecting internal temperature. 307-312 - Weihong Xu, Jaeyoung Kang, Tajana Rosing:
A near-storage framework for boosted data preprocessing of mass spectrum clustering. 313-318 - Ruihao Gao, Xueqi Li, Yewen Li, Xun Wang, Guangming Tan:
MetaZip: a high-throughput and efficient accelerator for DEFLATE. 319-324 - Hongxiang Fan, Martin Ferianc, Wayne Luk:
Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations. 325-330 - Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao:
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform. 331-336 - Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao:
GEML: GNN-based efficient mapping method for large loop applications on CGRA. 337-342 - Jinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin:
Mixed-granularity parallel coarse-grained reconfigurable architecture. 343-348 - Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh:
GuardNN: secure accelerator architecture for privacy-preserving deep learning. 349-354 - Lei Zhao, Youtao Zhang, Jun Yang:
SRA: a secure ReRAM-based DNN accelerator. 355-360 - Liyan Shen, Ye Dong, Binxing Fang, Jinqiao Shi, Xuebin Wang, Shengli Pan, Ruisheng Shi:
ABNN2: secure two-party arbitrary-bitwidth quantized neural network predictions. 361-366 - Prathyush Poduval, Yang Ni, Yeseong Kim, Kai Ni, Raghavan Kumar, Rosario Cammarota, Mohsen Imani:
Adaptive neural recovery for highly robust brain-like representation. 367-372 - Sarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy, Anand Raghunathan:
Efficiency attacks on spiking neural networks. 373-378 - Ji Zhang, Xijun Li, Xiyao Zhou, Mingxuan Yuan, Zhuo Cheng, Keji Huang, Yifan Li:
L-QoCo: learning to optimize cache capacity overloading in storage systems. 379-384 - Shuhan Bai, Hu Wan, Yun Huang, Xuan Sun, Fei Wu, Changsheng Xie, Hung-Chih Hsieh, Tei-Wei Kuo, Chun Jason Xue:
Pipette: efficient fine-grained reads for SSDs. 385-390 - Longfei Luo, Dingcui Yu, Liang Shi, Chuanming Ding, Changlong Li, Edwin H.-M. Sha:
CDB: critical data backup design for consumer devices with high-density flash based hybrid storage. 391-396 - Chunhua Li, Man Wu, Yuhan Liu, Ke Zhou, Ji Zhang, Yunqing Sun:
SS-LRU: a smart segmented LRU caching. 397-402 - Haoran Dang, Chongnan Ye, Yanpeng Hu, Chundong Wang:
NobLSM: an LSM-tree with non-blocking writes for SSDs. 403-408 - Jaeyong Lee, Myungsuk Kim, Wonil Choi, Sanggu Lee, Jihong Kim:
TailCut: improving performance and lifetime of SSDs using pattern-aware state encoding. 409-414 - Xing Li, Lei Chen, Fan Yang, Mingxuan Yuan, Hongli Yan, Yupeng Wan:
HIMap: a heuristic and iterative logic synthesis approach. 415-420 - Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon:
Improving LUT-based optimization for ASICs. 421-426 - Shiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young:
NovelRewrite: node-level parallel AIG rewriting. 427-432 - Linus Witschen, Tobias Wiersema, Lucas Reuter, Marco Platzner:
Search space characterization for approximate logic synthesis. 433-438 - Chang Meng, Xuan Wang, Jiajun Sun, Sijun Tao, Wei Wu, Zhihang Wu, Leibin Ni, Xiaolong Shen, Junfeng Zhao, Weikang Qian:
SEALS: sensitivity-driven efficient approximate logic synthesis. 439-444 - Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Beyond local optimality of buffer and splitter insertion for AQFP circuits. 445-450 - Shubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy:
NAX: neural architecture and memristive xbar based accelerator co-design. 451-456 - Zhiheng Yue, Yabing Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computation. 457-462 - Mengyuan Li, Ann Franchesca Laguna, Dayane Reis, Xunzhao Yin, Michael T. Niemier, X. Sharon Hu:
iMARS: an in-memory-computing architecture for recommendation systems. 463-468 - Cong Liu, Haikun Liu, Hai Jin, Xiaofei Liao, Yu Zhang, Zhuohui Duan, Jiahong Xu, Huize Li:
ReGNN: a ReRAM-based heterogeneous architecture for general graph neural networks. 469-474 - Xiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Weichen Liu:
You only search once: on lightweight differentiable architecture search for resource-constrained embedded platforms. 475-480 - Arnav Vaibhav Malawade, Trier Mortlock, Mohammad Abdullah Al Faruque:
EcoFusion: energy-aware adaptive sensor fusion for efficient autonomous vehicle perception. 481-486 - Yijie Wei, Zhiwei Zhong, Jie Gu:
Human emotion based real-time memory and computation management on resource-limited edge devices. 487-492 - Zihan Wang, Chengcheng Wan, Yuting Chen, Ziyi Lin, He Jiang, Lei Qiao:
Hierarchical memory-constrained operator scheduling of neural architecture search networks. 493-498 - Abhiroop Bhattacharjee, Yeshwanth Venkatesha, Abhishek Moitra, Priyadarshini Panda:
MIME: adapting a single neural network for multi-task inference with memory-efficient dynamic pruning. 499-504 - Weihong Liu, Jiawei Geng, Zongwei Zhu, Jing Cao, Zirui Lian:
Sniper: cloud-edge collaborative inference scheduling with neural network similarity modeling. 505-510 - Yibin Gu, Yifan Li, Hua Wang, Li Liu, Ke Zhou, Wei Fang, Gang Hu, Jinhu Liu, Zhuo Cheng:
LPCA: learned MRC profiling based cache allocation for file storage systems. 511-516 - Tom Peham, Lukas Burgholzer, Robert Wille:
Equivalence checking paradigms in quantum circuit design: a case study. 517-522 - Chun-Yu Wei, Yuan-Hung Tsai, Chiao-Shan Jhang, Jie-Hong R. Jiang:
Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verification. 523-528 - Lukas Burgholzer, Robert Wille:
Handling non-unitaries in quantum circuit equivalence checking. 529-534 - Wei-Hsiang Tseng, Yao-Wen Chang:
A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits. 535-540 - Tuo Li, Sri Parameswaran:
FaSe: fast selective flushing to mitigate contention-based cache timing attacks. 541-546 - Peinan Li, Rui Hou, Lutan Zhao, Yifan Zhu, Dan Meng:
Conditional address propagation: an efficient defense mechanism against transient execution attacks. 547-552 - Anirban Chakraborty, Nikhilesh Singh, Sarani Bhattacharya, Chester Rebeiro, Debdeep Mukhopadhyay:
Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures. 553-558 - Fan Zhang, Zhiyong Wang, Haoting Shen, Bolin Yang, Qianmei Wu, Kui Ren:
DARPT: defense against remote physical attack based on TDC in multi-tenant scenario. 559-564 - Sudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar:
GNNIE: GNN inference engine with load-balancing and graph-specific caching. 565-570 - Guan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo:
SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequences. 571-576 - Joonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong Hyun Lee, Jungwook Choi:
NN-LUT: neural approximation of non-linear operations for efficient transformer inference. 577-582 - Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna:
Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML. 583-588 - Deokki Hong, Kanghyun Choi, Hyeyoon Lee, Joonsang Yu, Noseong Park, Youngsok Kim, Jinho Lee:
Enabling hard constraints in differentiable neural network and accelerator co-exploration. 589-594 - Guohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, Yu Wang:
Heuristic adaptability to input dynamics for SpMM on CPUs. 595-600 - Xinyi Zhang, Cong Hao, Peipei Zhou, Alex K. Jones, Jingtong Hu:
H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness. 601-606 - Yunseong Kim, Yujeong Choi, Minsoo Rhu:
PARIS and ELSA: an elastic scheduling algorithm for reconfigurable multi-GPU inference servers. 607-612 - Zhiqiang Liu, Wenjian Yu:
Pursuing more effective graph spectral sparsifiers via approximate trace reduction. 613-618 - Zhou Jin, Haojie Pei, Yichao Dong, Xiang Jin, Xiao Wu, Wei W. Xing, Dan Niu:
Accelerating nonlinear DC circuit simulation with reinforcement learning. 619-624 - Xiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng:
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling. 625-630 - Jinwei Liu, Xiaopeng Zhang, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
Partition and place finite element model on wafer-scale engine. 631-636 - Huimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang:
CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. 637-642 - Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang:
High-performance placement for large-scale heterogeneous FPGAs with clock constraints. 643-648 - Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin:
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility. 649-654 - Hanrui Wang, Zirui Li, Jiaqi Gu, Yongshan Ding, David Z. Pan, Song Han:
QOC: quantum on-chip training with parameter shift and gradient pruning. 655-660 - Mikail Yayla, Jian-Jia Chen:
Memory-efficient training of binarized neural networks on the edge. 661-666 - Min Li, Sadaf Khan, Zhengyuan Shi, Naixing Wang, Huang Yu, Qiang Xu:
DeepGate: learning neural representations of logic gates. 667-672 - Suyong Lee, Insu Choi, Joon-Sung Yang:
Bipolar vector classifier for fault-tolerant deep neural networks. 673-678 - Shijin Duan, Shaolei Ren, Xiaolin Xu:
HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealing. 679-684 - Junge Xu, Bohan Xuan, Anlin Liu, Mo Sun, Fan Zhang, Zeke Wang, Kui Ren:
Terminator on SkyNet: a practical DVFS attack on DNN hardware IP for UAV object detection. 685-690 - Pei Cao, Hongyi Zhang, Dawu Gu, Yan Lu, Yidong Yuan:
AL-PA: cross-device profiled side-channel attack using adversarial learning. 691-696 - Vasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan (JV) Rajendran:
DETERRENT: detecting trojans using reinforcement learning. 697-702 - Jinxi Kuang, Minghua Shen, Yutong Lu, Nong Xiao:
Exploiting data locality in memory for ORAM to reduce memory access overheads. 703-708 - Hsu-Kang Dow, Tuo Li, Sri Parameswaran:
HWST128: complete memory safety accelerator on RISC-V with metadata compression. 709-714 - Jinyan Xu, Haoran Lin, Ziqi Yuan, Wenbo Shen, Yajin Zhou, Rui Chang, Lei Wu, Kui Ren:
RegVault: hardware assisted selective data randomization for operating system kernels. 715-720 - Adam Caulfield, Norrathep Rattanavipanon, Ivan De Oliveira Nunes:
ASAP: reconciling asynchronous real-time operations and proofs of execution in simple embedded systems. 721-726 - Lucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz:
Towards a formally verified hardware root-of-trust for data-oblivious computing. 727-732 - Huimin Li, Nele Mentens, Stjepan Picek:
A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyber. 733-738 - Marcel Walter, Samuel Sze Hang Ng, Konrad Walus, Robert Wille:
Hexagons are the bestagons: design automation for silicon dangling bond logic. 739-744 - Brian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury:
Improving compute in-memory ECC reliability with successive correction. 745-750 - Jiahao Cai, Mohsen Imani, Kai Ni, Grace Li Zhang, Bing Li, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin:
Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memory. 751-756 - Yuqiao Zhang, Chunli Tang, Peng Li, Ujjwal Guin:
CamSkyGate: camouflaged skyrmion gates for protecting ICs. 757-762 - Weiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao:
GNN-based concentration prediction for random microfluidic mixers. 763-768 - Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers:
Designing ML-resilient locking at register-transfer level. 769-774 - M. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mohamed Abdel-Moneum, Mark M. Tehranipoor:
O'clock: lock the clock via clock-gating for SoC IP protection. 775-780 - Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato:
ALICE: an automatic design flow for eFPGA redaction. 781-786 - Nishant Gupta, Mohil Sandip Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar:
DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysis. 787-792 - Aritra Bhattacharyay, Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia:
VIPR-PCB: a machine learning based golden-free PCB assurance framework. 793-798 - Zhuohui Duan, Haobo Wang, Haikun Liu, Xiaofei Liao, Hai Jin, Yu Zhang, Fubing Mao:
CLIMBER: defending phase change memory against inconsistent write attacks. 799-804 - Sung-Ming Wu, Li-Pin Chang:
Rethinking key-value store for byte-addressable optane persistent memory. 805-810 - Feng Ren, Kang Chen, Yongwei Wu:
libcrpm: improving the checkpoint performance of NVM. 811-816 - Ming Zhang, Yu Hua, Xuan Li, Hao Xu:
Scalable crash consistency for secure persistent memory. 817-822 - Yongho Lee, Osang Kwon, Seokin Hong:
Don't open row: rethinking row buffer policy for improving performance of non-volatile memories. 823-828 - Xiangjun Peng, Ming-Chang Yang, Ho Ming Tsui, Chi Ngai Leung, Wang Kang:
SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory. 829-834 - Yujuan Tan, Wei Chen, Zhulin Ma, Dan Xiao, Zhichao Yan, Duo Liu, Xianzhang Chen:
SAPredictor: a simple and accurate self-adaptive predictor for hierarchical hybrid memory system. 835-840 - Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS. 841-846 - Shiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris:
A defect tolerance framework for improving yield. 847-852 - Xinghua Xue, Haitong Huang, Cheng Liu, Tao Luo, Lei Zhang, Ying Wang:
Winograd convolution: a perspective from fault tolerance. 853-858 - Muhammad Rashedul Haq Rashed, Amro Awad, Sumit Kumar Jha, Rickard Ewetz:
Towards resilient analog in-memory deep learning via data layout re-organization. 859-864 - Zhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen:
SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS process. 865-870 - Valentin Poirot, Oliver Harms, Hendric Martens, Olaf Landsiedel:
BlueSeer: AI-driven environment detection via BLE scans. 871-876 - Yujun Huang, Bin Chen, Jianghui Zhang, Han Qiu, Shu-Tao Xia:
Compressive sensing based asymmetric semantic image compression for resource-constrained IoT system. 877-882 - Diansen Sun, Yunpeng Chai, Chaoyang Liu, Weihao Sun, Qingpeng Zhang:
R2B: high-efficiency and fair I/O scheduling for multi-tenant with differentiated demands. 883-888 - Sizhe An, Ümit Y. Ogras:
Fast and scalable human pose estimation using mmWave point cloud. 889-894 - Benoît W. Denkinger, Miguel Peón Quirós, Mario Konijnenburg, David Atienza, Francky Catthoor:
VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices. 895-900 - Haiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie:
Alleviating datapath conflicts and design centralization in graph analytics acceleration. 901-906 - Mike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum:
Hyperdimensional hashing: a robust and efficient dynamic hash table. 907-912 - Maimaiti Nazhamaiti, Haijin Su, Han Xu, Zheyu Liu, Fei Qiao, Qi Wei, Zidong Du, Xinghua Yang, Li Luo:
In-situ self-powered intelligent vision system with inference-adaptive energy scheduling for BNN-based always-on perception. 913-918 - Lin Zhang, Zifan Wang, Mengyu Liu, Fanxin Kong:
Adaptive window-based sensor attack detection for cyber-physical systems. 919-924 - Yixuan Wang, Chao Huang, Zhaoran Wang, Zhilu Wang, Qi Zhu:
Design-while-verify: correct-by-construction control learning with verification in the loop. 925-930 - Jiajie Chen, Le Yang, Youhui Zhang:
GaBAN: a generic and flexibly programmable vector neuro-processor on FPGA. 931-936 - Jiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, David Z. Pan:
ADEPT: automatic differentiable DEsign of photonic tensor cores. 937-942 - Zhijie Yang, Lei Wang, Yao Wang, LingHui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, Weixia Xu:
Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neurons. 943-948 - Hoon Shin, Rihae Park, Seung Yul Lee, Yeonhong Park, Hyunseung Lee, Jae W. Lee:
Effective zero compression on ReRAM-based sparse DNN accelerators. 949-954 - Szu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang:
Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. 955-960 - Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen:
Towards collaborative intelligence: routability estimation based on decentralized private data. 961-966 - Qijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young:
A2-ILT: GPU accelerated ILT with spatial attention mechanism. 967-972 - Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren:
Generic lithography modeling with dual-band optics-inspired neural networks. 973-978 - Bonan Zhang, Peter Deaville, Naveen Verma:
Statistical computing framework and demonstration for in-memory computing systems. 979-984 - Ziqi Meng, Yanan Sun, Weikang Qian:
Write or not: programming scheme optimization for RRAM-based neuromorphic computing. 985-990 - Huize Li, Hai Jin, Long Zheng, Yu Huang, Xiaofei Liao, Zhuohui Duan, Dan Chen, Chuangyi Gui:
ReSMA: accelerating approximate string matching using ReRAM-based content addressable memory. 991-996 - Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li:
VStore: in-storage graph based vector search accelerator. 997-1002 - Shuyuan Yu, Sheldon X.-D. Tan:
Scaled-CBSC: scaled counting-based stochastic computing multiplication for improved accuracy. 1003-1008 - Xingchen Li, Zhihang Yuan, Guangyu Sun, Liang Zhao, Zhichao Lu:
Tailor: removing redundant operations in memristive analog neural network accelerators. 1009-1014 - Weidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma:
Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimization. 1015-1020 - Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen:
A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. 1021-1026 - Hiago Mayk G. de A. Rocha, Janaina Schwarzrock, Arthur Francisco Lorenzon, Antonio Carlos Schneider Beck:
Using machine learning to optimize graph execution on NUMA machines. 1027-1032 - Zhuo Su, Zehong Yu, Dongyan Wang, Yixiao Yang, Yu Jiang, Rui Wang, Wanli Chang, Jia-Guang Sun:
HCG: optimizing embedded code generation of simulink with SIMD instruction synthesis. 1033-1038 - Hongyi Lu, Fengwei Zhang:
Raven: a novel kernel debugging tool on RISC-V. 1039-1044 - Qi Sun, Xinyun Zhang, Hao Geng, Yuxuan Zhao, Yang Bai, Haisheng Zheng, Bei Yu:
GTuner: tuning DNN computations on GPU via graph attention network. 1045-1050 - Quentin Huppert, Francky Catthoor, Lionel Torres, David Novo:
Pref-X: a framework to reveal data prefetching in commercial in-order cores. 1051-1056 - Xin Xin, Wanyi Zhu, Li Zhao:
Architecting DDR5 DRAM caches for non-volatile memory systems. 1057-1062 - Zerun Li, Xiaoming Chen, Yinhe Han:
GraphRing: an HMC-ring based graph processing framework with optimized data movement. 1063-1068 - Ismet Dagli, Alexander Cieslewicz, Jedidiah McClurg, Mehmet E. Belviranli:
AxoNN: energy-aware execution of neural network inference on multi-accelerator heterogeneous SoCs. 1069-1074 - Nezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad:
PIPF-DRAM: processing in precharge-free DRAM. 1075-1080 - Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim:
TAIM: ternary activation in-memory computing hardware with 6T SRAM array. 1081-1086 - Fangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Zhezhi He, Rui Yang, Qidong Tang, Tao Yang, Cheng Zhuo, Li Jiang:
PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing acceleration. 1087-1092 - Yiming Chen, Guodong Yin, Zhanhong Tan, Mingyen Lee, Zekun Yang, Yongpan Liu, Huazhong Yang, Kaisheng Ma, Xueqing Li:
YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip. 1093-1098 - Ziru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen:
ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses. 1099-1104 - Fangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, Li Jiang:
SATO: spiking neural network acceleration via temporal-oriented dataflow and architecture. 1105-1110 - Shijin Duan, Yejia Liu, Shaolei Ren, Xiaolin Xu:
LeHDC: learning-based hyperdimensional computing classifier. 1111-1116 - Behnam Khaleghi, Jaeyoung Kang, Hanyang Xu, Justin Morris, Tajana Rosing:
GENERIC: highly efficient learning engine on edge using hyperdimensional computing. 1117-1122 - Qichao Tao, Jie Han:
Solving traveling salesman problems via a parallel fully connected ising machine. 1123-1128 - Sven Thijssen, Sumit Kumar Jha, Rickard Ewetz:
PATH: evaluation of boolean logic using path-based in-memory computing. 1129-1134 - Hongwu Peng, Shaoyi Huang, Shiyang Chen, Bingbing Li, Tong Geng, Ang Li, Weiwen Jiang, Wujie Wen, Jinbo Bi, Hang Liu, Caiwen Ding:
A length adaptive algorithm-hardware co-design of transformer on FPGA through sparse attention and dynamic pipelining. 1135-1140 - Yang Ni, Mariam Issa, Danny Abraham, Mahdi Imani, Xunzhao Yin, Mohsen Imani:
HDPG: hyperdimensional policy-based reinforcement learning for continuous control. 1141-1146 - Soobee Lee, Minindu Weerakoon, Jonghyun Choi, Minjia Zhang, Di Wang, Myeongjae Jeon:
CarM: hierarchical episodic memory for continual learning. 1147-1152 - Guyue Huang, Haoran Li, Minghai Qin, Fei Sun, Yufei Ding, Yuan Xie:
Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruning. 1153-1158 - Jongho Park, Hyukjun Kwon, Seowoo Kim, Junyoung Lee, Minho Ha, Euicheol Lim, Mohsen Imani, Yeseong Kim:
QuiltNet: efficient deep learning inference on multi-chip accelerators using model partitioning. 1159-1164 - Byung Hoon Ahn, Sean Kinzer, Hadi Esmaeilzadeh:
Glimpse: mathematical embedding of hardware specification for neural compilation. 1165-1170 - Keyi Zhang, Zain Asgar, Mark Horowitz:
Bringing source-level debugging frameworks to hardware generators. 1171-1176 - Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. 1177-1182 - Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler:
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. 1183-1188 - Gaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, Tejas Kadale, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan, Hamid Mahmoodi, Houman Homayoun:
Silicon validation of LUT-based logic-locked IP cores. 1189-1194 - Shuo Yin, Xiang Jin, Linxu Shi, Kang Wang, Wei W. Xing:
Efficient bayesian yield analysis and optimization with active learning. 1195-1200 - Jun Xia, Ming Hu, Xin Chen, Mingsong Chen:
Accelerated synthesis of neural network-based barrier certificates using collaborative learning. 1201-1206 - Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin:
A timing engine inspired graph neural network model for pre-routing slack prediction. 1207-1212 - Xu He, Zhiyong Fu, Yao Wang, Chang Liu, Yang Guo:
Accurate timing prediction at placement stage with look-ahead RC network. 1213-1218 - Kevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang:
Timing macro modeling with graph neural networks. 1219-1224 - Xiao Dong, Yufei Chen, Xunzhao Yin, Cheng Zhuo:
Worst-case dynamic power distribution network noise prediction using convolutional neural network. 1225-1230 - Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany:
GATSPI: GPU accelerated gate-level simulation for power improvement. 1231-1236 - Hao Geng, Qi Xu, Tsung-Yi Ho, Bei Yu:
PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learning. 1237-1242 - Ran Bi, Xinbin Liu, Jiankang Ren, Pengfei Wang, Huawei Lv, Guozhen Tan:
Efficient maximum data age analysis for cause-effect chains in automotive systems. 1243-1248 - Zhao Gu, Rodolfo Pellizzoni:
Optimizing parallel PREM compilation over nested loop structures. 1249-1254 - Yang Wang, Xu Jiang, Nan Guan, Mingsong Lv, Dong Ji, Wang Yi:
Scheduling and analysis of real-time tasks with parallel critical sections. 1255-1260 - Zhe Jiang, Kecheng Yang, Neil C. Audsley, Nathan Fisher, Weisong Shi, Zheng Dong:
BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCs. 1261-1266 - Wei Zhang, Mingsong Lv, Wanli Chang, Lei Ju:
Precise and scalable shared cache contention analysis for WCET estimation. 1267-1272 - Zhuanhao Wu, Hiren D. Patel:
Predictable sharing of last-level cache partitions for multi-core safety-critical systems. 1273-1278 - Yu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang:
Thermal-aware optical-electrical routing codesign for on-chip signal communications. 1279-1284 - Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. 1285-1290 - Mohit Upadhyay, Rohan Juneja, Bo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh:
REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables. 1291-1296 - Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng:
LHNN: lattice hypergraph neural network for VLSI congestion prediction. 1297-1302 - Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Floorplanning with graph attention. 1303-1308 - Lixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young:
Xplace: an extremely fast and extensible global placement framework. 1309-1314 - Zizheng Guo, Yibo Lin:
Differentiable-timing-driven global placement. 1315-1320 - Peiyan Dong, Yanyue Xie, Hongjia Li, Mengshu Sun, Olivia Chen, Nobuyuki Yoshikawa, Yanzhi Wang:
TAAS: a timing-aware analytical strategy for AQFP-capable placement automation. 1321-1326 - Gobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy:
A cross-layer approach to cognitive computing: invited. 1327-1330 - Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren:
Generative self-supervised learning for gate sizing: invited. 1331-1334 - Harrison Liew, Daniel Grubb, John Wright, Colin Schmidt, Nayiri Krzysztofowicz, Adam M. Izraelevitz, Edward Wang, Krste Asanovic, Jonathan Bachrach, Borivoje Nikolic:
Hammer: a modular and reusable physical design flow tool: invited. 1335-1338 - Alex Carsello, James Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng:
mflowgen: a modular flow generator and ecosystem for community-driven physical design: invited. 1339-1342 - Andreas Olofsson, William Ransohoff, Noah Moroze:
A distributed approach to silicon compilation: invited. 1343-1346 - Yunsheng Bai, Atefeh Sohrabizadeh, Yizhou Sun, Jason Cong:
Improving GNN-based accelerator design automation with meta learning. 1347-1350 - Debjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang:
Accelerator design with decoupled hardware customizations: benefits and challenges: invited. 1351-1354 - Hanchen Ye, HyeGang Jun, Hyunmin Jeong, Stephen Neuendorffer, Deming Chen:
ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited. 1355-1358 - Nicolas Bohm Agostini, Serena Curzel, Ankur Limaye, Vinay Amatya, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Fabrizio Ferrandi:
The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invited. 1359-1362 - Mathias Soeken, Mariia Mykhailova:
Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passes. 1363-1366 - Robert Wille, Lukas Burgholzer, Stefan Hillmich, Thomas Grurl, Alexander Ploier, Tom Peham:
The basis of design tools for quantum computing: arrays, decision diagrams, tensor networks, and ZX-calculus. 1367-1370 - Md Rafid Muttaki, Zahin Ibnat, Farimah Farahmandi:
Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invited. 1371-1374 - Christian Pilato, Donatella Sciuto, Benjamin Tan, Siddharth Garg, Ramesh Karri:
High-level design methods for hardware security: is it the right choice? invited. 1375-1378 - Chen Chen, Rahul Kande, Pouya Mahmoody, Ahmad-Reza Sadeghi, J. V. Rajendran:
Trusting the trust anchor: towards detecting cross-layer vulnerabilities with hardware fuzzing. 1379-1383 - Ryan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton:
Automating hardware security property generation: invited. 1384-1387 - Cheng-Hsiang Chiu, Tsung-Wei Huang:
Efficient timing propagation with simultaneous structural and pipeline parallelisms: late breaking results. 1388-1389 - Amir Hossein Jalilvand, Seyedeh Newsha Estiri, Samaneh Naderi, M. Hassan Najafi, Mohsen Imani:
A fast and low-cost comparison-free sorting engine with unary computing: late breaking results. 1390-1391 - Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible chip placement via reinforcement learning: late breaking results. 1392-1393 - Mengshu Sun, Zhengang Li, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang:
FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results. 1394-1395 - Sung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun, Yanyu Li, Xiaolong Ma, Zhengang Li, Yanyue Xie, Minghai Qin, Xue Lin, Zhenman Fang, Yanzhi Wang:
Hardware-efficient stochastic rounding unit design for DNN training: late breaking results. 1396-1397 - Pengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang:
Placement initialization via a projected eigenvector algorithm: late breaking results. 1398-1399 - Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang:
Subgraph matching based reference placement for PCB designs: late breaking results. 1400-1401 - Hojun Choi, Youngmoon Lee:
Thermal-aware drone battery management: late breaking results. 1402-1403 - Lucas Klemmer, Daniel Große:
Waveform-based performance analysis of RISC-V processors: late breaking results. 1404-1405
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