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2020 – today
- 2024
[c132]Allen Boston, Roman Gauchi, Pierre-Emmanuel Gaillardon:
Secure eFPGA Configuration: A System-Level Approach. ARC 2024: 151-165- [c131]Seyed Mohammad Ali Zeinolabedin, Matthieu Couriol, Pierre-Emmanuel Gaillardon:
Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants. MWSCAS 2024: 651-655 - [c130]Ashton Snelgrove, Skylar Stockham, Pierre-Emmanuel Gaillardon:
Benchmarking Microfluidic Design Automation Flows. VLSI-SoC 2024: 1-6 - [i10]Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace:
AIvril: AI-Driven RTL Generation With Verification In-The-Loop. CoRR abs/2409.11411 (2024) - [i9]Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace:
EDA-Aware RTL Generation with Large Language Models. CoRR abs/2412.04485 (2024) - 2023
- [j41]Walter Lau Neto
, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu:
FlowTune: End-to-End Automatic Logic Optimization Exploration via Domain-Specific Multiarmed Bandit. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1912-1925 (2023) - [j40]Aurélien Alacchi, Edouard Giacomin, Scott Temple, Roman Gauchi, Michael J. Wirthlin, Pierre-Emmanuel Gaillardon:
Low Latency SEU Detection in FPGA CRAM With In-Memory ECC Checking. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 2028-2036 (2023) - [j39]Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep Kulkarni, Lizy K. John:
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration. ACM Trans. Reconfigurable Technol. Syst. 16(3): 50:1-50:34 (2023) - [j38]Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA Design. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1128-1139 (2023) - [j37]Aurélien Alacchi, Edouard Giacomin, Roman Gauchi, Szymon Kulis, Pierre-Emmanuel Gaillardon:
Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1204-1213 (2023) - [j36]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters for IP Redaction. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1459-1471 (2023) - [c129]Dana How, Tim Ansell, Vaughn Betz, Chris Lavin, Ted Speers, Pierre-Emmanuel Gaillardon:
Open-source and FPGAs: Hardware, Software, Both or None? FPGA 2023: 149 - [c128]Grant Brown, Ganesh Gore, Pierre-Emmanuel Gaillardon:
Performance Optimized Clock Tree Embedding for Auto-Generated FPGAs. ISVLSI 2023: 1-6 - [i8]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023) - 2022
- [j35]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5126-5130 (2022) - [j34]Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
Programmable Local Clock SET Filtering for SEE-Resistant FPGA. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3879-3883 (2022) - [c127]Thomas Becnel, Kerry E. Kelly, Pierre-Emmanuel Gaillardon:
Tiny Time-Series Transformers: Realtime Multi-Target Sensor Inference At The Edge. COINS 2022: 1-6 - [c126]Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon:
Improving LUT-based optimization for ASICs. DAC 2022: 421-426 - [c125]Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato:
ALICE: an automatic design flow for eFPGA redaction. DAC 2022: 781-786 - [c124]Ashton Snelgrove, Pierre-Emmanuel Gaillardon:
Programmable logic elements using multigate ambipolar transistors. DDECS 2022: 112-117 - [c123]Roman Gauchi, Ashton Snelgrove, Pierre-Emmanuel Gaillardon:
An Open-source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis. ISCAS 2022: 273-277 - [c122]Michael Keyser, Roman Gauchi, Pierre-Emmanuel Gaillardon:
An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing. VLSI-SoC 2022: 1-6 - [d1]Thomas Becnel, Kerry E. Kelly, Pierre-Emmanuel Gaillardon:
University of Utah AirU Pollution Monitoring Network - Salt Lake City UT - 2019-07-26 - 2021-05-14. IEEE DataPort, 2022
- [i7]Walter Lau Neto, Yingjie Li, Pierre-Emmanuel Gaillardon, Cunxi Yu:
End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit. CoRR abs/2202.07721 (2022) - [i6]Chiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato:
ALICE: An Automatic Design Flow for eFPGA Redaction. CoRR abs/2205.07425 (2022) - 2021
- [j33]Sherief Reda, Leon Stok, Pierre-Emmanuel Gaillardon:
Guest Editors' Introduction: The Resurgence of Open- Source EDA Technology. IEEE Des. Test 38(2): 5-7 (2021) - [j32]Adi Eliahu, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. ACM J. Emerg. Technol. Comput. Syst. 17(2): 24:1-24:27 (2021) - [c121]Grant Brown, Valerio Tenace, Pierre-Emmanuel Gaillardon:
NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks. ASAP 2021: 57-60 - [c120]Walter Lau Neto, Matheus Trevisan Moreira, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization. ASP-DAC 2021: 530-535 - [c119]Walter Lau Neto, Matheus T. Moreira, Yingjie Li, Luca G. Amarù, Cunxi Yu, Pierre-Emmanuel Gaillardon:
SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping. DAC 2021: 859-864 - [c118]Scott Temple, Walter Lau Neto, Ashton Snelgrove, Xifan Tang, Pierre-Emmanuel Gaillardon:
Invited: Getting the Most out of your Circuits with Heterogeneous Logic Synthesis. DAC 2021: 1331-1334 - [c117]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c116]Thomas Becnel, Pierre-Emmanuel Gaillardon:
A Deep Learning Approach to Sensor Fusion Inference at the Edge. DATE 2021: 1420-1425 - [c115]Xifan Tang, Ganesh Gore, Grant Brown, Pierre-Emmanuel Gaillardon:
Taping out an FPGA in 24 hours with OpenFPGA: The SOFA Project. FPL 2021: 400 - [c114]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Exploring eFPGA-based Redaction for IP Protection. ICCAD 2021: 1-9 - [c113]Aurélien Alacchi, Edouard Giacomin, Xifan Tang, Pierre-Emmanuel Gaillardon:
Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. ISCAS 2021: 1-5 - [c112]Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. ISCAS 2021: 1-5 - [c111]Ganesh Gore, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs. ISPD 2021: 135-142 - [c110]Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors. VLSI-SoC 2021: 1-6 - [c109]Matthieu Couriol, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A 12-pA Resolution Sigma Delta ADC Topology for Chemiresistive Sensor-Based Applications. VLSI-SoC 2021: 1-6 - [c108]Matthieu Couriol, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A First Approach in Using Super-Steep-Subthreshold-Slope Field-Effect Transistors in Ultra-Low Power Analog Design. VLSI-SoC (Selected Papers) 2021: 205-224 - [e2]Andrea Calimera, Pierre-Emmanuel Gaillardon, Kunal Korgaonkar, Shahar Kvatinsky, Ricardo Reis:
VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 621, Springer 2021, ISBN 978-3-030-81640-7 [contents] - [i5]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Exploring eFPGA-based Redaction for IP Protection. CoRR abs/2110.13346 (2021) - [i4]Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan, Christian Pilato, Ganesh Gore, Xifan Tang, Scott Temple, Pierre-Emmanuel Gaillardon, Ramesh Karri:
Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction. CoRR abs/2111.04222 (2021) - [i3]Gabriel Ammes, Walter Lau Neto, Paulo F. Butzen, Pierre-Emmanuel Gaillardon, Renato P. Ribas:
A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal. CoRR abs/2112.00621 (2021) - 2020
- [j31]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8: 226828-226844 (2020) - [j30]Walter Lau Neto, Vinicius N. Possani, Felipe S. Marranghello, Jody Maick Matos, Pierre-Emmanuel Gaillardon, André Inácio Reis, Renato Perez Ribas:
Exact Benchmark Circuits for Logic Synthesis. IEEE Des. Test 37(3): 51-58 (2020) - [j29]Xifan Tang, Edouard Giacomin, Baudouin Chauviere, Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
OpenFPGA: An Open-Source Framework for Agile Prototyping Customizable FPGAs. IEEE Micro 40(4): 41-48 (2020) - [c107]Xifan Tang, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore, Pierre-Emmanuel Gaillardon:
A RRAM-based FPGA for Energy-efficient Edge Computing. DATE 2020: 144- - [c106]Max Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon:
A Scalable Mixed Synthesis Framework for Heterogeneous Networks. DATE 2020: 670-673 - [c105]Mohammad Mehdi Sharifi, Ramin Rajaei, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael T. Niemier, Xiaobo Sharon Hu:
A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks. DATE 2020: 1253-1258 - [c104]Surya Narayanan, Karl Taht, Rajeev Balasubramonian, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
SpinalFlow: An Architecture and Dataflow Tailored for Spiking Neural Networks. ISCA 2020: 349-362 - [c103]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC 2020: 34-39 - [c102]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) 2020: 279-300 - [e1]Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Carlos Silva Cárdenas, Ricardo Reis:
VLSI-SoC: New Technology Enabler - 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco, Peru, October 6-9, 2019, Revised and Extended Selected Papers. IFIP Advances in Information and Communication Technology 586, Springer 2020, ISBN 978-3-030-53272-7 [contents] - [i2]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [j28]Thomas Becnel, Kyle Tingey, Jonathan Whitaker, Tofigh Sayahi, Katrina Lê, Pascal Goffin, Anthony Butterfield, Kerry E. Kelly, Pierre-Emmanuel Gaillardon:
A Distributed Low-Cost Pollution Monitoring Platform. IEEE Internet Things J. 6(6): 10738-10748 (2019) - [j27]Edouard Giacomin, Tzofnat Greenberg-Toledo, Shahar Kvatinsky, Pierre-Emmanuel Gaillardon:
A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(2): 643-654 (2019) - [j26]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 27(3): 637-650 (2019) - [j25]Giovanni V. Resta, Alessandra Leonhardt, Yashwanth Balaji, Stefan De Gendt, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 27(7): 1486-1503 (2019) - [c101]Patsy Cadareanu, N. Reddy C, Carmen G. Almudéver, A. Khanna, Arijit Raychowdhury, Suman Datta, Koen Bertels, Vijayakrishan Narayanan, Massimiliano Di Ventra, Pierre-Emmanuel Gaillardon:
Rebooting Our Computing Models. DATE 2019: 1469-1476 - [c100]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Scalable Boolean Methods in a Modern Synthesis Flow. DATE 2019: 1643-1648 - [c99]Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Baudouin Chauviere, Pierre-Emmanuel Gaillardon:
OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs. FPL 2019: 367-374 - [c98]Walter Lau Neto, Max Austin, Scott Temple, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon:
LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper. ICCAD 2019: 1-6 - [c97]Thomas Becnel, Tofigh Sayahi, Kerry E. Kelly, Pierre-Emmanuel Gaillardon:
A Recursive Approach to Partially Blind Calibration of a Pollution Sensor Network. ICESS 2019: 1-8 - [c96]Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. FPT 2019: 247-250 - [c95]Walter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon:
Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs. ISVLSI 2019: 224-229 - [c94]Sumanth Gudaparthi, Surya Narayanan, Rajeev Balasubramonian, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
Wire-Aware Architecture and Dataflow for CNN Accelerators. MICRO 2019: 1-13 - [c93]Anirban Nag, C. N. Ramachandra, Rajeev Balasubramonian, Ryan Stutsman, Edouard Giacomin, Hari Kambalasubramanyam, Pierre-Emmanuel Gaillardon:
GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment. MICRO 2019: 334-346 - [c92]Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza:
Functionality Enhanced Memories for Edge-AI Embedded Systems. NVMTS 2019: 1-4 - [c91]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. VLSI-SoC 2019: 160-165 - [c90]Ganesh Gore, Patsy Cadareanu, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC 2019: 172-177 - [c89]João Vieira, Edouard Giacomin, Yasir Mahmood Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky, David Atienza, Pierre-Emmanuel Gaillardon:
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. VLSI-SoC (Selected Papers) 2019: 257-278 - [c88]Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon:
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors. VLSI-SoC (Selected Papers) 2019: 307-322 - [p2]Davide Sacchetto, Pierre-Emmanuel Gaillardon, Yusuf Leblebici, Giovanni De Micheli:
Memory Effects in Multi-terminal Solid State Devices and Their Applications. Handbook of Memristor Networks 2019: 1021-1064 - [p1]John Reuben, Nishil Talati, Nimrod Wald, Rotem Ben Hur, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
A Taxonomy and Evaluation Framework for Memristive Logic. Handbook of Memristor Networks 2019: 1065-1099 - 2018
- [j24]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Post-P&R Performance and Power Analysis for RRAM-Based FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 639-650 (2018) - [j23]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1422-1435 (2018) - [j22]Said Hamdioui, Pierre-Emmanuel Gaillardon, Dietmar Fey, Tajana Simunic Rosing:
Guest Editorial Memristive-Device-Based Computing. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2581-2583 (2018) - [c87]Giovanni V. Resta, Jorge Romero Gonzalez, Yashwanth Balaji, Tarun Agarwal, Dennis Lin, Francky Catthoor, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Towards high-performance polarity-controllable FETs with 2D materials. DATE 2018: 637-641 - [c86]Nishil Talati, Ameer Haj Ali, Rotem Ben Hur, Nimrod Wald, Ronny Ronen, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Practical challenges in delivering the promises of real processing-in-memory machines. DATE 2018: 1628-1633 - [c85]Giovanni V. Resta, Yashwanth Balaji, Dennis Lin, Iuliana P. Radu, Francky Catthoor, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors. DRC 2018: 1-2 - [c84]Shubham Rai, Srivatsa Rangachar Srinivasa, Patsy Cadareanu, Xunzhao Yin, Xiaobo Sharon Hu, Pierre-Emmanuel Gaillardon, Vijaykrishnan Narayanan, Akash Kumar:
Emerging reconfigurable nanotechnologies: can they support future electronics? ICCAD 2018: 13 - [c83]Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon:
An Efficient Adder Architecture with Three- Independent-Gate Field-Effect Transistors. ICRC 2018: 1-8 - [c82]Edouard Giacomin, Pierre-Emmanuel Gaillardon:
Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors. VLSI-SoC 2018: 107-112 - 2017
- [j21]Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli:
A PLiM Computer for the Internet of Things. Computer 50(6): 35-40 (2017) - [j20]Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Exact Synthesis of Majority-Inverter Graphs and Its Applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(11): 1842-1855 (2017) - [j19]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1173-1186 (2017) - [j18]Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers. IEEE Trans. Emerg. Top. Comput. 5(2): 210-222 (2017) - [c81]Winston Haaswijk, Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A novel basis for logic rewriting. ASP-DAC 2017: 151-156 - [c80]Luca Gaetano Amarù, Mathias Soeken, Winston Haaswijk, Eleonora Testa, Patrick Vuillod, Jiong Luo, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Multi-level logic benchmarks: An exactness study. ASP-DAC 2017: 157-162 - [c79]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler:
Endurance management for resistive Logic-In-Memory computing architectures. DATE 2017: 1092-1097 - [c78]Odysseas Zografos, A. De Meester, Eleonora Testa, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Luca Gaetano Amarù, Praveen Raghavan, Francky Catthoor, Rudy Lauwereins:
Wave pipelining for majority-based beyond-CMOS technologies. DATE 2017: 1306-1311 - [c77]Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. ACM Great Lakes Symposium on VLSI 2017: 131-136 - [c76]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359 - [c75]Mahesh Nataraj, Alexandre Levisse, Bastien Giraud, Jean-Philippe Noël, Pascal Andreas Meinerzhagen, Jean-Michel Portal, Pierre-Emmanuel Gaillardon:
Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop. ISCAS 2017: 1-4 - [c74]Sebastien Naus, Ioulia Tzouvadaki, Pierre-Emmanuel Gaillardon, Armando Biscontini, Giovanni De Micheli, Sandro Carrara:
An efficient electronic measurement interface for memristive biosensors. ISCAS 2017: 1-4 - [c73]Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
RM3 based logic synthesis (Special session paper). ISCAS 2017: 1-4 - [c72]Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Physical Design Considerations of One-level RRAM-based Routing Multiplexers. ISPD 2017: 47-54 - [c71]Xifan Tang, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Optimization opportunities in RRAM-based FPGA architectures. LASCAS 2017: 1-4 - [c70]Edouard Giacomin, Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon:
Low-power multiplexer designs using three-independent-gate field effect transistors. NANOARCH 2017: 33-38 - [c69]John Reuben, Rotem Ben Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, Shahar Kvatinsky:
Memristive logic: A framework for evaluation and comparison. PATMOS 2017: 1-8 - 2016
- [j17]Jury Sandrini, Marios Barlas, Maxime Thammasack, Tugba Demirci, Michele De Marchi, Davide Sacchetto, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Yusuf Leblebici:
Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(3): 339-351 (2016) - [j16]Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Xunzhao Yin, Xiaobo Sharon Hu, Michael T. Niemier, Yier Jin:
Emerging Technology-Based Design of Primitives for Hardware Security. ACM J. Emerg. Technol. Comput. Syst. 13(1): 3:1-3:19 (2016) - [j15]Hassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Jian Zhang, Giovanni De Micheli, Ernesto Sánchez, Matteo Sonza Reorda:
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