18th DDECS 2015: Belgrade, Serbia

Session 1A: ATPG & Test Compression

Session 1B: Design Architectures & Synthesis

Session 2A: Digital Design

Session 2B: Analog Circuits

Poster Session I

Session 3A: Modeling and Simulation

Session 3B: Student Session

Session 4A: Formal Verification

Session 4B: Design Enhancement

Session 5A: Wear-Out & Intermittent Faults

Session 5B: Measurement & Analysis

Poster Session II

a service of Schloss Dagstuhl - Leibniz Center for Informatics