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ORCID57th DAC 2020: San Francisco, CA, USA
- 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020. IEEE 2020, ISBN 978-1-7281-1085-1
- Antonino Tumeo, Marco Minutoli
, Vito Giovanni Castellana, Joseph B. Manzano, Vinay Amatya, David Brooks, Gu-Yeon Wei:
Invited: Software Defined Accelerators From Learning Tools Environment. 1-6 - Ghada Dessouky, Patrick Jauernig, Nele Mentens, Ahmad-Reza Sadeghi, Emmanuel Stapf:
INVITED: AI Utopia or Dystopia - On Securing AI Platforms. 1-6 - Shaza Zeitouni, Emmanuel Stapf, Hossein Fereidooni, Ahmad-Reza Sadeghi:
On the Security of Strong Memristor-based Physically Unclonable Functions. 1-6 - Anna Bernasconi, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni:
Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to Security. 1-6 - Behnam Khaleghi, Mohsen Imani, Tajana Rosing:
Prive-HD: Privacy-Preserved Hyperdimensional Computing. 1-6 - Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. 1-6 - Brett Shook, Prateek Bhansali, Chandramouli V. Kashyap, Chirayu Amin, Siddhartha Joshi:
MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design. 1-6 - Renzo Andri, Tomas Henriksson, Luca Benini:
Extending the RISC-V ISA for Efficient RNN-based 5G Radio Resource Management. 1-6 - Javad Bagherzadeh, Aporva Amarnath, Jielun Tan, Subhankar Pal, Ronald G. Dreslinski:
R2D3: A Reliability Engine for 3D Parallel Systems. 1-6 - Zhanhong Tan, Jiebo Song, Xiaolong Ma, Sia Huat Tan, Hongyang Chen, Yuanqing Miao, Yifu Wu, Shaokai Ye, Yanzhi Wang, Dehui Li, Kaisheng Ma:
PCNN: Pattern-based Fine-Grained Regular Pruning Towards Optimizing CNN Accelerators. 1-6 - Peiyan Dong, Siyue Wang, Wei Niu, Chengming Zhang, Sheng Lin, Zhengang Li, Yifan Gong, Bin Ren, Xue Lin, Dingwen Tao:
RTMobile: Beyond Real-Time Mobile Acceleration of RNNs for Speech Recognition. 1-6 - He-Teng Zhang, Jie-Hong R. Jiang:
SFO: A Scalable Approach to Fanout-Bounded Logic Synthesis for Emerging Technologies. 1-6 - Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele:
ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. 1-6 - Minah Lee, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay:
WarningNet: A Deep Learning Platform for Early Warning of Task Failures under Input Perturbation for Reliable Autonomous Platforms. 1-6 - Minjin Tang, Mei Wen, Junzhong Shen, Xiaolei Zhao, Chunyuan Zhang:
Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. 1-6 - Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang:
An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. 1-6 - Kaushik Roy, Indranil Chakraborty, Mustafa Fayez Ali, Aayush Ankit, Amogh Agrawal:
In-Memory Computing in Emerging Memory Technologies for Machine Learning: An Overview. 1-6 - Yung-Chih Chen, Hao-Ju Chang, Li-Cheng Zheng:
Don't-Care-Based Node Minimization for Threshold Logic Networks. 1-6 - Jaekang Shin, Seungkyu Choi, Yeongjae Choi, Lee-Sup Kim:
A Pragmatic Approach to On-device Incremental Learning System with Selective Weight Updates. 1-6 - Huili Chen, Rosario Cammarota, Felipe Valencia, Francesco Regazzoni, Farinaz Koushanfar:
AHEC: End-to-end Compiler Framework for Privacy-preserving Machine Learning Acceleration. 1-6 - Sundar Dev, David Lo, Liqun Cheng, Parthasarathy Ranganathan:
Autonomous Warehouse-Scale Computers. 1-6 - Pei-Wei Chen, Yu-Ching Huang, Cheng-Lin Lee, Jie-Hong Roland Jiang:
Circuit Learning for Logic Regression on High Dimensional Boolean Space. 1-6 - Dimitrios Serpanos, Shengqi Yang, Marilyn Wolf:
Neural Network-Based Side Channel Attacks and Countermeasures. 1-2 - Tao Lu, Lu Peng:
BPU: A Blockchain Processing Unit for Accelerated Smart Contract Execution. 1-6 - Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang:
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. 1-6 - Jiaji He, Xiaolong Guo, Haocheng Ma, Yanjiang Liu, Yiqiang Zhao, Yier Jin:
Runtime Trust Evaluation and Hardware Trojan Detection Using On-Chip EM Sensors. 1-6 - Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku:
ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. 1-6 - Thierry Tambe, En-Yu Yang, Zishen Wan, Yuntian Deng, Vijay Janapa Reddi, Alexander M. Rush, David Brooks, Gu-Yeon Wei:
Algorithm-Hardware Co-Design of Adaptive Floating-Point Encodings for Resilient Deep Learning Inference. 1-6 - Xianfeng Li, Gengchao Li, Xiaole Cui:
ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations. 1-6 - Hyungjun Oh, Yongseung Yu, Giha Ryu, Gunjoo Ahn, Yuri Jeong, Yongjun Park, Jiwon Seo:
Convergence-Aware Neural Network Training. 1-6 - Jianqi Chen, Monir Zaman, Yiorgos Makris, R. D. Shawn Blanton, Subhasish Mitra, Benjamin Carrión Schäfer:
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. 1-6 - Daan van der Valk, Marina Krcek, Stjepan Picek, Shivam Bhasin:
Learning From A Big Brother - Mimicking Neural Networks in Profiled Side-channel Analysis. 1-6 - Prawar Poudel, Biswajit Ray, Aleksandar Milenkovic:
Flashmark: Watermarking of NOR Flash Memories for Counterfeit Detection. 1-6 - Feng Xiong, Fengbin Tu, Man Shi, Yang Wang, Leibo Liu, Shaojun Wei, Shouyi Yin:
STC: Significance-aware Transform-based Codec Framework for External Memory Access Reduction. 1-6 - Chaoqun Chu, Yanzhi Wang, Yilong Zhao, Xiaolong Ma, Shaokai Ye, Yunyan Hong, Xiaoyao Liang, Yinhe Han, Li Jiang:
PIM-Prune: Fine-Grain DCNN Pruning for Crossbar-Based Process-In-Memory Architecture. 1-6 - Hongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu:
A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip Training. 1-6 - Nitthilan Kanappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande:
PETNet: Polycount and Energy Trade-off Deep Networks for Producing 3D Objects from Images. 1-6 - Yawen Wu, Zhepeng Wang, Zhenge Jia, Yiyu Shi, Jingtong Hu:
Intermittent Inference with Nonuniformly Compressed Multi-Exit Neural Network for Energy Harvesting Powered Devices. 1-6 - Soheil Nazar Shahsavani, Massoud Pedram:
TDP-ADMM: A Timing Driven Placement Approach for Superconductive Electronic Circuits Using Alternating Direction Method of Multipliers. 1-6 - Dongup Kwon, Suyeon Hur, Hamin Jang, Eriko Nurvitadhi, Jangwoo Kim:
Scalable Multi-FPGA Acceleration for Large RNNs with Full Parallelism Levels. 1-6 - Wenhan Xia, Hongxu Yin, Niraj K. Jha:
INVITED: Efficient Synthesis of Compact Deep Neural Networks. 1-6 - Wei Zhong, Shuxiang Hu, Yuzhe Ma, Haoyu Yang, Xiuyuan Ma, Bei Yu:
Deep Learning-Driven Simultaneous Layout Decomposition and Mask Optimization. 1-6 - Bo Qiao, M. Akif Özkan, Jürgen Teich, Frank Hannig:
The Best of Both Worlds: Combining CUDA Graph with an Image Processing DSL. 1-6 - Andrew B. Kahng, Lutong Wang, Bangqi Xu:
The Tao of PAO: Anatomy of a Pin Access Oracle for Detailed Routing. 1-6 - Bharath Srinivas Prabakaran, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique:
ApproxFPGAs: Embracing ASIC-Based Approximate Arithmetic Components for FPGA-Based Systems. 1-6 - Xiandong Zhao, Ying Wang, Cheng Liu, Cong Shi, Kaijie Tu, Lei Zhang:
BitPruner: Network Pruning for Bit-serial Accelerators. 1-6 - Rémi Denis-Courmont, Hans Liljestrand, Carlos Chinea Perez, Jan-Erik Ekberg:
Camouflage: Hardware-assisted CFI for the ARM Linux kernel. 1-6 - Jorge Echavarria, Stefan Wildermann, Oliver Keszöcze, Jürgen Teich:
Probabilistic Error Propagation through Approximated Boolean Networks. 1-6 - Jan Spieck, Stefan Wildermann, Jürgen Teich:
Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. 1-6 - Jinho Lee, Inseok Hwang, Soham Shah, Minsik Cho:
FlexReduce: Flexible All-reduce for Distributed Deep Learning on Asymmetric Network Topology. 1-6 - Srikant Bharadwaj, Jieming Yin, Bradford M. Beckmann, Tushar Krishna:
Kite: A Family of Heterogeneous Interposer Topologies Enabled via Accurate Interconnect Modeling. 1-6 - Yina Lv, Liang Shi, Qiao Li, Chun Jason Xue, Edwin H.-M. Sha:
Access Characteristic Guided Partition for Read Performance Improvement on Solid State Drives. 1-6 - Alexander Hoffman, Anuj Pathania, Philipp H. Kindt, Samarjit Chakraborty, Tulika Mitra:
BrezeFlow: Unified Debugger for Android CPU Power Governors and Schedulers on Edge Devices. 1-6 - Rafael Billig Tonetto, Hiago Mayk G. de A. Rocha, Gabriel L. Nazar, Antonio Carlos Schneider Beck:
A Machine Learning Approach for Reliability-Aware Application Mapping for Heterogeneous Multicores. 1-6 - Arman Kazemi, Cristobal Alessandri, Alan C. Seabaugh, Xiaobo Sharon Hu, Michael T. Niemier, Siddharth Joshi:
A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays. 1-6 - Kyungchul Park, Chanyoung Oh, Youngmin Yi:
BPNet: Branch-pruned Conditional Neural Network for Systematic Time-accuracy Tradeoff. 1-6 - Seyed Hamidreza Moghadas, Michael Pehl:
ROPAD: A Fully Digital Highly Predictive Ring Oscillator Probing Attempt Detector. 1-6 - Ahmad M. Radaideh, Paul V. Gratz:
Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs. 1-6 - Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, Maurizio Martina:
NACU: A Non-Linear Arithmetic Unit for Neural Networks. 1-6 - Bahar Asgari, Ramyad Hadidi, Nima Shoghi Ghaleshahi, Hyesoon Kim:
PISCES: Power-Aware Implementation of SLAM by Customizing Efficient Sparse Algebra. 1-6 - Ji Zhang, Yuanzhang Wang, Yangtao Wang, Ke Zhou, Sebastian Schelter, Ping Huang, Bin Cheng, Yongguang Ji:
Tier-Scrubbing: An Adaptive and Tiered Disk Scrubbing Scheme with Improved MTTD and Reduced Cost. 1-6 - Po-Chun Chien, Jie-Hong R. Jiang:
Time Multiplexing via Circuit Folding. 1-6 - Rick Bahr, Clark W. Barrett, Nikhil Bhagdikar, Alex Carsello, Ross Daly, Caleb Donovick, David Durst, Kayvon Fatahalian, Kathleen Feng, Pat Hanrahan, Teguh Hofstee, Mark Horowitz, Dillon Huff, Fredrik Kjolstad, Taeyoung Kong, Qiaoyi Liu, Makai Mann, Jackson Melchert, Ankita Nayak, Aina Niemetz, Gedeon Nyengele, Priyanka Raina, Stephen Richardson, Rajsekhar Setaluri, Jeff Setter, Kavya Sreedhar, Maxwell Strange, James Thomas, Christopher Torng, Leonard Truong, Nestan Tsiskaridze, Keyi Zhang:
Creating an Agile Hardware Design Flow. 1-6 - Qing Wang, Youyou Lu, Zhongjie Wu, Fan Yang, Jiwu Shu:
Improving the Concurrency Performance of Persistent Memory Transactions on Multicores. 1-6 - Stefan Hillmich, Igor L. Markov, Robert Wille:
Just Like the Real Thing: Fast Weak Simulation of Quantum Computation. 1-6 - Quan Chen:
A Robust Exponential Integrator Method for Generic Nonlinear Circuit Simulation. 1-6 - Tianjia He, Lin Zhang, Fanxin Kong, Asif Salekin:
Exploring Inherent Sensor Redundancy for Automotive Anomaly Detection. 1-6 - Mahabubul Alam, Abdullah Ash-Saki, Swaroop Ghosh:
An Efficient Circuit Compilation Flow for Quantum Approximate Optimization Algorithm. 1-6 - Sunwoo Ahn, Hayoon Yi, Younghan Lee, Whoi Ree Ha, Giyeol Kim, Yunheung Paek:
Hawkware: Network Intrusion Detection based on Behavior Analysis with ANNs on an IoT Device. 1-6 - Dharanidhar Dang, Sahar Taheri, Bill Lin, Debashis Sahoo:
MEMTONIC: A Neuromorphic Accelerator for Energy Efficient Deep Learning. 1-2 - Haowei Deng, Yu Zhang, Quanxi Li:
Codar: A Contextual Duration-Aware Qubit Mapping for Various NISQ Devices. 1-6 - Lukas Burgholzer, Robert Wille:
The Power of Simulation for Equivalence Checking in Quantum Computing. 1-6 - Arne Hamann, Selma Saidi, David Ginthoer, Christian Wietfeld, Dirk Ziegenbein:
Building End-to-End IoT Applications with QoS Guarantees. 1-6 - Zhuoran Song, Jianfei Wang, Tianjian Li, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
GPNPU: Enabling Efficient Hardware-Based Direct Convolution with Multi-Precision Support in GPU Tensor Cores. 1-6 - Kyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park:
Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-Precision. 1-6 - Marina Neseem, Jon Nelson, Sherief Reda:
AdaSense: Adaptive Low-Power Sensing and Activity Recognition for Wearable Devices. 1-6 - Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. 1-6 - Leilai Shao, Ting Lei, Tsung-Ching Huang, Zhenan Bao, Kwang-Ting Cheng:
Robust Design of Large Area Flexible Electronics via Compressed Sensing. 1-6 - Mengshu Sun, Pu Zhao, Mehmet Güngör, Massoud Pedram, Miriam Leeser, Xue Lin:
3D CNN Acceleration on FPGA using Hardware-Aware Pruning. 1-6 - Mohammad Rahmani Fadiheh, Johannes Müller, Raik Brinkmann, Subhasish Mitra, Dominik Stoffel, Wolfgang Kunz:
A Formal Approach for Detecting Vulnerabilities to Transient Execution Attacks in Out-of-Order Processors. 1-6 - Cheng-Yun Hsieh, Chen-Hung Wu, Chia-Hsien Huang, His-Sheng Goan, James Chien-Mo Li:
Realistic Fault Models and Fault Simulation for Quantum Dot Quantum Circuits. 1-6 - Rui Li, Heng Yu, Weixiong Jiang, Yajun Ha:
DVFS-Based Scrubbing Scheduling for Reliability Maximization on Parallel Tasks in SRAM-based FPGAs. 1-6 - Mojan Javaheripi, Huili Chen, Farinaz Koushanfar:
Unified Architectural Support for Secure and Robust Deep Learning. 1-6 - Md Fahim Faysal Khan, Mohammad Mahdi Kamani, Mehrdad Mahdavi, Vijaykrishnan Narayanan:
Learning to Quantize Deep Neural Networks: A Competitive-Collaborative Approach. 1-6 - Wenye Liu, Chip-Hong Chang, Fan Zhang, Xiaoxuan Lou:
Imperceptible Misclassification Attack on Deep Learning Accelerator by Glitch Injection. 1-6 - Ziru Li, Bonan Yan, Hai Helen Li:
ReSiPE: ReRAM-based Single-Spiking Processing-In-Memory Engine. 1-6 - Charles Gouert, Nektarios Georgios Tsoutsos:
Romeo: Conversion and Evaluation of HDL Designs in the Encrypted Domain. 1-6 - Mohamed Baker Alawieh, Duane S. Boning, David Z. Pan:
Wafer Map Defect Patterns Classification using Deep Selective Learning. 1-6 - Runbin Shi, Yuhao Ding, Xuechao Wei, He Li, Hang Liu, Hayden Kwok-Hay So, Caiwen Ding:
FTDL: A Tailored FPGA-Overlay for Deep Learning with High Scalability. 1-6 - Yi-Chen Lu, Sai Surya Kiran Pentapati, Lingjun Zhu, Kambiz Samadi, Sung Kyu Lim:
TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs. 1-6 - Yijie Wei, Kofi Otseidu, Jie Gu:
Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-Low Power SoC. 1-6 - Maolin Yang, Ze-Wei Chen, Xu Jiang, Nan Guan, Hang Lei:
DPCP-p: A Distributed Locking Protocol for Parallel Real-Time Tasks. 1-6 - Inayat Ullah, Kashif Inayat, Joon-Sung Yang, Jaeyong Chung:
Factored Radix-8 Systolic Array for Tensor Processing. 1-6 - Marcelo Brandalero, Bernardo Neuhaus Lignati, Antonio Carlos Schneider Beck, Muhammad Shafique, Michael Hübner:
Proactive Aging Mitigation in CGRAs through Utilization-Aware Allocation. 1-6 - Jinrong Guo, Songlin Hu, Wang Wang, Chunrong Yao, Jizhong Han, Ruixuan Li, Yijun Lu:
Tail: An Automated and Lightweight Gradient Compression Framework for Distributed Deep Learning. 1-6 - Xun Jiao, Dongning Ma, Wanli Chang, Yu Jiang:
TEVoT: Timing Error Modeling of Functional Units under Dynamic Voltage and Temperature Variations. 1-6 - Xi Wang, Brody Williams, John D. Leidel, Alan Ehret, Michel A. Kinsy, Yong Chen:
Remote Atomic Extension (RAE) for Scalable High Performance Computing. 1-6 - Qilin Zheng, Zongwei Wang, Zishun Feng, Bonan Yan, Yimao Cai, Ru Huang, Yiran Chen, Chia-Lin Yang, Hai Helen Li:
Lattice: An ADC/DAC-less ReRAM-based Processing-In-Memory Architecture for Accelerating Deep Convolution Neural Networks. 1-6 - Igor L. Markov, Aneeqa Fatima, Sergei V. Isakov, Sergio Boixo:
Massively Parallel Approximate Simulation of Hard Quantum Circuits. 1-6 - Shuhan Zhang, Fan Yang, Dian Zhou, Xuan Zeng:
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis. 1-6 - Jiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen, David Z. Pan:
FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization. 1-6 - Nguyen-Dong Ho, Minh-Son Le, Ik-Joon Chang:
O-2A: Low Overhead DNN Compression with Outlier-Aware Approximation. 1-6 - Daniele Jahier Pagliari, Roberta Chiaro, Yukai Chen, Sara Vinco, Enrico Macii, Massimo Poncino:
Input-Dependent Edge-Cloud Mapping of Recurrent Neural Networks Inference. 1-6 - Mohamed S. Abdelfattah, Lukasz Dudziak, Thomas Chau, Royson Lee, Hyeji Kim, Nicholas D. Lane:
Best of Both Worlds: AutoML Codesign of a CNN and its Hardware Accelerator. 1-6 - Nils Heitmann, Philipp H. Kindt, Samarjit Chakraborty:
Late Breaking Results: Can You Hear Me? Towards an Ultra Low-Cost Hearing Screening Device. 1-2 - Dmitry Utyamishev, Inna Partin-Vaisband:
Late Breaking Results: A Neural Network that Routes ICs. 1-2 - Minghua Wang, Zhi Zhang, Yueqiang Cheng, Surya Nepal:
DRAMDig: A Knowledge-assisted Tool to Uncover DRAM Address Mapping. 1-6 - Akashdeep Saha, Sayandeep Saha, Siddhartha Chowdhury, Debdeep Mukhopadhyay, Bhargab B. Bhattacharya:
LoPher: SAT-Hardened Logic Embedding on Block Ciphers. 1-6 - Debjit Sinha, Vasant Rao, Chaitanya Peddawad, Michael H. Wood, Jeffrey G. Hemmett, Suriya Skariah, Patrick Williams:
Statistical Timing Analysis considering Multiple-Input Switching. 1-6 - Wenfei Hu, Zuochang Ye, Yan Wang:
Adjoint Transient Sensitivity Analysis for Objective Functions Associated to Many Time Points. 1-6 - Zhengxiong Luo, Feilong Zuo, Yuheng Shen, Xun Jiao, Wanli Chang, Yu Jiang:
ICS Protocol Fuzzing: Coverage Guided Packet Crack and Generation. 1-6 - Sumit K. Mandal, Ümit Y. Ogras, Janardhan Rao Doppa, Raid Zuhair Ayoub, Michael Kishinevsky, Partha Pratim Pande:
Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs. 1-6