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ORCIDAndreas G. Veneris
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- affiliation: University of Toronto, Canada
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2020 – today
- 2024
[j38]James Won-Ki Hong, Andreas G. Veneris, Hongtaek Ju, Taeyeol Jeong, Changhoon Kang:
Innovations in Blockchain for Crypto Assets and Exchanges. Int. J. Netw. Manag. 34(4) (2024)- [j37]Srisht Fateh Singh
, Panagiotis Michalopoulos, Andreas G. Veneris:
Deeper: A shared liquidity decentralized exchange design for low trading volume tokens to enhance average liquidity. Int. J. Netw. Manag. 34(4) (2024) - [j36]Jemin Andrew Choi, Sidi Mohamed Beillahi, Srisht Fateh Singh, Panagiotis Michalopoulos, Peilun Li, Andreas G. Veneris, Fan Long:
LMPT: A Novel Authenticated Data Structure to Eliminate Storage Bottlenecks for High Performance Blockchains. IEEE Trans. Netw. Serv. Manag. 21(2): 1333-1343 (2024) - [c117]Reina Ke Xin Li, Srisht Fateh Singh, Andreas G. Park, Andreas G. Veneris:
On Tokenizing Securities in Contemporary Decentralized Finance Ecosystems. BRAINS 2024: 1-9 - [c116]Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris:
Option Contracts in the DeFi Ecosystem: Motivation, Solutions, & Technical Challenges. ICBC 2024: 1-7 - [c115]Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris:
BakUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance. ICBC 2024: 235-239 - [c114]Panagiotis Michalopoulos, Odunayo Olowookere, Nadia Pocher, Johannes Sedlmeir, Andreas G. Veneris, Poonam Puri:
Compliance Design Options for Offline CBDCs: Balancing Privacy and AML/CFT. ICBC 2024: 307-315 - [c113]Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long:
Safeguarding DeFi Smart Contracts against Oracle Deviations. ICSE 2024: 171:1-171:12 - [i5]Xun Deng, Sidi Mohamed Beillahi, Cyrus Minwalla, Han Du, Andreas G. Veneris, Fan Long:
Safeguarding DeFi Smart Contracts against Oracle Deviations. CoRR abs/2401.06044 (2024) - [i4]Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris:
BAKUP: Automated, Flexible, and Capital-Efficient Insurance Protocol for Decentralized Finance. CoRR abs/2410.09341 (2024) - 2023
- [j35]Keerthi Nelaturu, Anastasia Mavridou, Emmanouela Stachtiari, Andreas G. Veneris, Aron Laszka:
Correct-by-Design Interacting Smart Contracts and a Systematic Approach for Verifying ERC20 and ERC721 Contracts With VeriSolid. IEEE Trans. Dependable Secur. Comput. 20(4): 3110-3127 (2023) - [c112]Eric Keilty, Keerthi Nelaturu, Anastasia Kastania, Andreas G. Veneris:
Gas Optimization Patterns in Move Smart Contracts on the Aptos Blockchain. BRAINS 2023: 1-4 - [c111]Xun Deng, Zihan Zhao, Sidi Mohamed Beillahi, Han Du, Cyrus Minwalla, Keerthi Nelaturu, Andreas G. Veneris, Fan Long:
A Robust Front-Running Methodology for Malicious Flash- Loan DeFi Attacks. DAPPS 2023: 38-47 - [c110]Srisht Fateh Singh, Panagiotis Michalopoulos, Sidi Mohamed Beillahi, Andreas G. Veneris, Fan Long:
Möbius: an Atomic State Sharding Design for Account-Based Blockchains. ICBC 2023: 1-9 - [c109]Srisht Fateh Singh, Panagiotis Michalopoulos, Andreas G. Veneris:
DEEPER: Enhancing Liquidity in Concentrated Liquidity AMM DEX via Sharing. ICBC 2023: 1-7 - [c108]Panagiotis Michalopoulos, Srisht Fateh Singh, Andreas G. Veneris:
Inducing Trust in Blockchain-enabled IoT Marketplaces Through Reputation and Dispute Resolution. MetaCom 2023: 398-402 - [c107]Keerthi Nelaturu, Eric Keilty, Andreas G. Veneris:
Natural Language-Based Model-Checking Framework for Move Smart Contracts. SDS 2023: 89-94 - 2022
- [j34]Yuxi Cai, Nafis Irtija, Eirini-Eleni Tsiropoulou, Andreas G. Veneris:
Truthful Decentralized Blockchain Oracles. Int. J. Netw. Manag. 32(2) (2022) - [j33]Zihan Zhao, Sidi Mohamed Beillahi, Ryan Song, Yuxi Cai, Andreas G. Veneris, Fan Long:
SigVM: enabling event-driven execution for truly decentralized smart contracts. Proc. ACM Program. Lang. 6(OOPSLA2): 673-698 (2022) - [j32]Nadia Pocher, Andreas G. Veneris:
Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. IEEE Trans. Netw. Serv. Manag. 19(2): 1776-1788 (2022) - [j31]Salil S. Kanhere, Andreas G. Veneris, Sachiko Yoshihama, Sandip Chakraborty, Ori Rottenstreich, Marta Beltrán Pardo, Bruno Rodriguez:
Guest Editorial: Special Issue on Recent Advances on Blockchain for Network and Service Management. IEEE Trans. Netw. Serv. Manag. 19(4): 3689-3693 (2022) - [c106]Sidi Mohamed Beillahi, Eric Keilty, Keerthi Nelaturu, Andreas G. Veneris, Fan Long:
Automated Auditing of Price Gouging TOD Vulnerabilities in Smart Contracts. ICBC 2022: 1-6 - [c105]Jemin Andrew Choi, Sidi Mohamed Beillahi, Peilun Li, Andreas G. Veneris, Fan Long:
LMPTs: Eliminating Storage Bottlenecks for Processing Blockchain Transactions. ICBC 2022: 1-9 - 2021
- [c104]James Meijers, Edward Au, Yuxi Cai, Hans-Arno Jacobsen, Shashank Motepalli, Robert Sun, Andreas G. Veneris, Gengrui Zhang, Shiquan Zhang:
Blockchain for V2X: A Taxonomy of Design Use Cases and System Requirements. BRAINS 2021: 113-120 - [c103]Keerthi Nelaturu, Sidi Mohamed Beillahi, Fan Long, Andreas G. Veneris:
Smart Contracts Refinement for Gas Optimization. BRAINS 2021: 229-236 - [c102]James Meijers, Guntur Dharma Putra, Grammateia Kotsialou, Salil S. Kanhere, Andreas G. Veneris:
Cost-Effective Blockchain-based IoT Data Marketplaces with a Credit Invariant. IEEE ICBC 2021: 1-9 - [c101]Nadia Pocher, Andreas G. Veneris:
Privacy and Transparency in CBDCs: A Regulation-by-Design AML/CFT Scheme. IEEE ICBC 2021: 1-9 - [i3]Ryan Song, Zihan Zhao, Yuxi Cai, Andreas G. Veneris, Fan Long:
SigVM: Toward Fully Autonomous Smart Contracts. CoRR abs/2102.10784 (2021) - 2020
- [j30]Neil Veira, Zissis Poulos, Andreas G. Veneris:
Searching for Bugs Using Probabilistic Suspect Implications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5267-5280 (2020) - [j29]Keerthi Nelaturu, John Adler, Marco Merlini, Ryan Berryhill, Neil Veira, Zissis Poulos, Andreas G. Veneris:
On Public Crowdsource-Based Mechanisms for a Decentralized Blockchain Oracle. IEEE Trans. Engineering Management 67(4): 1444-1458 (2020) - [c100]Yuxi Cai, Georgios Fragkos, Eirini-Eleni Tsiropoulou, Andreas G. Veneris:
A Truth-Inducing Sybil Resistant Decentralized Blockchain Oracle. BRAINS 2020: 128-135 - [c99]Yuxi Cai, Fan Long, Andreas G. Park, Andreas G. Veneris:
Engineering Economics in the Conflux Network. BRAINS 2020: 160-167 - [c98]Keerthi Nelaturu, Anastasia Mavridou, Andreas G. Veneris, Aron Laszka:
Verified Development and Deployment of Multiple Interacting Smart Contracts with VeriSolid. IEEE ICBC 2020: 1-9
2010 – 2019
- 2019
- [c97]Neil Veira, Zissis Poulos, Andreas G. Veneris:
Suspect2vec: a suspect prediction model for directed RTL debugging. ASP-DAC 2019: 681-686 - [c96]Ryan Berryhill, Andreas G. Veneris:
Chasing Minimal Inductive Validity Cores in Hardware Model Checking. FMCAD 2019: 19-27 - [c95]Marco Merlini, Neil Veira, Ryan Berryhill, Andreas G. Veneris:
On Public Decentralized Ledger Oracles via a Paired-Question Protocol. IEEE ICBC 2019: 337-344 - [c94]Neil Veira, Brian Keng, Kanchana Padmanabhan, Andreas G. Veneris:
Unsupervised Embedding Enhancements of Knowledge Graphs using Textual Associations. IJCAI 2019: 5218-5225 - [i2]Andreas G. Veneris, Andreas G. Park:
Special Drawing Rights in a New Decentralized Century. CoRR abs/1907.11057 (2019) - 2018
- [j28]Ryan Berryhill, Andreas G. Veneris:
Efficient suspect selection in unreachable state diagnosis. Ann. Math. Artif. Intell. 82(4): 261-277 (2018) - [j27]Ryan Berryhill, Andreas G. Veneris:
Methodologies for Diagnosis of Unreachable States via Property Directed Reachability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1298-1311 (2018) - [j26]Zissis Poulos, Andreas G. Veneris:
Failure Triage in RTL Regression Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1893-1906 (2018) - [c93]Neil Veira, Zissis Poulos, Andreas G. Veneris:
Suspect set prediction in RTL bug hunting. DATE 2018: 1544-1549 - [c92]John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania:
Astraea: A Decentralized Blockchain Oracle. iThings/GreenCom/CPSCom/SmartData 2018: 1145-1152 - [c91]Ryan Berryhill, Alexander Ivrii, Andreas G. Veneris:
Finding All Minimal Safe Inductive Sets. SAT 2018: 346-362 - [i1]John Adler, Ryan Berryhill, Andreas G. Veneris, Zissis Poulos, Neil Veira, Anastasia Kastania:
Astraea: A Decentralized Blockchain Oracle. CoRR abs/1808.00528 (2018) - 2017
- [j25]John Adler, Andreas G. Veneris:
Leveraging Software Configuration Management in Automated RTL Design Debug. IEEE Des. Test 34(5): 47-53 (2017) - [c90]John Adler, Ryan Berryhill, Andreas G. Veneris:
An extensible perceptron framework for revision RTL debug automation. ASP-DAC 2017: 257-262 - [c89]Ryan Berryhill, Alexander Ivrii, Neil Veira, Andreas G. Veneris:
Learning support sets in IC3 and Quip: The good, the bad, and the ugly. FMCAD 2017: 140-147 - [c88]Koushik Pal, Zissis Poulos, Edward Kim, Andreas G. Veneris:
Fast GPU-Based Influence Maximization Within Finite Deadlines via Node-Level Parallelism. ICDM 2017: 151-165 - [c87]Ryan Berryhill, Neil Veira, Andreas G. Veneris, Zissis Poulos:
Learning lemma support graphs in Quip and IC3. IVSW 2017: 105-110 - 2016
- [j24]Zissis Poulos, Andreas G. Veneris:
Exemplar-based Failure Triage for Regression Design Debugging. J. Electron. Test. 32(2): 125-136 (2016) - [c86]Ryan Berryhill, Andreas G. Veneris:
A complete approach to unreachable state diagnosability via property directed reachability. ASP-DAC 2016: 127-132 - [c85]John Adler, Djordje Maksimovic, Andreas G. Veneris:
Root-cause analysis for memory-locked errors. DATE 2016: 1054-1059 - [c84]Ryan Berryhill, Andreas G. Veneris:
Efficient Selection of Suspect Sets in Unreachable State Diagnosis. ISAIM 2016 - [c83]John Adler, Ryan Berryhill, Andreas G. Veneris:
Revision debug with non-linear version history in regression verification. IVSW 2016: 1-6 - [c82]Zissis Poulos, Ryan Berryhill, John Adler, Andreas G. Veneris:
On simulation-based metrics that characterize the behavior of RTL errors. SummerSim 2016: 14 - 2015
- [c81]Ryan Berryhill, Andreas G. Veneris:
Automated rectification methodologies to functional state-space unreachability. DATE 2015: 1401-1406 - [c80]Andrew Becker, Djordje Maksimovic, David Novo, Mohsen Ewaida, Andreas G. Veneris, Barbara Jobstmann, Paolo Ienne:
FudgeFactor: Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction. Haifa Verification Conference 2015: 259-275 - [c79]Djordje Maksimovic, Andreas G. Veneris, Zissis Poulos:
Clustering-based revision debug in regression verification. ICCD 2015: 32-37 - [c78]Zissis Poulos, Andreas G. Veneris:
Mining simulation metrics for failure triage in regression testing. IOLTS 2015: 182-187 - [c77]Zissis Poulos, Andreas G. Veneris:
Exemplar-based failure triage for regression design debugging. LATS 2015: 1-6 - [c76]Bao Le, Djordje Maksimovic, Dipanjan Sengupta, Erhan Ergin, Ryan Berryhill, Andreas G. Veneris:
Constructing stability-based clock gating with hierarchical clustering. PATMOS 2015: 97-102 - 2014
- [j23]Hratch Mangassarian, Bao Le, Andreas G. Veneris:
Debugging RTL Using Structural Dominance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 153-166 (2014) - [c75]Brian Keng, Evean Qin, Andreas G. Veneris, Bao Le:
Automated debugging of missing assumptions. ASP-DAC 2014: 732-737 - [c74]Djordje Maksimovic, Bao Le, Andreas G. Veneris:
Multiple clock domain synchronization in a QBF-based verification environment. ICCAD 2014: 684-689 - [c73]Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris, Bao Le:
Simulation and satisfiability guided counter-example triage for RTL design debugging. ISQED 2014: 618-624 - [c72]Zissis Poulos, Andreas G. Veneris:
Clustering-based failure triage for RTL regression debugging. ITC 2014: 1-10 - 2013
- [j22]Brian Keng, Andreas G. Veneris:
Path-Directed Abstraction and Refinement for SAT-Based Design Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(10): 1609-1622 (2013) - [c71]Bao Le, Dipanjan Sengupta, Andreas G. Veneris:
Reviving erroneous stability-based clock-gating using partial Max-SAT. ASP-DAC 2013: 717-722 - [c70]Bao Le, Dipanjan Sengupta, Andreas G. Veneris, Zissis Poulos:
Accelerating post silicon debug of deep electrical faults. IOLTS 2013: 61-66 - [c69]Zissis Poulos, Yu-Shen Yang, Andreas G. Veneris:
A failure triage engine based on error trace signature extraction. IOLTS 2013: 73-78 - [c68]Dipanjan Sengupta, Erhan Ergin, Andreas G. Veneris:
Early detection of current hot spots in power gated designs. ISLPED 2013: 45-50 - 2012
- [j21]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov:
Multi-objective voltage island floorplanning using sequence pair representation. Sustain. Comput. Informatics Syst. 2(2): 58-70 (2012) - [j20]Hratch Mangassarian, Andreas G. Veneris, Farid N. Najm:
Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(2): 271-284 (2012) - [j19]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici:
Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. IEEE Trans. Very Large Scale Integr. Syst. 20(6): 1118-1131 (2012) - [c67]Yu-Shen Yang, Andreas G. Veneris, Nicola Nicolici, Masahiro Fujita:
Automated data analysis techniques for a modern silicon debug environment. ASP-DAC 2012: 298-303 - [c66]Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita:
On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700 - [c65]Brian Keng, Andreas G. Veneris:
Path directed abstraction and refinement in SAT-based design debugging. DAC 2012: 947-954 - [c64]Zissis Poulos, Yu-Shen Yang, Jason Helge Anderson, Andreas G. Veneris, Bao Le:
Leveraging reconfigurability to raise productivity in FPGA functional debug. DATE 2012: 292-295 - [c63]Bao Le, Hratch Mangassarian, Brian Keng, Andreas G. Veneris:
Non-solution implications using reverse domination in a modern SAT-based debugging environment. DATE 2012: 629-634 - [c62]Brian Keng, Andreas G. Veneris:
Automated debugging of missing input constraints in a formal verification environment. FMCAD 2012: 101-105 - [c61]Dipanjan Sengupta, Flavio M. de Paula, Alan J. Hu, Andreas G. Veneris, André Ivanov:
Lazy suspect-set computation: fault diagnosis for deep electrical bugs. ACM Great Lakes Symposium on VLSI 2012: 189-194 - 2011
- [j18]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Transformations With Approximate SPFDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(5): 651-664 (2011) - [j17]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
Two-Stage, Pipelined Register Renaming. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1926-1931 (2011) - [c60]Andreas G. Veneris, Brian Keng, Sean Safarpour:
From RTL to silicon: The case for automated debug. ASP-DAC 2011: 306-310 - [c59]Brian Keng, Andreas G. Veneris:
Managing complexity in design debugging with sequential abstraction and refinement. ASP-DAC 2011: 479-484 - [c58]Brian Keng, Sean Safarpour, Andreas G. Veneris:
Automated debugging of SystemVerilog assertions. DATE 2011: 323-328 - [c57]Dipanjan Sengupta, Andreas G. Veneris, Steven J. E. Wilton, André Ivanov, Res Saleh:
Sequence pair based voltage island floorplanning. IGCC 2011: 1-6 - [c56]Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour:
Debugging with dominance: On-the-fly RTL debug solution implications. ICCAD 2011: 587-594 - 2010
- [j16]Hratch Mangassarian, Andreas G. Veneris, Marco Benedetti:
Robust QBF Encodings for Sequential Circuits with Applications to Verification, Debug, and Test. IEEE Trans. Computers 59(7): 981-994 (2010) - [j15]Brian Keng, Sean Safarpour, Andreas G. Veneris:
Bounded Model Debugging. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1790-1803 (2010) - [j14]Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris:
Automated Design Debugging With Maximum Satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1804-1817 (2010) - [j13]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
On the Latency and Energy of Checkpointed Superscalar Register Alias Tables. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 365-377 (2010) - [c55]Sean Safarpour, Andreas G. Veneris, Farid N. Najm:
Managing verification error traces with bounded model debugging. ASP-DAC 2010: 601-606 - [c54]Hratch Mangassarian, Bao Le, Alexandra Goultiaeva, Andreas G. Veneris, Fahiem Bacchus:
Leveraging dominators for preprocessing QBF. DATE 2010: 1695-1700 - [c53]Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour:
Automated silicon debug data analysis techniques for a hardware data acquisition environment. ISQED 2010: 675-682 - [c52]Brian Keng, Andreas G. Veneris, Sean Safarpour:
An Automated Framework for Correction and Debug of PSL Assertions. MTV 2010: 9-12
2000 – 2009
- 2009
- [j12]Sean Safarpour, Andreas G. Veneris:
Automated Design Debugging With Abstraction and Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(10): 1597-1608 (2009) - [c51]Andreas G. Veneris, Sean Safarpour:
The day Sherlock Holmes decided to do EDA. DAC 2009: 631-634 - [c50]Yu-Shen Yang, Nicola Nicolici, Andreas G. Veneris:
Automated data analysis solutions to silicon debug. DATE 2009: 982-987 - [c49]Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton, Duncan Exon Smith:
Sequential logic rectifications with approximate SPFDs. DATE 2009: 1698-1703 - [c48]Brian Keng, Andreas G. Veneris:
Scaling VLSI design debugging with interpolation. FMCAD 2009: 144-151 - [c47]Yibin Chen, Sean Safarpour, Andreas G. Veneris, João Marques-Silva:
Spatial and temporal design debug using partial MaxSAT. ACM Great Lakes Symposium on VLSI 2009: 345-350 - [c46]Sean Safarpour, Andreas G. Veneris:
Automated debugging with high level abstraction and refinement. HLDVT 2009: 26-31 - [c45]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors. ICSAMOS 2009: 41-48 - 2008
- [j11]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
Improved SAT-based Reachability Analysis with Observability Don't Cares. J. Satisf. Boolean Model. Comput. 5(1-4): 1-25 (2008) - [j10]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
L-CBF: A Low-Power, Fast Counting Bloom Filter Architecture. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 628-638 (2008) - [c44]Brian Keng, Hratch Mangassarian, Andreas G. Veneris:
A succinct memory model for automated design debugging. ICCAD 2008: 137-142 - [c43]Sobeeh Almukhaizim, Yiorgos Makris, Yu-Shen Yang, Andreas G. Veneris:
On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. IOLTS 2008: 123-128 - [c42]Elham Safi, Andreas Moshovos, Andreas G. Veneris:
A physical level study and optimization of CAM-based checkpointed register alias table. ISLPED 2008: 233-236 - 2007
- [c41]Yu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton:
Automating Logic Rectification by Approximate SPFDs. ASP-DAC 2007: 402-407 - [c40]Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian:
Trace Compaction using SAT-based Reachability Analysis. ASP-DAC 2007: 932-937 - [c39]Sean Safarpour, Andreas G. Veneris:
Abstraction and refinement techniques in automated design debugging. DATE 2007: 1182-1187 - [c38]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir:
Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543 - [c37]Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah:
Improved Design Debugging Using Maximum Satisfiability. FMCAD 2007: 13-19 - [c36]Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith:
A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. ICCAD 2007: 240-245 - [c35]Elham Safi, Patrick Akl, Andreas Moshovos, Andreas G. Veneris, Aggeliki Arapoyanni:
On the latency, energy and area of checkpointed, superscalar register alias tables. ISLPED 2007: 379-382 - 2006
- [j9]Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman:
Extraction error modeling and automated model debugging in high-performance custom designs. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 763-776 (2006) - [c34]