
Rainer Leupers
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- affiliation: RWTH Aachen University, Germany
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2020 – today
- 2020
- [j44]Jure Vreca
, Karl J. X. Sturm, Ernest Gungl
, Farhad Merchant
, Paolo Bientinesi, Rainer Leupers, Zmago Brezocnik
:
Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. IEEE Access 8: 165913-165926 (2020) - [j43]Milan Copic, Rainer Leupers, Gerd Ascheid:
Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling. Integr. 70: 10-20 (2020) - [c202]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. ARCS 2020: 56-68 - [c201]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß:
Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS 2020: 138-152 - [c200]Andre Guntoro, Cecilia De la Parra
, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar:
Next Generation Arithmetic for Edge Computing. DATE 2020: 1357-1365 - [c199]Lukas Jünger, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann:
ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms. DATE 2020: 1508-1513 - [c198]Milan Copic, Rainer Leupers, Gerd Ascheid:
Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables. ISSRE 2020: 127-137 - [c197]Lukas Jünger
, Niko Zurstraßen
, Tim Kogel
, Holger Keding
, Rainer Leupers:
AMAIX: A Generic Analytical Model for Deep Learning Accelerators. SAMOS 2020: 36-51 - [c196]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß:
A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES 2020: 62-65 - [i9]Riya Jain, Niraj Sharma, Farhad Merchant, Sachin Patkar, Rainer Leupers:
CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR abs/2006.00364 (2020) - [i8]Andreas Bytyn, René Ahlsdorf, Rainer Leupers, Gerd Ascheid:
Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect. CoRR abs/2006.12274 (2020) - [i7]Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers:
Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR abs/2011.10389 (2020) - [i6]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Syun-Kun Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR abs/2012.12563 (2020)
2010 – 2019
- 2019
- [j42]Gereon Führ
, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs. IEEE Embed. Syst. Lett. 11(3): 93-96 (2019) - [j41]Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. Integr. 69: 50-61 (2019) - [c195]Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers:
Combined MPSoC Task Mapping and Memory Optimization for Low-Power. APCCAS 2019: 121-124 - [c194]Milan Copic, Rainer Leupers, Gerd Ascheid:
Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration. ASP-DAC 2019: 603-608 - [c193]Gereon Onnebrink
, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen:
A heuristic for multi objective software application mappings on heterogeneous MPSoCs. ASP-DAC 2019: 609-614 - [c192]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss:
Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS 2019: 1-6 - [c191]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss:
Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI 2019: 27-32 - [c190]Sebastian Birke, Dominik Auras, Tobias Piwczyk, Robin Mahlke, Nikolas Alberti, Rainer Leupers, Gerd Ascheid:
VLSI Architectures for ORVD Trellis based MIMO Detection. ICNC 2019: 983-989 - [c189]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ISCAS 2019: 1-5 - [c188]Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Fast SystemC Processor Models with Unicorn. RAPIDO 2019: 2:1-2:6 - [c187]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers:
Protecting the Integrity of Processor Cores with Logic Encryption. SoCC 2019: 424-425 - [c186]Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Volker Kiefer:
A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT 2019: 1-4 - [c185]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSI Design 2019: 64-69 - [c184]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Applying Modified Householder Transform to Kalman Filter. VLSI Design 2019: 431-436 - [i5]Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. CoRR abs/1904.05106 (2019) - 2018
- [c183]Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping. APCCAS 2018: 532-535 - [c182]Jan Henrik Weinstock, Robert Lajos Bücs, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress. CODES+ISSS 2018: 13 - [c181]Robert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann:
OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. DATE 2018: 281-284 - [c180]Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers:
Parameterized Posit Arithmetic Hardware Generator. ICCD 2018: 334-341 - [c179]Dominik Auras, Sebastian Birke, Rainer Leupers, Gerd Ascheid:
Reducing the Computational Complexity of ORVD-Trellis Search Based MIMO Detection. ICNC 2018: 315-321 - [c178]Robert Lajos Bücs, Marcel Heistermann, Rainer Leupers, Gerd Ascheid:
Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach. ICVES 2018: 1-8 - [c177]Sebastian Birke, Wei-Jhe Chen, Gaojian Wang, Dominik Auras, Chung-An Shen, Rainer Leupers, Gerd Ascheid:
VLSI implementation of channel estimation for millimeter wave beamforming training. LASCAS 2018: 1-4 - [c176]Koen De Bosschere, Rainer Leupers:
HiPEAC compilation architecture. MECO 2018: 13 - [c175]Gereon Onnebrink
, Rainer Leupers, Gerd Ascheid:
ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models. RAPIDO 2018: 1:1-1:6 - [c174]Dominik Sisejkovic, Rainer Leupers, Gerd Ascheid, Simon Metzner:
A Unifying logic encryption security metric. SAMOS 2018: 179-186 - [c173]Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
A Multi-domain Co-simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping. SMARTGREENS/VEHITS (Selected Papers) 2018: 181-201 - [c172]Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid:
Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem. VEHITS 2018: 59-69 - [i4]Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers:
Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR abs/1803.05320 (2018) - 2017
- [j40]Miguel Angel Aguilar
, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. Int. J. Parallel Program. 45(6): 1592-1624 (2017) - [c171]Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick:
Multi-grained performance estimation for MPSoC compilers: work-in-progress. CASES 2017: 14:1-14:2 - [c170]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick:
Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack. DATE 2017: 1237-1240 - [c169]María H. Auras-Rodríguez, Anthony Zimmermann, Gerd Ascheid, Rainer Leupers:
Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition. PARMA-DITAM@HiPEAC 2017: 13-18 - [c168]Andreas Bytyn, Jannik Springer, Rainer Leupers, Gerd Ascheid:
VLSI implementation of LS-SVM training and classification using entropy based subset-selection. ISCAS 2017: 1-4 - [c167]Robert Lajos Bücs, Juan Sebastian Reyes Aristizabal, Rainer Leupers, Gerd Ascheid:
Multi-level vehicle dynamics modeling and export for ADAS prototyping in a 3D driving environment. ITSC 2017: 1-8 - [c166]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models. RAPIDO 2017: 2 - [c165]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse:
Extraction of recursion level parallelism for embedded multicore systems. SAMOS 2017: 154-162 - [c164]Gereon Onnebrink, Florian Walbroel, Jonathan Klimt, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo, Stefan Schürmans, Xiaotao Chen, YwhPyng Harn:
DVFS-enabled power-performance trade-off in MPSoC SW application mapping. SAMOS 2017: 196-202 - [p4]Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng:
MAPS: A Software Development Environment for Embedded Multicore Applications. Handbook of Hardware/Software Codesign 2017: 917-949 - 2016
- [j39]Andres Goens
, Jerónimo Castrillón
, Maximilian Odendahl, Rainer Leupers:
An optimal allocation of memory buffers for complex multicore platforms. J. Syst. Archit. 66-67: 69-83 (2016) - [j38]Pier Stanislao Paolucci
, Andrea Biagioni
, Luis Gabriel Murillo, Frédéric Rousseau
, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli
, Elena Pastorelli
, Devendra Rai, Davide Rossetti
, Francesco Simula
:
Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. 69: 29-53 (2016) - [j37]Daniel Günther
, Rainer Leupers, Gerd Ascheid:
A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(8): 1283-1294 (2016) - [j36]Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs. ACM Trans. Embed. Comput. Syst. 16(1): 7:1-7:25 (2016) - [j35]Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model. ACM Trans. Embed. Comput. Syst. 16(1): 26:1-26:26 (2016) - [j34]Jan Henrik Weinstock, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid:
Parallel SystemC Simulation for ESL Design. ACM Trans. Embed. Comput. Syst. 16(1): 27:1-27:25 (2016) - [j33]Daniel Günther, Rainer Leupers, Gerd Ascheid:
Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 567-577 (2016) - [c163]Marius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang, Giorgis Georgakoudis
, Dimitrios S. Nikolopoulos
, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu:
Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting. ARCS 2016: 277-289 - [c162]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo:
Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. DAC 2016: 49:1-49:6 - [c161]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann:
SystemC-link: Parallel SystemC simulation using time-decoupled segments. DATE 2016: 493-498 - [c160]Rainer Leupers:
Technology Transfer in computing systems: The TETRACOM approach. DATE 2016: 834-837 - [c159]Daniel Günther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid:
Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing. DATE 2016: 1028-1029 - [c158]Gereon Onnebrink, Stefan Schürmans, Florian Walbroel, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, YwhPyng Harn:
Black box power estimation for digital signal processors using virtual platforms. RAPIDO@HiPEAC 2016: 6:1-6:6 - [c157]Dominik Auras, Sebastian Birke, Tobias Piwczyk, Rainer Leupers, Gerd Ascheid:
A flexible MCMC detector ASIC. ISOCC 2016: 285-286 - [c156]Dominik Auras, Rainer Leupers, Gerd Ascheid:
ORVD-Trellis based MIMO detection. NEWCAS 2016: 1-4 - [c155]Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid:
Concurrent memory subsystem and application optimization for ASIP design. SAMOS 2016: 1-10 - [c154]Maria H. Rodriguez Blanco, Georg Reinke, Gerd Ascheid, Rainer Leupers:
Automatic recognition of computational kernels for platform-dependent code optimizations. SAMOS 2016: 11-20 - [c153]Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Stefan Schürmans:
Black box ESL power estimation for loosely-timed TLM models. SAMOS 2016: 366-371 - 2015
- [j32]Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers:
CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design. ACM Trans. Reconfigurable Technol. Syst. 8(3): 17:1-17:16 (2015) - [j31]Xiaolin Chen, Andreas Minwegen, Bilal Syed Hussain, Anupam Chattopadhyay, Gerd Ascheid, Rainer Leupers:
Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2173-2186 (2015) - [c152]Miguel Angel Aguilar, Rainer Leupers:
Unified Identification of Multiple Forms of Parallelism in Embedded Applications. PACT 2015: 482-483 - [c151]Luis Gabriel Murillo
, Robert Lajos Bücs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid:
SWAT: Assertion-based debugging of concurrency issues at system level. ASP-DAC 2015: 600-605 - [c150]Ayman Tarakji, Marwan Hassani
, Lyubomir Georgiev, Thomas Seidl
, Rainer Leupers:
Parallel Density-Based Stream Clustering Using a Multi-user GPU Scheduler. BDAS 2015: 343-360 - [c149]Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers:
Multi/many-core programming: where are we standing? DATE 2015: 1708-1717 - [c148]Robert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann:
Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. FDL 2015: 49-56 - [c147]Miguel Angel Aguilar, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Maximilian Odendahl:
Extraction of Kahn Process Networks from While Loops in Embedded Software. HPCC/CSS/ICESS 2015: 1078-1085 - [c146]Cosmin Cernazanu-Glavan, Marius Marcu, Alexandru Amaricai, Stefan Fedeac, Madalin Ghenea, Zheng Wang, Anupam Chattopadhyay, Jan Weinstock, Rainer Leupers:
Direct FPGA-based power profiling for a RISC processor. I2MTC 2015: 1578-1583 - [c145]Maximilian Odendahl, Andres Goens
, Rainer Leupers, Gerd Ascheid, Tomas Henriksson:
Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms. IPDPS Workshops 2015: 1119-1124 - [c144]Ayman Tarakji, Lukas Börger, Rainer Leupers:
A comparative investigation of device-specific mechanisms for exploiting HPC accelerators. GPGPU@PPoPP 2015: 1-12 - [c143]Zoltán Endre Rákossy, Axel Acosta Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Design and synthesis of reconfigurable control-flow structures for CGRA. ReConFig 2015: 1-8 - [c142]Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma:
Parallelism extraction in embedded software for android devices. SAMOS 2015: 9-17 - [c141]Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid:
Deterministic event-based control of Virtual Platforms for MPSoC software debugging. SAMOS 2015: 348-353 - [c140]Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
ESL power estimation using virtual platforms with black box processor models. SAMOS 2015: 354-359 - [c139]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Parallel SystemC simulation for ESL design using flexible time decoupling. SAMOS 2015: 378-383 - [c138]Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias:
A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms. SCOPES 2015: 76-79 - [c137]Juan Fernando Eusse, Luis Gabriel Murillo
, Christopher McGirr, Rainer Leupers, Gerd Ascheid:
Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. SCOPES 2015: 84-87 - [c136]Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid:
Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator. SCOPES 2015: 129-132 - [c135]Ayman Tarakji, Alexander Gladis, Tarek Anwar, Rainer Leupers:
Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling. TrustCom/BigDataSE/ISPA (3) 2015: 45-52 - [c134]Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay:
Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. VLSI-SoC 2015: 337-342 - 2014
- [j30]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
A compiler infrastructure for embedded heterogeneous MPSoCs. Parallel Comput. 40(2): 51-68 (2014) - [j29]Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Laura Tosoratto, Alessandro Lonardo, Dietmar Petras, Andreas Hoffmann:
legaSCi: Legacy SystemC Model Integration into Parallel Simulators. ACM Trans. Embed. Comput. Syst. 13(5s): 165:1-165:24 (2014) - [c133]Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue:
A flexible ASIP architecture for connected components labeling in embedded vision applications. DATE 2014: 1-6 - [c132]Rainer Leupers, Norbert Wehn, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson:
Technology transfer towards Horizon 2020. DATE 2014: 1 - [c131]Luis Gabriel Murillo
, Simon Wawroschek, Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
Automatic detection of concurrency bugs through event ordering constraints. DATE 2014: 1-6 - [c130]Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson:
Optimized buffer allocation in multicore platforms. DATE 2014: 1-6 - [c129]Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto:
Time-decoupled parallel SystemC simulation. DATE 2014: 1-4 - [c128]Dominik Auras, Dominik Rieth, Rainer Leupers, Gerd Ascheid:
VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract. ACM Great Lakes Symposium on VLSI 2014: 71-72 - [c127]Dominik Auras, Rainer Leupers, Gerd H. Ascheid:
A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture. ICC 2014: 4722-4728 - [c126]Benjamin Ries, Walter Unger, Maximilian Odendahl, Rainer Leupers:
A heuristic for logical data buffer allocation in multicore platforms. IPCCC 2014: 1-2 - [c125]Dominik Auras, Rainer Leupers, Gerd Ascheid:
Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors. ISCAS 2014: 1018-1021 - [c124]Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo
, Pier Stanislao Paolucci
, Frédéric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini
, Jan Weinstock:
EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. ISPA 2014: 182-189 - [c123]Daniel Günther, Andreas Bytyn, Rainer Leupers, Gerd Ascheid:
Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems. ISSoC 2014: 1-7 - [c122]Dominik Auras, Rainer Leupers, Gerd Ascheid:
A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture. ISVLSI 2014: 41-47 - [c121]Juan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo
, Rainer Leupers, Gerd Ascheid:
Pre-architectural performance estimation for ASIP design based on abstract processor models. ICSAMOS 2014: 133-140 - [c120]Stefan Schürmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Xiaotao Chen:
Improving ESL power models using switching activity information from timed functional models. SCOPES 2014: 89-97 - [c119]Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers. VLSI-SoC 2014: 1-6 - [c118]Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid:
A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm. VLSI-SoC (Selected Papers) 2014: 149-169 - 2013
- [j28]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid:
Automatic Calibration of Streaming Applications for Software Mapping Exploration. IEEE Des. Test 30(3): 49-58 (2013) - [j27]Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout:
Efficient Implementation of Application-Aware Spinlock Control in MPSoCs. Int. J. Embed. Real Time Commun. Syst. 4(1): 64-84 (2013) - [j26]Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid:
MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs. IEEE Trans. Ind. Informatics 9(1): 527-545 (2013) - [c117]Massimiliano Donati
, Sergio Saponara
, Luca Fanucci, Walter Errico, Annamaria Colonna, Giuseppe Piscopiello, Giovanni Tuccio, Franco Bigongiari, Maximilian Odendahl, Rainer Leupers, Antonio Spada, Vincenzo Pii, Elena Cordiviola, Francesco Nuzzolo, Frederic Reiter:
A New Space Digital Signal Processor Design. ApplePies 2013: 51-60 - [c116]Stefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang:
Creation of ESL power models for communication architectures using automatic calibration. DAC 2013: 58:1-58:58 - [c115]Weihua Sheng, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
Embedded Real-Time Application Prototyping Using a Hybrid Multiprocessing Platform. HPCC/EUC 2013: 1745-1750 - [c114]Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Laura Tosoratto, Alessandro Lonardo, Dietmar Petras, Thorsten Grötker:
legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators. IPDPS Workshops 2013: 2188-2193 - [c113]Maximilian Odendahl, Jerónimo Castrillón, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
Split-cost communication model for improved MPSoC application mapping. ISSoC 2013: 1-8 - [c112]Daniel Günther, Rainer Leupers, Gerd Ascheid:
Mapping of MIMO Receiver Algorithms onto Application-Specific Multi-Core Platforms. ISWCS 2013: 1-5 - [c111]Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid:
A compiler infrastructure for embedded heterogeneous MPSoCs. PMAM 2013: 1-10 - [c110]