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ORCID24th DDECS 2021: Vienna, Austria
- Muhammad Shafique, Andreas Steininger, Lukás Sekanina, Milos Krstic, Goran Stojanovic, Vojtech Mrazek:
24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2021, Vienna, Austria, April 7-9, 2021. IEEE 2021, ISBN 978-1-6654-3595-6 - Alija Dervic
, Saman Kohneh Poushi, Horst Zimmermann:
Fully-integrated SPAD active quenching/resetting circuit in high-voltage 0.35-μ m CMOS for reaching PDP saturation at 650 nm. 1-5 - Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Michal Sovcik, Viera Stopjaková:
EKV MOS Transistor Model For Ultra Low-Voltage Bulk-Driven IC Design. 6-10 - Nicola Dall'Ora, Sadia Azam, Enrico Fraccaroli, André Alberts, Franco Fummi:
Predictive Fault Grouping based on Faulty AC Matrices. 11-16 - Zdenek Vasícek:
Synthesis of approximate circuits for LUT-based FPGAs. 17-22 - Christoph Niemann, Michael Rethfeldt, Dirk Timmermann:
Approximate Multipliers for Optimal Utilization of FPGA Resources. 23-28 - Jianan Wen, Markus Ulbricht, Eduardo Pérez, Xin Fan, Milos Krstic:
Behavioral Model of Dot-Product Engine Implemented with 1T1R Memristor Crossbar Including Assessment. 29-32 - Nurettin Bölücü, Suleyman Tosun:
Q-Learning-based Routing Algorithm for 3D Network-on-Chips. 33-36 - Olivier Sentieys, Silviu-Ioan Filip, David Briand, David Novo, Etienne Dupuis, Ian O'Connor, Alberto Bosio:
AdequateDL: Approximating Deep Learning Accelerators. 37-40 - Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez, Luigi Dilillo:
A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. 41-44 - Alessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio:
Efficient Neural Network Approximation via Bayesian Reasoning. 45-50 - Aleksa Damljanovic, Annachiara Ruospo, Ernesto Sánchez, Giovanni Squillero:
A Benchmark Suite of RT-level Hardware Trojans for Pipelined Microprocessor Cores. 51-56 - Mitko Veleski, Michael Hübner, Milos Krstic, Rolf Kraemer:
Design and Implementation Strategy of Adaptive Processor-Based Systems for Error Resilient and Power-Efficient Operation. 57-62 - Raghda El Shehaby, Andreas Steininger:
Analysis of State Corruption caused by Permanent Faults in WCHB-based Quasi Delay-Insensitive Pipelines. 63-68 - Davide Appello, Paolo Bernardi, Andrea Calabrese, Stefano Littardi, Giorgio Pollaccia, Stefano Quer, Vincenzo Tancorre, Roberto Ugioli:
Accelerated Analysis of Simulation Dumps through Parallelization on Multicore Architectures. 69-74 - Hassan Ebrahimi, Hans G. Kerkhoff:
Embedded Test Instrument for Intermittent Resistive Fault Detection at Chip Level and Its Reuse at Board Level. 75-80 - Juan-David Guerrero-Balaguera, Josie E. Rodriguez Condia, Matteo Sonza Reorda:
On the Functional Test of Special Function Units in GPUs. 81-86 - Denis Dutey, Stephane Martin, Anne Merlande, Om Ranjan:
Prevention and Detection Methods of Systematic Failures in the Implementation of SoC Safety Mechanisms not Covered by Regular Functional Tests. 87-92 - Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola:
Emerging Technologies: Challenges and Opportunities for Logic Synthesis. 93-98 - Rolf Drechsler:
PolyAdd: Polynomial Formal Verification of Adder Circuits. 99-104 - Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. 105-110 - Josef Strnadel:
Using Model Checker to Analyze and Test Digital Circuits with Regard to Delay Faults. 111-114 - Roman Vrána, Jan Korenek:
Efficient Acceleration of Decision Tree Algorithms for Encrypted Network Traffic Analysis. 115-118 - David Maljar, Michal Sovcík, Daniel Arbet, Viera Stopjaková:
Enhanced Reliability of Fully Differential Difference Amplifier Through On-chip Digital Calibration. 119-122 - Martin Skriver, Anders Stengaard Sørensen, Ulrik Pagh Schultz:
HEIST: A Hardware Signal Fault Injection Methodology Enabling Feasible Software Robustness Testing. 123-126 - Ameer Shalabi, Tara Ghasempouri, Peeter Ellervee, Jaan Raik:
CLD: An Accurate, Cost-Effective and Scalable Run-Time Cache Leakage Detector. 127-132 - Pawel Skrzypiec, Robert Szczygiel:
Development of On-Chip Calibration for Hybrid Pixel Detectors. 133-136 - Lukasz A. Kadlubowski, Piotr Kmon:
Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array. 137-140 - Vukan D. Damnjanovic, Marija L. Petrovic, Vladimir M. Milovanovic:
A Parameterizable Chisel Generator of Numerically Controlled Oscillators for Direct Digital Synthesis. 141-144 - Malik Imran, Zain Ul Abideen, Samuel Pagliarini:
An Open-source Library of Large Integer Polynomial Multipliers. 145-150 - Michal Orsák, Tomás Benes:
High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories. 151-156 - Zoran Stamenkovic, Hassen Aziza, Ernesto Sánchez, Alberto Bosio:
Tutorial: Silicon Systems for Wireless LAN. 157-158
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