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2020 – today
- 2021
[i1]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
Fast Exploration of Weight Sharing Opportunities for CNN Compression. CoRR abs/2102.01345 (2021)- 2020
- [j35]Marcello Traiola
, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE 108(12): 2178-2194 (2020) - [c149]Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich:
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP 2020: 157-164 - [c148]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Maximizing Yield for Approximate Integrated Circuits. DATE 2020: 810-815 - [c147]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression. DATE 2020: 1319-1322 - [c146]Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio:
Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing. DDECS 2020: 1-6 - [c145]Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo:
Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. DFT 2020: 1-6 - [c144]Dario Mamone, Alberto Bosio, Alessandro Savino, Said Hamdioui, Maurizio Rebaudengo:
On the Analysis of Real-time Operating System Reliability in Embedded Systems. DFT 2020: 1-6 - [c143]Annachiara Ruospo, Angelo Balaara, Alberto Bosio, Ernesto Sánchez:
A Pipelined Multi-Level Fault Injector for Deep Neural Networks. DFT 2020: 1-6 - [c142]Annachiara Ruospo, Alberto Bosio, Alessandro Ianne, Ernesto Sánchez:
Evaluating Convolutional Neural Networks Reliability depending on their Data Representation. DSD 2020: 672-679 - [c141]Alberto Bosio, Ramon Canal, Stefano Di Carlo, Dimitris Gizopoulos, Alessandro Savino:
Cross-Layer Soft-Error Resilience Analysis of Computing Systems. DSN (Supplements) 2020: 79 - [c140]Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Lima, Said Hamdioui:
Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms. DTIS 2020: 1-2 - [c139]Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo:
Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. DTIS 2020: 1-6 - [c138]Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel:
Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS 2020: 1-10 - [c137]S. Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar:
Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS 2020: 1-2 - [c136]S. Mhamdi, P. Girard, Arnaud Virazel, Alberto Bosio, A. Ladhar:
A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC 2020: 1-10
2010 – 2019
- 2019
- [j34]Maha Kooli, Giorgio Di Natale, Alberto Bosio:
Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems. J. Electron. Test. 35(2): 145-162 (2019) - [j33]Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection. J. Electron. Test. 35(3): 367-381 (2019) - [j32]Alberto Bosio, Mario Barbareschi:
Special Issue on Design, Technology, and Test of Integrated Circuits and Systems. J. Circuits Syst. Comput. 28(Supplement-1): 1902001:1-1902001:1 (2019) - [j31]Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Marti Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo:
SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. IEEE Trans. Computers 68(5): 765-783 (2019) - [c135]Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, Surya Nagarajan, Moritz Fieback, Said Hamdioui:
Rebooting Computing: The Challenges for Test and Reliability. DFT 2019: 8138-8143 - [c134]Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale:
Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS 2019: 1-10 - [c133]Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar:
Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS 2019: 21-26 - [c132]Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková:
International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC 2019: 1-4 - [c131]Alberto Bosio, Paolo Bernardi, Annachiara Ruospo, Ernesto Sánchez:
A Reliability Analysis of a Deep Neural Network. LATS 2019: 1-6 - [c130]Gennaro Severino Rodrigues, Juan Fonseca, Fabio Benevenuti, Fernanda Lima Kastensmidt, Alberto Bosio:
Exploiting approximate computing for low-cost fault tolerant architectures. SBCCI 2019: 3 - [c129]Alberto Bosio, Wilson Javier Perez Holguin, Ernesto Sánchez:
Exploiting Approximate Computing to Increase System Lifetime. VLSI-SoC 2019: 311-316 - 2018
- [j30]Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena Ioana Vatajelu:
Test and Reliability in Approximate Computing. J. Electron. Test. 34(4): 375-387 (2018) - [j29]Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Estimating dynamic power consumption for memristor-based CiM architecture. Microelectron. Reliab. 80: 241-248 (2018) - [j28]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray:
Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. 6(2): 278-287 (2018) - [c128]Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio:
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs. ARC 2018: 647-658 - [c127]Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Alberto Bosio, Fernanda Lima Kastensmidt, Edison Pignaton de Freitas:
ARFT: An Approximative Redundant Technique for Fault Tolerance. DCIS 2018: 1-6 - [c126]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS 2018: 85-90 - [c125]Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio:
Synthesis of Finite State Machines on Memristor Crossbars. DDECS 2018: 107-112 - [c124]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT 2018: 1-6 - [c123]Marcello Traiola, Alessandro Savino, Mario Barbareschi, Stefano Di Carlo, Alberto Bosio:
Predicting the Impact of Functional Approximation: from Component- to Application-Level. IOLTS 2018: 61-64 - [c122]Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications. IOLTS 2018: 291-294 - [c121]Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard:
An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC 2018: 1-8 - [c120]Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio:
Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection. LATS 2018: 1-6 - [c119]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Testing approximate digital circuits: Challenges and opportunities. LATS 2018: 1-6 - [c118]Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel A. G. de Oliveira, Fernando Fernandes, Stefano Di Carlo:
Special session: How approximate computing impacts verification, test and reliability. VTS 2018: 1 - 2017
- [j27]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. 33(1): 25-36 (2017) - [j26]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. 26(8): 1740004:1-1740004:19 (2017) - [j25]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. 26(8): 1740007:1-1740007:18 (2017) - [j24]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. 13(1): 10-28 (2017) - [j23]Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres:
Computing reliability: On the differences between software testing and software fault injection techniques. Microprocess. Microsystems 50: 102-112 (2017) - [c117]Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards approximation during test of Integrated Circuits. DDECS 2017: 28-33 - [c116]Marcello Traiola, Mario Barbareschi, Alberto Bosio:
Formal Design Space Exploration for memristor-based crossbar architecture. DDECS 2017: 145-150 - [c115]Mario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, Elena Ioana Vatajelu:
Memristive devices: Technology, design automation and computing frontiers. DTIS 2017: 1-8 - [c114]G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi:
An effective fault-injection framework for memory reliability enhancement perspectives. DTIS 2017: 1-6 - [c113]Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
Towards digital circuit approximation by exploiting fault simulation. EWDTS 2017: 1-7 - [c112]Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle:
Reliability of computing systems: From flip flops to variables. IOLTS 2017: 196-198 - [c111]Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi:
Approximate computing: Design & test for integrated circuits. LATS 2017: 1 - 2016
- [j22]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda:
A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. 32(2): 147-161 (2016) - [j21]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot:
Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. 25(3): 1640013:1-1640013:18 (2016) - [c110]Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori:
System-level reliability evaluation through cache-aware software-based fault injection. DDECS 2016: 9-14 - [c109]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective approach for functional test programs compaction. DDECS 2016: 119-124 - [c108]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A hybrid power modeling approach to enhance high-level power models. DDECS 2016: 151-156 - [c107]Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel:
Auto-adaptive ultra-low power IC. DTIS 2016: 1-6 - [c106]Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS 2016: 1-2 - [c105]Alberto Bosio, Patrick Girard, Arnaud Virazel:
Test of low power circuits: Issues and industrial practices. ICECS 2016: 524-527 - [c104]Maha Kooli, Giorgio Di Natale, Alberto Bosio:
Cache-aware reliability evaluation through LLVM-based analysis and fault injection. IOLTS 2016: 19-22 - [c103]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan:
An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED 2016: 185-191 - [c102]Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio:
Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED 2016: 295-300 - [c101]Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI 2016: 731-736 - [c100]Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale:
Cross-layer system reliability assessment framework for hardware faults. ITC 2016: 1-10 - [c99]Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini:
Faster-than-at-speed execution of functional programs: An experimental analysis. VLSI-SoC 2016: 1-6 - [c98]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC 2016: 1-6 - [c97]Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio:
XbarGen: A memristor based boolean logic synthesis tool. VLSI-SoC 2016: 1-6 - [c96]Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sánchez, Federico Venini:
Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs. VLSI-SoC (Selected Papers) 2016: 130-151 - [c95]J. Alt, Paolo Bernardi, Alberto Bosio, Riccardo Cantoro, Hans G. Kerkhoff, Andreas Leininger, Wolfgang Molzer, Alessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, R. Strasser:
Thermal issues in test: An overview of the significant aspects and industrial practice. VTS 2016: 1-4 - [c94]Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio:
Cache- and register-aware system reliability evaluation based on data lifetime analysis. VTS 2016: 1-6 - 2015
- [j20]Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Gianfranco Politano, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo:
Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview. Microprocess. Microsystems 39(8): 1204-1214 (2015) - [c93]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Exploring the impact of functional test programs re-used for power-aware testing. DATE 2015: 1277-1280 - [c92]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot:
Design-for-Diagnosis Architecture for Power Switches. DDECS 2015: 43-48 - [c91]Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
An effective ATPG flow for Gate Delay Faults. DTIS 2015: 1-6 - [c90]Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres:
Software testing and software fault injection. DTIS 2015: 1-6 - [c89]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda:
Scan-chain intra-cell defects grading. DTIS 2015: 1-6 - [c88]Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard:
An effective hybrid fault-tolerant architecture for pipelined cores. ETS 2015: 1-6 - [c87]Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier:
An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM 2015: 17-20 - [c86]Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda:
Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS 2015: 89-94 - [c85]Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard:
Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED 2015: 366-370 - [c84]Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch:
An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI 2015: 515-520 - 2014
- [j19]D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich:
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. 30(4): 401-413 (2014) - [j18]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray:
Intra-Cell Defects Diagnosis. J. Electron. Test. 30(5): 541-555 (2014) - [j17]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine:
On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. 30(5): 611-627 (2014) - [j16]Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2131-2144 (2014) - [j15]Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay:
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. 22(11): 2326-2335 (2014) - [c83]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC 2014: 544-549 - [c82]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray:
On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS 2014: 312-317 - [c81]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Timing-aware ATPG for critical paths with multiple TSVs. DDECS 2014: 116-121 - [c80]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS 2014: 207-212 - [c79]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
Test and diagnosis of power switches. DDECS 2014: 213-218 - [c78]Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri:
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS 2014: 223-225 - [c77]Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi:
An intra-cell defect grading tool. DDECS 2014: 298-301 - [c76]Luca Cassano, Alberto Bosio, Giorgio Di Natale:
A novel adaptive fault tolerant flip-flop architecture based on TMR. ETS 2014: 1-2 - [c75]Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot:
iBoX - Jitter based Power Supply Noise sensor. ETS 2014: 1-2 - [c74]Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel:
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI 2014: 226-231 - [c73]Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi:
A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW 2014: 69-72 - [c72]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS 2014: 1-6 - 2013
- [j14]Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard:
Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. 9(2): 253-263 (2013) - [j13]Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel:
A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. 21(2): 306-319 (2013) - [j12]Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel:
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. 21(5): 958-970 (2013) - [c71]Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium 2013: 109-114 - [c70]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Test solution for data retention faults in low-power SRAMs. DATE 2013: 442-447 - [c69]Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS 2013: 143-148 - [c68]Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS 2013: 39-44 - [c67]Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville:
Computing detection probability of delay defects in signal line tsvs. ETS 2013: 1-6 - [c66]Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS 2013: 1-6 - [c65]Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné:
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS 2013: 145-150 - [c64]Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray:
Effect-cause intra-cell diagnosis at transistor level. ISQED 2013: 460-467 - [c63]Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vevet, Marc Belleville:
A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI 2013: 121-126 - [c62]Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine:
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC 2013: 1-10 - [c61]Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, J. Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné:
Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI 2013: 75-80 - [c60]