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ORCIDVLSI-SoC 2005: Perth, Australia
- Ricardo Augusto da Luz Reis, Adam Osseiran, Hans-Jörg Pfleiderer:
VLSI-SoC: From Systems To Silicon, Proceedings of IFIP TC 10, WG 10.5, Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2005), October 17-19, 2005, Perth, Australia. IFIP 240, Springer 2007, ISBN 978-0-387-73660-0 - Paul D. Franzon, David Nackashi, Christian Amsinck, Neil Di Spigna, Sachin Sonkusale:
Molecular Electronics - Devices and Circuits Technology. 1-10 - G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard:
Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals. 11-24 - Leonardo Londero de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa
, José Monteiro, João Baptista dos Santos Martins, Sergio Bampi, Ricardo Augusto da Luz Reis:
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. 25-39 - Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert:
Defragmentation Algorithms for Partially Reconfigurable Hardware. 41-53 - Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin:
Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits. 55-69 - Chul Kim, A. M. Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian:
3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System. 71-86 - Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto:
Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms. 87-109 - Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici:
A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis. 111-125 - João M. S. Silva, L. Miguel Silveira:
Issues in Model Reduction of Power Grids. 127-144 - Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen:
A Traffic Injection Methodology with Support for System-Level Synchronization. 145-161 - Jun-Cheol Park, Vincent John Mooney III:
Pareto Points in SRAM Design Using the Sleepy Stack Approach. 163-177 - César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis:
Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. 179-194 - Jerome Quartana, Laurent Fesquet, Marc Renaudin:
Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping. 195-207 - Muhsen Aljada, Kamal E. Alameh, Adam Osseiran, Khalid Al-Begain:
A Novel MicroPhotonic Structure for Optical Header Recognition. 209-219 - Erik Larsson, Stina Edbom:
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint. 221-244 - Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur:
On-chip Pseudorandom Testing for Linear and Nonlinear MEMS. 245-266 - Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault:
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. 267-281 - Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner:
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. 283-297 - Rüdiger Ebendt, Rolf Drechsler:
Exact BDD Minimization for Path-Related Objective Functions. 299-315 - Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Michel Robert, Guy Cathébras, Gilles Sassatelli, Fernando Gehm Moraes:
Current Mask Generation: an Analog Circuit to Thwart DPA Attacks. 317-330 - Cristiano Lazzari, Lorena Anghel, Ricardo Reis:
A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming. 331-344
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