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ORCID27th DDECS 2024: Kielce, Poland
- 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, DDECS 2024, Kielce, Poland, April 3-5, 2024. IEEE 2024, ISBN 979-8-3503-5934-3
- Jan Klhufek, Miroslav Safar, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina:
Exploring Quantization and Mapping Synergy in Hardware-Aware Deep Neural Network Accelerators. 1-6 - Roshwin Sengupta, Ilia Polian, John P. Hayes:
Performance and Error Tolerance of Stochastic Computing-Based Digital Filter Design. 7-12 - V. Turco, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda:
Early Detection of Permanent Faults in DNNs Through the Application of Tensor-Related Metrics. 13-18 - Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio:
SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. 19-24 - Clemens Scharwitzl, Andreas Steininger:
An Autonomous Clock Frequency Supervision Circuit. 25-30 - Giorgio Cora, Corrado De Sio, Daniele Rizzieri, Sarah Azimi, Luca Sterpone:
A New Reliability Analysis of RISC-V Soft Processor for Safety-Critical Systems. 31-36 - Marika Grochowska, Witold A. Pleskacz:
The Impact of Well-Edge Proximity Effect on PMOS Threshold Voltage in Various Submicron CMOS Technologies. 37-40 - Jie Pan, Fanyang Li, Yidong Yuan, Tianting Zhao, Hongwei Shen, Liguo Wen, Yi Hu, Jiazhen Jin, Shuwen Wu:
A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement. 41-46 - Michaela Brunner, Hye-Hyun Lee, Alexander Hepp, Johanna Baehr, Georg Sigl:
Hardware Honeypot: Setting Sequential Reverse Engineering on a Wrong Track. 47-52 - Michael Mildner, Michaela Brunner, Michael Gruber, Johanna Baehr, Georg Sigl:
Fault-Simulation-Based Flip-Flop Classification for Reverse Engineering. 53-56 - Mahnaz Namazi Rizi, Nusa Zidaric, Lejla Batina, Nele Mentens:
Optimised AES with RISC-V Vector Extensions. 57-60 - Parisa Amiri Eliasi, Silvia Mella, Léo Weissbart, Lejla Batina, Stjepan Picek:
Xoodyak Under SCA Siege. 61-66 - Mounika Vaddeboina, Endri Kaja, Alper Yilmazer, Uttal Ghosh, Wolfgang Ecker:
PaGoRi:A Scalable Parallel Golomb-Rice Decoder. 67-72 - Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler:
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences. 73-78 - Tobias Hahn, Daniel Schüll, Stefan Wildermann, Jürgen Teich:
ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. 79-85 - Jan Schmidt
, Petr Fiser, Miroslav Skrbek:
A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks. 86-91 - Florian Huemer:
QDI Binary Comparator Networks and their Application in Combinational Logic. 92-97 - Ernesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Michael Glaß:
An Efficient Approach for STLs Development of Automotive SoCs Using Colored Petri Nets. 98-103 - Raghunandana K. K, Yogesh Prasad K. R, Matteo Sonza Reorda, Virendra Singh:
TCC: GPGPU Architecture for Instruction Decoder and Control Flow Error Detection. 104-109 - Rosario Milazzo, Vincenzo De Marco, Corrado De Sio, Sophie M. Fosson, Lia Morra, Luca Sterpone:
On the Fault Tolerance of Self-Supervised Training in Convolutional Neural Networks. 110-115 - Fabian Luis Vargas:
On-Chip Cross-Layer Infrastructure to Leverage System Reliability for Aero-Space Applications: Embedded Tutorial. 116-117 - Sami El Amraoui, Régis Leveugle, Paolo Maistri:
Choose your Path: Control of Ring Oscillators EMFI Susceptibility through FPGA P&R Constraints. 118-123 - Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda, Serag E.-D. Habib:
Evaluating the Reliability of Integer Multipliers With Respect to Permanent Faults. 124-129 - Jan Schmidt, Petr Fiser, Miroslav Skrbek:
Adaptive Input Normalization for Quantized Neural Networks. 130-135 - Ján Mach, Lukás Kohútka, Pavel Cicák:
Interface Protection Against Transient Faults. 136-141 - Sakari Lahti, Tuomas Aaltonen, Elizaveta Rastorgueva-Foi, Jukka Talvitie, Bo Tan, Timo D. Hämäläinen:
An Efficient High-level Synthesis Implementation of the MUSIC DoA Algorithm for FPGA. 142-147 - Seyedbehnam Beladi, Linus Maurer, Jonas Stricker, Georg Pelz:
A ML-Based Approach for Finding the Product Definition Space of Microelectronic Power Switches. 148-151 - Adam Hudec, Róbert Ondica, Richard Ravasz, Viera Stopjaková:
Constant Voltage Maximum Power Point Tracking Method for Fully Integrated Solar-Powered Energy Harvester. 152-155
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