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ORCIDIntegration, Volume 59
Volume 59, September 2017
- Mahya Sam Daliri
, Reza Faghih Mirzaee, Keivan Navi, Nader Bagherzadeh:
High-performance ternary operators for scrambling. 1-9 - Navid Khoshavi, Rizwan A. Ashraf, Ronald F. DeMara, Saman Kiamehr, Fabian Oboril, Mehdi Baradaran Tahoori:
Contemporary CMOS aging mitigation techniques: Survey, taxonomy, and methods. 10-22 - Qin Wang, Zhenyang Chen, Jianfei Jiang, Zheng Guo, Zhigang Mao:
Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. 23-30 - Zbigniew Hajduk:
Simple method of asynchronous circuits implementation in commercial FPGAs. 31-41 - Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler:
Synthesis of optical circuits using binary decision diagrams. 42-51 - Huyen Thi Pham, Sabooh Ajaz, Hanho Lee:
High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. 52-63 - Siraj Fulum Mossa, Syed Rafay Hasan, Omar S. Elkeelany:
Hardware trojans in 3-D ICs due to NBTI effects and countermeasure. 64-74 - Javier Lemus-López, Alejandro Díaz-Sánchez, José Miguel Rocha-Pérez, Carlos Muñiz-Montero, Jaime Ramírez-Angulo:
High gain amplifier with feedforward compensation based on quasi-floating gate transistors. 75-80 - Simone Acciarito, Gian Carlo Cardarilli, Alessandro Cristini, Luca Di Nunzio, Rocco Fazzolari, Gaurav Mani Khanal, Marco Re, Gianluca Susi:
Hardware design of LIF with Latency neuron model with memristive STDP synapses. 81-89 - Anu Tonk, Neelofer Afzal:
On advance towards sub-sampling technique in phase locked loops - A review. 90-97 - Bernhard Schmidt, Daniel Ziener, Jürgen Teich, Christian Zöllner:
Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. 98-108 - M. Mohamed Asan Basiri, Sandeep K. Shukla:
Flexible VLSI architectures for Galois field multipliers. 109-124 - Subhamita Mukherjee, Indrajit Pan, Tuhina Samanta:
Pareto optimization technique in actuation control for error minimization and reliability analysis in an operational pin-constrained digital microfluidic biochip. 125-134 - Ons Lahiouel, Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar:
Exploiting bounds optimization for the semi-formal verification of analog circuits. 135-147 - Weijing Shi, Mohamed Baker Alawieh, Xin Li, Huafeng Yu:
Algorithm and hardware implementation for visual perception system in autonomous vehicle: A survey. 148-156 - Qi Xu, Song Chen:
Fast thermal analysis for fixed-outline 3D floorplanning. 157-167 - Bibhas Ghoshal, Chittaranjan Mandal, Indranil Sengupta:
Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs. 168-178 - Riccardo Bernardini, Roberto Rinaldo:
A very stable diode-based physically unclonable constant. 179-189 - Y. Zhang, Rostislav (Reuven) Dobkin, Aharon Unikovski, Danniel Nahmanny, Goel Samuel, Michael Moyal, Ran Ginosar:
A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication. 190-197 - Szu Huat Goh, Y. H. Chan, Zhao Lin, Jeffrey Lam:
Concurrent built-in self-testing under the constraint of shared test resources and its test time reduction. 198-205 - Wei Jin, Guanghui He, Weifeng He, Zhigang Mao:
A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. 206-217 - Maryam Dehbashian, Mohammad Maymandi-Nejad:
Co-AGSA: An efficient self-adaptive approach for constrained optimization of analog IC based on the shrinking circles technique. 218-232 - Gunti Nagendra Babu, Karthikeyan Lingasubramanian:
Effective usage of redundancy to aid neutralization of hardware Trojans in Integrated Circuits. 233-242 - Carlos Aristoteles De la Cruz-Blas, G. Thomas-Erviti, José María Algueta-Miguel, Antonio J. López-Martín:
CMOS analogue current-mode multiplier/divider circuit operating in triode-saturation with bulk-driven techniques. 243-246 - Zongwei Li, Xingyin Xiong, Xiong Liu, Kedu Han, Ning Cong, Changchun Yang:
Design of a high precision digital interface circuit for capacitive MEMS accelerometers with floating point ADC. 247-254
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