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ORCIDVLSI-SoC 2003: Darmstadt, Germany
- Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak
, Vincent John Mooney III, Hans Eveking:
VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. IFIP 200, Springer 2006, ISBN 978-0-387-33402-8 - Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Effect of Power Optimizations on Soft Error Rate. 1-20 - João M. S. Silva, Luís Miguel Silveira:
Dynamic Models for Substrate Coupling in Mixed-Mode Systems. 21-37 - Thomas Hollstein, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner:
Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs. 39-54 - Axel G. Braun, Djones Lettnin, Joachim Gerlach, Wolfgang Rosenstiel:
Automated Conversion of SystemC Fixed-Point Data Types. 55-72 - Nicole Drechsler, Rolf Drechsler:
Exploration of Sequential Depth by Evolutionary Algorithms. 73-83 - Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Siriani:
Validation of Asynchronous Circuit Specifications Using IF/CADP. 85-100 - José Augusto Miranda Nacif, Claudionor Nunes Coelho, Harry Foster, Flávio Miana de Paula, Edjard Mota, Márcia Roberta Falcão Mota, Antônio Otávio Fernandes:
On-Chip Property Verification Using Assertion Processors. 101-117 - Jürgen Becker, Michael Hübner, Michael Ullmann:
Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems. 119-132 - Giuseppe Bonfini, Andrea S. Brogna, Roberto Saletti, Cristian Garbossa, Luca Colombini, Maurizio Bacci, Stefania Chicca, Franco Bigongiari:
A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications. 133-147 - Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans. 149-164 - Alexandre M. Amory, Leandro A. Oliveira, Fernando Gehm Moraes:
Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures. 165-179 - Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources Using Dual Sequences. 181-196 - Cristiano Lazzari, Cristiano Viana Domingues, José Luís Güntzel, Ricardo Reis:
A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits. 197-211 - Antonio Carlos Schneider Beck, Luigi Carro:
Low Power Java Processor for Embedded Applications. 213-228 - Stephan Henzler, Philip Teichmann, Markus Koban, Jörg Berthold, Georg Georgakos, Doris Schmitt-Landsiedel:
Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes. 229-245 - Casper Lageweg, Sorin Cotofana, Stamatis Vassiliadis:
Evaluation Methodology for Single Electron Encoded Threshold Logic Gates. 247-262 - Jürgen Becker, Alexander Thomas, Maik Scheer:
Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath. 263-279 - Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi:
Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths. 281-297 - Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Stuck-At-Fault Testability of SPP Three-Level Logic Forms. 299-313
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