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ORCIDDATE 2009: Nice, France
- Luca Benini, Giovanni De Micheli, Bashir M. Al-Hashimi, Wolfgang Müller:
Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009. IEEE 2009, ISBN 978-1-4244-3781-8 - Mike Muller:
Has anything changed in electronic design since 1983? 1 - Joseph Sifakis:
Embedded systems design - Scientific challenges and work directions. 2 - Huaxi Gu, Jiang Xu, Wei Zhang:
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip. 3-8 - Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli:
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. 9-14 - Chen-Ling Chou, Radu Marculescu:
User-centric design space exploration for heterogeneous Network-on-Chip platforms. 15-20 - David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David T. Blaauw:
A highly resilient routing algorithm for fault-tolerant NoCs. 21-26 - Sean Whitty, Henning Sahlbach, Rolf Ernst, Wolfram Putzke-Röming:
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture. 27-32 - Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan
, Tughrul Arslan:
An ILP formulation for task mapping and scheduling on multi-core architectures. 33-38 - Wenxue Gao, Andreas Kugel, Reinhard Männer, Norbert Abel, Nick Meier, Udo Kebschull:
DPR in high energy physics. 39-44 - Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn:
A flexible layered architecture for accurate digital baseband algorithm development and verification. 45-50 - Lin Huang, Feng Yuan, Qiang Xu:
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms. 51-56 - Soheil Samii, Anton Cervin, Petru Eles, Zebo Peng:
Integrated scheduling and synthesis of control applications on distributed embedded systems. 57-62 - Chengmo Yang, Alex Orailoglu:
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude. 63-68 - Hoeseok Yang, Soonhoi Ha:
Pipelined data parallel task mapping/scheduling technique for MPSoC. 69-74 - Kai-Chiang Wu, Diana Marculescu:
Joint logic restructuring and pin reordering against NBTI-induced performance degradation. 75-80 - Omer Khan, Sandip Kundu:
A self-adaptive system architecture to address transistor aging. 81-86 - Mihir R. Choudhury, Kartik Mohanram:
Masking timing errors on speed-paths in logic circuits. 87-92 - Michael Mendler, Reinhard von Hanxleden, Claus Traulsen:
WCRT algebra and interfaces for esterel-style synchronous processing. 93-98 - Nikolay Stoimenov, Simon Perathoner, Lothar Thiele:
Reliable mode changes in real-time systems with fixed priority or EDF scheduling. 99-104 - Victor Pollex, Steffen Kollmann, Karsten Albers, Frank Slomka:
Improved worst-case response-time calculations by upper-bound conditions. 105-110 - William Plishker, Nimish Sane, Shuvra S. Bhattacharyya:
A generalized scheduling approach for dynamic dataflow applications. 111-116 - Daniel Gomez-Prado, Qian Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon:
Optimizing data flow graphs to minimize hardware implementation. 117-122 - Roopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic:
Multi-clock Soc design using protocol conversion. 123-128 - Karin Avnit, Arcot Sowmya:
A formal approach to design space exploration of protocol converters. 129-134 - Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jürgen Teich:
Model-based synthesis and optimization of static multi-rate image processing algorithms. 135-140 - Marco Casale-Rossi, Giovanni De Micheli:
Panel session - Consolidation, a modern "Moor of Venice" tale. 141 - Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski:
Variation resilient adaptive controller for subthreshold circuits. 142-147 - David R. Bild, Gregory E. Bok, Robert P. Dick:
Minimization of NBTI performance degradation using internal node control. 148-153 - Ashoka Visweswara Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii:
Physically clustered forward body biasing for variability compensation in nanometer CMOS design. 154-159 - Meeta Sharma Gupta, Vijay Janapa Reddi, Glenn H. Holloway, Gu-Yeon Wei, David M. Brooks:
An event-guided approach to reducing voltage noise in processors. 160-165 - Panagiotis Afratis, Constantinos Galanakis, Euripides Sotiriades, Georgios-Grigorios Mplemenos, Grigorios Chrysos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos:
Design and implementation of a database filter for BLAST acceleration. 166-171 - Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris:
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs. 172-177 - Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Priority-based packet communication on a bus-shaped structure for FPGA-systems. 178-183 - Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres:
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor. 184-189 - Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe:
Functional qualification of TLM verification. 190-195 - Alfred Kölbl, Reily Jacoby, Himanshu Jain, Carl Pixley:
Solver technology for system-level to RTL equivalence checking. 196-201 - Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad:
A high-level debug environment for communication-centric debug. 202-207 - Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan:
Cache aware compression for processor debug support. 208-213 - Gerhard Grießnig, Roland Mader, Christian Steger, Reinhold Weiss:
Fault insertion testing of a novel CPLD-based fail-safe system. 214-219 - Li Jiang, Lin Huang, Qiang Xu:
Test architecture design and optimization for three-dimensional SoCs. 220-225 - Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, Philippe Soulard, Jean-Philippe Diguet:
A co-design approach for embedded system modeling and code generation with UML and MARTE. 226-231 - Kecheng Hao, Fei Xie:
Componentizing hardware/software interface design. 232-237 - Tim Schattkowsky, Tao Xie, Wolfgang Müller:
A UML frontend for IP-XACT-based IP management. 238-243 - Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo D. Hämäläinen, Marko Hännikäinen:
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA. 244-249 - Andreas Hansson, Mahesh Subburaman, Kees Goossens:
Aelite: A flit-synchronous Network on Chip with composable and predictable services. 250-255 - Mohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel:
Configurable links for runtime adaptive on-chip communication. 256-261 - Igor Loi, Federico Angiolini, Luca Benini:
Synthesis of low-overhead configurable source routing tables for network interfaces. 262-267 - Abelardo Jara-Berrocal, Ann Gordon-Ross:
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems. 268-273 - Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser:
Analog layout synthesis - Recent advances in topological approaches. 274-279 - Baohua Wang, Pinaki Mazumder:
An accurate interconnect thermal model using equivalent transmission line circuit. 280-283 - Tobias Kirchner, Nico Bannow, Christoph Grimm:
Analogue mixed signal simulation using spice and SystemC. 284-287 - Amirali Shayan Arani, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen:
Reliability aware through silicon via planning for 3D stacked ICs. 288-291 - Kelageri Nagaraj, Sandip Kundu:
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. 292-295 - Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan:
Analysis and optimization of NBTI induced clock skew in gated clock trees. 296-299 - Adam Flynn, Ann Gordon-Ross, Alan D. George:
Bitstream relocation with local clock domains for partially reconfigurable FPGAs. 300-303 - He Peng, Chung-Kuan Cheng:
Parallel transistor level full-chip circuit simulation. 304-307 - Fu-Wei Chen, Yi-Yu Liu:
Performance-driven dual-rail insertion for chip-level pre-fabricated design. 308-311 - Martin Trautmann, Stylianos Mamagkakis, Bruno Bougard, Jeroen Declerck, Erik Umans, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor:
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning. 312-315 - H. W. M. van Moll, Henk Corporaal, Víctor Reyes, Marleen Boonen:
Fast and accurate protocol specific bus modeling using TLM 2.0. 316-319 - Michael Glaß, Martin Lukasiewycz, Christian Haubelt, Jürgen Teich:
Incorporating graceful degradation into embedded system design. 320-323 - Chun-Chi Lin, Chun-Yao Wang:
Rewiring using IRredundancy Removal and Addition. 324-327 - Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang:
Gate replacement techniques for simultaneous leakage and aging optimization. 328-333 - Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino:
Enabling concurrent clock and power gating in an industrial design flow. 334-339 - Amin Khajeh, Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir:
TRAM: A tool for Temperature and Reliability Aware Memory Design. 340-345 - Jean Casteres, Tovo Ramaherirariny:
Aircraft integration real-time simulator modeling with AADL for architecture tradeoffs. 346-351 - Matteo Sonza Reorda, Massimo Violante, Cristina Meinhardt, Ricardo Reis:
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips. 352-357 - Hassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozbeh Jafari:
Communication minimization for in-network processing in body sensor networks: A buffer assignment technique. 358-363 - Luca Larcher, Riccardo Brama, Marcello Ganzerli, Jacopo Iannacci, Marco Bedani, Antonio Gnudi:
A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standard. 364-368 - José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino:
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. 369-373 - Loic Le Toumelin:
PANEL SESSION - Is the second wave of HLS the one industry will surf on? 374 - Sherief Reda, Sani R. Nassif:
Analyzing the impact of process variations on parametric measurements: Novel models and applications. 375-380 - Aswin Sreedhar, Sandip Kundu:
On linewidth-based yield analysis for nanometer lithography. 381-386 - Vikas Chandra, Robert C. Aitken:
Impact of voltage scaling on nanoscale SRAM reliability. 387-392 - Po-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo:
A file-system-aware FTL design for flash-memory storage systems. 393-398 - Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis:
FSAF: File system aware flash translation layer for NAND Flash Memories. 399-404 - Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei-Wei Kuo:
A set-based mapping strategy for flash-memory reliability enhancement. 405-410 - Jason Cong, Karthik Gururaj:
Energy efficient multiprocessor task scheduling under input-dependent variation. 411-416 - Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung:
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scaling. 417-422 - Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi:
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. 423-428 - P. Parrish:
PANEL SESSION - Open source hardware IP, are you serious? 429 - Lorena Anghel:
HOT TOPIC - Concurrent SoC development and end-to-end planning. 430 - Shinobu Fujita:
Nano-electronics challenge chip designers meet real nano-electronics in 2010s? 431-432 - Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu:
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues. 433-435 - Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei:
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors. 436-441 - Chen Dong, Scott Chilstedt, Deming Chen:
Reconfigurable circuit design with nanomaterials. 442-447 - Chunxiao Li, Anand Raghunathan, Niraj K. Jha:
An architecture for secure software defined radio. 448-453 - Xu Guo, Patrick Schaumont:
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storage. 454-459 - Foad Dabiri, Miodrag Potkonjak:
Hardware aging-based software metering. 460-465 - Young-Pyo Joo, Sungchan Kim, Soonhoi Ha:
On-chip communication architecture exploration for processor-pool-based MPSoC. 466-471 - Martin Lukasiewycz, Martin Streubühr, Michael Glaß, Christian Haubelt, Jürgen Teich:
Combined system synthesis and communication architecture exploration for MPSoCs. 472-477 - Douglas Densmore, Alena Simalatsar, Abhijit Davare, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
UMTS MPSoC design evaluation using a system level design framework. 478-483 - Mikael Väyrynen, Virendra Singh, Erik Larsson:
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips. 484-489 - Abhisek Pan, Omer Khan, Sandip Kundu:
Improving yield and reliability of chip multiprocessors. 490-495 - Guihai Yan, Yinhe Han, Xiaowei Li:
A unified online Fault Detection scheme via checking of Stability Violation. 496-501 - Régis Leveugle, A. Calvez, Paolo Maistri, Pierre Vanhauwaert:
Statistical fault injection: Quantified error and confidence. 502-506 - Hyun-jin Cho, Dongkun Shin, Young Ik Eom:
KAST: K-associative sector translation for NAND flash memory in real-time systems. 507-512 - Alexander Viehl, Michael Pressler, Oliver Bringmann, Wolfgang Rosenstiel:
White box performance analysis considering static non-preemptive software scheduling. 513-518 - Frank König, Dave Boers, Frank Slomka, Ulrich Margull, Michael Niemetz, Gerhard Wirrer:
Application specific performance indicators for quantitative evaluation of the timing behavior for embedded real-time systems. 519-523 - Mircea Negrean, Simon Schliecker, Rolf Ernst:
Response-time analysis of arbitrarily activated tasks in multiprocessor systems with shared resources. 524-529 - Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals:
Light NUCA: A proposal for bridging the inter-cache latency gap. 530-535 - Sotiria Fytraki, Dionisios N. Pnevmatikatos:
ReSim, a trace-driven, reconfigurable ILP processor simulator. 536-541 - Giovanni Ansaloni, Paolo Bonzini, Laura Pozzi:
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration. 542-547 - Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels:
Algorithms for the automatic extension of an instruction-set. 548-553 - Bastian Ristau, Torsten Limberg, Oliver Arnold, Gerhard P. Fettweis:
Dimensioning heterogeneous MPSoCs via parallelism analysis. 554-557 - Leandro Fiorin, Gianluca Palermo, Cristina Silvano:
MPSoCs run-time monitoring through Networks-on-Chip. 558-561 - Daniele Ludovici, Francisco Gilabert Villamón, Simone Medardoni, Crispín Gómez Requena, María Engracia Gómez, Pedro López, Georgi Nedeltchev Gaydadjiev, Davide Bertozzi:
Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints. 562-565 - Mehdi Modarressi, Hamid Sarbazi-Azad, Mohammad Arjomand:
A hybrid packet-circuit switched on-chip network based on SDM. 566-569 - Lifeng Su, Stephan Courcambeck, Pierre Guillemin, Christian Schwarz, Renaud Pacalet:
SecBus: Operating System controlled hierarchical page-based memory bus protection. 570-573 - Jonas Diemer, Rolf Ernst:
A link arbitration scheme for quality of service in a latency-optimized network-on-chip. 574-577 - Zhonghai Lu, Mikael Millberg, Axel Jantsch, Alistair C. Bruce, Pieter van der Wolf, Tomas Henriksson:
Flow regulation for on-chip communication. 578-581 - Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Customizing IP cores for system-on-chip designs using extensive external don't-cares. 582-585 - Amin El Mrabti, Frédéric Pétrot, Aimen Bouchhima:
Extending IP-XACT to support an MDE based approach for SoC design. 586-589 - Christian Genz, Rolf Drechsler:
Overcoming limitations of the SystemC data introspection. 590-593 - Hao Xu, Ranga Vemuri, Wen-Ben Jone:
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. 594-597 - Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete:
A power-efficient migration mechanism for D-NUCA caches. 598-601 - Yervant Zorian:
Panel Session - Vertical integration versus disaggregation. 602