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ORCIDMatthias Sauer 0002
Person information
- affiliation: Advantest Europe GmbH
- affiliation (PhD 2013): University of Freiburg, Computer Architecture, Germany
Other persons with the same name
- Matthias Sauer 0001 — Apple, Inc., Cupertino, CA, USA (and 1 more)
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2020 – today
- 2024
[i4]Denis Schwachhofer, Peter Domanski, Steffen Becker, Stefan Wagner, Matthias Sauer, Dirk Pflüger, Ilia Polian:
Large Language Models to Generate System-Level Test Programs Targeting Non-functional Properties. CoRR abs/2403.10086 (2024)- 2023
- [c62]Jens Anders, Pablo Andreu, Bernd Becker, Steffen Becker, Riccardo Cantoro, Nikolaos Ioannis Deligiannis, Nourhan Elhamawy, Tobias Faller, Carles Hernández, Nele Mentens
, Mahnaz Namazi Rizi, Ilia Polian, Abolfazl Sajadi, Matthias Sauer, Denis Schwachhofer, Matteo Sonza Reorda, Todor Stefanov, Ilya Tuzov, Stefan Wagner, Nusa Zidaric:
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors. ETS 2023: 1-10 - [c61]Denis Schwachhofer, Maik Betka, Steffen Becker, Stefan Wagner, Matthias Sauer, Ilia Polian:
Automating Greybox System-Level Test Generation. ETS 2023: 1-4 - 2022
- [c60]Hussam Amrouch, Jens Anders, Steffen Becker, Maik Betka, Gerd Bleher, Peter Domanski, Nourhan Elhamawy, Thomas Ertl, Athanasios Gatzastras, Paul R. Genssler, Sebastian Hasler, Martin Heinrich, André van Hoorn, Hanieh Jafarzadeh, Ingmar Kallfass, Florian Klemme, Steffen Koch, Ralf Küsters, Andrés Lalama, Raphaël Latty, Yiwen Liao, Natalia Lylina, Zahra Paria Najafi-Haghi, Dirk Pflüger, Ilia Polian, Jochen Rivoir, Matthias Sauer, Denis Schwachhofer, Steffen Templin, Christian Volmer, Stefan Wagner, Daniel Weiskopf, Hans-Joachim Wunderlich, Bin Yang, Martin Zimmermann:
Intelligent Methods for Test and Reliability. DATE 2022: 969-974 - [c59]Hussam Amrouch, Krishnendu Chakrabarty, Dirk Pflüger, Ilia Polian, Matthias Sauer, Matteo Sonza Reorda:
Machine Learning for Test, Diagnosis, Post-Silicon Validation and Yield Optimization. ETS 2022: 1-6 - 2021
- [c58]Jaume Abella, Sergi Alcaide, Jens Anders, Francisco Bas, Steffen Becker, Elke De Mulder, Nourhan Elhamawy, Frank K. Gürkaynak, Helena Handschuh, Carles Hernández, Michael Hutter, Leonidas Kosmidis, Ilia Polian, Matthias Sauer, Stefan Wagner, Francesco Regazzoni:
Security, Reliability and Test Aspects of the RISC-V Ecosystem. ETS 2021: 1-10 - [c57]Davide Appello, H. H. Chen, Matthias Sauer, Ilia Polian, Paolo Bernardi, Matteo Sonza Reorda:
System-Level Test: State of the Art and Challenges. IOLTS 2021: 1-7 - [c56]Nikolaos Ioannis Deligiannis, Riccardo Cantoro, Matthias Sauer, Bernd Becker, Matteo Sonza Reorda:
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core. VTS 2021: 1-7 - [i3]Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. CoRR abs/2103.06656 (2021) - 2020
- [c55]Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner:
Exploring the Mysteries of System-Level Test. ATS 2020: 1-6
2010 – 2019
- 2019
- [c54]Pascal Raiola, Benjamin Thiemann, Jan Burchard, Ahmed Atteya, Natalia Lylina, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer:
On Secure Data Flow in Reconfigurable Scan Networks. DATE 2019: 1016-1021 - [c53]Benjamin Thiemann, Linus Feiten, Pascal Raiola, Bernd Becker, Matthias Sauer:
On Integrating Lightweight Encryption in Reconfigurable Scan Networks. ETS 2019: 1-6 - [c52]Natalia Lylina, Ahmed Atteya, Pascal Raiola, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich:
Security Compliance Analysis of Reconfigurable Scan Networks. ITC 2019: 1-9 - 2018
- [c51]Ahmed Atteya, Michael A. Kochte, Matthias Sauer, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich:
Online prevention of security violations in reconfigurable scan networks. ETS 2018: 1-6 - [c50]Johanna Sepúlveda, Damian Aboul-Hassan, Georg Sigl, Bernd Becker, Matthias Sauer:
Towards the formal verification of security properties of a Network-on-Chip router. ETS 2018: 1-6 - [c49]Pascal Raiola, Michael A. Kochte, Ahmed Atteya, Laura Rodríguez Gómez, Hans-Joachim Wunderlich, Bernd Becker, Matthias Sauer:
Detecting and Resolving Security Violations in Reconfigurable Scan Networks. IOLTS 2018: 91-96 - [c48]Felix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker, Matthias Sauer:
Efficient generation of parametric test conditions for AMS chips with an interval constraint solver. VTS 2018: 1-6 - 2017
- [c47]Matthias Sauer, Pascal Raiola, Linus Feiten, Bernd Becker, Ulrich Rührmair, Ilia Polian:
Sensitized path PUF: A lightweight embedded physical unclonable function. DATE 2017: 680-685 - [c46]Michael A. Kochte, Matthias Sauer, Laura Rodríguez Gómez, Pascal Raiola, Bernd Becker, Hans-Joachim Wunderlich:
Specification and verification of security in reconfigurable scan networks. ETS 2017: 1-6 - 2016
- [j9]Matthias Sauer, Bernd Becker, Ilia Polian:
PHAETON: A SAT-Based Framework for Timing-Aware Path Sensitization. IEEE Trans. Computers 65(6): 1869-1881 (2016) - [j8]Linus Feiten, Jonathan Oesterle, Tobias Martin, Matthias Sauer, Bernd Becker:
Systemic Frequency Biases in Ring Oscillator PUFs on FPGAs. IEEE Trans. Multi Scale Comput. Syst. 2(3): 174-185 (2016) - [j7]Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
A Flexible Framework for the Automatic Generation of SBST Programs. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3055-3066 (2016) - [c45]Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Mixed 01X-RSL-Encoding for fast and accurate ATPG with unknowns. ASP-DAC 2016: 749-754 - [c44]Matthias Sauer, Jie Jiang, Sven Reimer, Kohei Miyase, Xiaoqing Wen, Bernd Becker, Ilia Polian:
On Optimal Power-Aware Path Sensitization. ATS 2016: 179-184 - [c43]Michael A. Kochte, Rafal Baranowski, Matthias Sauer, Bernd Becker, Hans-Joachim Wunderlich:
Formal verification of secure reconfigurable scan network infrastructure. ETS 2016: 1-6 - [c42]Mathias Soeken, Pascal Raiola, Baruch Sterin, Bernd Becker, Giovanni De Micheli, Matthias Sauer:
SAT-Based Combinational and Sequential Dependency Computation. Haifa Verification Conference 2016: 1-17 - [c41]Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
Effective generation and evaluation of diagnostic SBST programs. VTS 2016: 1-6 - [i2]Linus Feiten, Matthias Sauer, Bernd Becker:
On Metrics to Quantify the Inter-Device Uniqueness of PUFs. IACR Cryptol. ePrint Arch. 2016: 320 (2016) - [i1]Linus Feiten, Matthias Sauer:
Extracting the RC4 secret key of the Open Smart Grid Protocol. IACR Cryptol. ePrint Arch. 2016: 455 (2016) - 2015
- [j6]Linus Feiten, Matthias Sauer, Tobias Schubert, Victor Tomashevich, Ilia Polian, Bernd Becker:
Formal Vulnerability Analysis of Security Components. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(8): 1358-1369 (2015) - [j5]Dominik Erb, Michael A. Kochte, Sven Reimer, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Accurate QBF-Based Test Pattern Generation in Presence of Unknown Values. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(12): 2025-2038 (2015) - [c40]Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker:
On the automatic generation of SBST test programs for in-field test. DATE 2015: 1186-1191 - [c39]Karina Gitina, Ralf Wimmer, Sven Reimer, Matthias Sauer, Christoph Scholl, Bernd Becker:
Solving DQBF through quantifier elimination. DATE 2015: 1617-1622 - [c38]Linus Feiten, Tobias Martin, Matthias Sauer, Bernd Becker:
Improving RO-PUF quality on FPGAs by incorporating design-dependent frequency biases. ETS 2015: 1-6 - [c37]Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Identification of high power consuming areas with gate type and logic level information. ETS 2015: 1-6 - [c36]Bernd Becker, Matthias Sauer, Christoph Scholl, Ralf Wimmer:
Modeling Unknown Values in Test and Verification. SyDe Summer School 2015: 122-150 - [c35]Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. VTS 2015: 1-6 - [c34]Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Improving diagnosis resolution of a fault detection test set. VTS 2015: 1-6 - 2014
- [b1]Matthias Sauer:
Testing time - time to test?: using formal methods for the timing analysis of digital circuits. University of Freiburg, Freiburg im Breisgau, Germany, Der Andere Verlag 2014, ISBN 978-3-86247-451-6, pp. 1-184 - [j4]Sven Reimer, Matthias Sauer, Paolo Marin, Bernd Becker:
QBF with Soft Variables. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 70 (2014) - [j3]Dominik Erb, Michael A. Kochte, Matthias Sauer, Stefan Hillebrecht, Tobias Schubert, Hans-Joachim Wunderlich, Bernd Becker:
Exact Logic and Fault Simulation in Presence of Unknowns. ACM Trans. Design Autom. Electr. Syst. 19(3): 28:1-28:17 (2014) - [c33]Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. ATS 2014: 131-136 - [c32]Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker:
Incremental Encoding and Solving of Cardinality Constraints. ATVA 2014: 297-313 - [c31]Matthias Sauer, Stefan Kupferschmid:
A Formal Approach to the Traveling Professor Problem. Aspekte der Technischen Informatik 2014: 81-88 - [c30]Dominik Erb, Karsten Scheibler, Matthias Sauer, Bernd Becker:
Efficient SMT-based ATPG for interconnect open defects. DATE 2014: 1-6 - [c29]Sven Reimer, Matthias Sauer, Tobias Schubert, Bernd Becker:
Using MaxBMC for Pareto-optimal circuit initialization. DATE 2014: 1-6 - [c28]Andreas Riefert, Lyl M. Ciganda, Matthias Sauer, Paolo Bernardi, Matteo Sonza Reorda, Bernd Becker:
An effective approach to automatic functional processor test generation for small-delay faults. DATE 2014: 1-6 - [c27]Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer:
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS 2014: 1-10 - [c26]Matthias Sauer, Ilia Polian, Michael E. Imhof, Abdullah Mumtaz, Eric Schneider, Alexander Czutro, Hans-Joachim Wunderlich, Bernd Becker:
Variation-aware deterministic ATPG. ETS 2014: 1-6 - [c25]Dominik Erb, Karsten Scheibler, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Test pattern generation in presence of unknown values based on restricted symbolic logic. ITC 2014: 1-10 - [c24]Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker:
Efficient SAT-Based Circuit Initialization for Larger Designs. VLSID 2014: 62-67 - 2013
- [j2]Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker:
SAT-Based Analysis of Sensitizable Paths. IEEE Des. Test 30(4): 81-88 (2013) - [j1]Linus Feiten, Andreas Spilla, Matthias Sauer, Tobias Schubert, Bernd Becker:
Implementation and Analysis of Ring Oscillator PUFs on 60 nm Altera Cyclone FPGAs. Inf. Secur. J. A Glob. Perspect. 22(5-6): 265-273 (2013) - [c23]Matthias Sauer, Sven Reimer, Ilia Polian, Tobias Schubert, Bernd Becker:
Provably optimal test cube generation using quantified boolean formula solving. ASP-DAC 2013: 533-539 - [c22]Kohei Miyase, Matthias Sauer, Bernd Becker, Xiaoqing Wen, Seiji Kajihara:
Search Space Reduction for Low-Power Test Generation. Asian Test Symposium 2013: 171-176 - [c21]Dominik Erb, Michael A. Kochte, Matthias Sauer, Hans-Joachim Wunderlich, Bernd Becker:
Accurate Multi-cycle ATPG in Presence of X-Values. Asian Test Symposium 2013: 245-250 - [c20]Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Matthias Sauer, Bernd Becker, Subhasish Mitra:
Detection of early-life failures in high-K metal-gate transistors and ultra low-K inter-metal dielectrics. CICC 2013: 1-4 - [c19]Matthias Sauer, Sven Reimer, Tobias Schubert, Ilia Polian, Bernd Becker:
Efficient SAT-based dynamic compaction and relaxation for longest sensitizable paths. DATE 2013: 448-453 - [c18]Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker:
Equivalence checking of partial designs using dependency quantified Boolean formulae. ICCD 2013: 396-403 - [c17]Matthias Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, Kyung Tae Do, Jung Yun Choi, Kee Sup Kim, Subhasish Mitra, Bernd Becker:
Early-life-failure detection using SAT-based ATPG. ITC 2013: 1-10 - [c16]Benjamin Andres, Matthias Sauer, Martin Gebser, Tobias Schubert, Bernd Becker, Torsten Schaub:
Accurate Computation of Sensitizable Paths Using Answer Set Programming. LPNMR 2013: 92-101 - [c15]Karina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker:
Equivalence Checking for Partial Implementations Revisited. MBMV 2013: 61-70 - [c14]Andreas Riefert, Jörg Müller, Matthias Sauer, Wolfram Burgard, Bernd Becker:
Identification of critical variables using an FPGA-based fault injection framework. VTS 2013: 1-6 - 2012
- [c13]Alexander Czutro, Michael E. Imhof, J. Jiang, Abdullah Mumtaz, Matthias Sauer, Bernd Becker, Ilia Polian, Hans-Joachim Wunderlich:
Variation-Aware Fault Grading. Asian Test Symposium 2012: 344-349 - [c12]Jie Jiang, Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian:
On the optimality of K longest path generation algorithm under memory constraints. DATE 2012: 418-423 - [c11]Linus Feiten, Matthias Sauer, Tobias Schubert, Alexander Czutro, Eberhard Böhl, Ilia Polian, Bernd Becker:
#SAT-based vulnerability analysis of security components - A case study. DFT 2012: 49-54 - [c10]Alexander Czutro, Matthias Sauer, Ilia Polian, Bernd Becker:
Multi-conditional SAT-ATPG for power-droop testing. ETS 2012: 1-6 - [c9]Matthias Sauer, Alexander Czutro, Bernd Becker, Ilia Polian:
On the quality of test vectors for post-silicon characterization. ETS 2012: 1-6 - [c8]Matthias Sauer, Alexander Czutro, Ilia Polian, Bernd Becker:
Small-delay-fault ATPG with waveform accuracy. ICCAD 2012: 30-36 - [c7]Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker:
Functional test of small-delay faults using SAT and Craig interpolation. ITC 2012: 1-8 - [c6]Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker:
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design 2012: 382-387 - [c5]Alexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker:
SAT-ATPG using preferences for improved detection of complex defect mechanisms. VTS 2012: 170-175 - 2011
- [c4]Matthias Sauer, Jie Jiang, Alejandro Czutro, Ilia Polian, Bernd Becker:
Efficient SAT-Based Search for Longest Sensitisable Paths. Asian Test Symposium 2011: 108-113 - [c3]Matthias Sauer, Alexander Czutro, Tobias Schubert, Stefan Hillebrecht, Ilia Polian, Bernd Becker:
SAT-based analysis of sensitisable paths. DDECS 2011: 93-98 - [c2]Matthias Sauer, Alejandro Czutro, Ilia Polian, Bernd Becker:
Estimation of component criticality in early design steps. IOLTS 2011: 104-110 - [c1]Matthias Sauer, Victor Tomashevich, Jörg Müller, Matthew Lewis, Andreas Spilla, Ilia Polian, Bernd Becker, Wolfram Burgard:
An FPGA-based framework for run-time injection and analysis of soft errors in microprocessors. IOLTS 2011: 182-185
Coauthor Index
[c62] [c56] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [j9] [j8] [j7] [c45] [c44] [c43] [c42] [c41] [i2] [j6] [j5] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [j4] [j3] [c33] [c32] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [j2] [j1] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
Alexander Czutro
aka: Alejandro Czutro
aka: Alejandro Czutro
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