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ORCIDJournal of Electronic Testing, Volume 7
Volume 7, Numbers 1-2, August 1995
- Vishwani D. Agrawal:
Editorial - Special issue on partial scan design. 5-6 - Johannes Steensma, Francky Catthoor, Hugo De Man:
Partial scan and symbolic test at the register-transfer level. 7-23 - Rajesh Gupta, Melvin A. Breuer:
Partial scan design of register-transfer level circuits. 25-46 - Kee Sup Kim, Charles R. Kime:
Partial scan flip-flop selection by use of empirical testability. 47-59 - Prashant S. Parikh, Miron Abramovici:
Testability-based partial scan analysis. 61-70 - Tatiana Orenstein, Zvi Kohavi, Irith Pomeranz:
An optimal algorithm for cycle breaking in directed graphs. 71-81 - Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal:
An exact algorithm for selecting partial scan flip-flops. 83-93 - Shang-E Tai, Debashis Bhattacharya:
A three-stage partial scan design method to ease ATPG. 95-104 - Sujit Dey, Srimat T. Chakradhar:
Design of testable sequential circuits by repositioning flip-flops. 105-114 - Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
Partial scan design and test sequence generation based on reduced scan shift method. 115-124 - Chih-Jen Lin, Yervant Zorian, Sudipta Bhawmik:
Integration of partial scan and built-in self-test. 125-137
Volume 7, Number 3, December 1995
- Vishwani D. Agrawal:
Editorial. 143 - Andrea Boni, Giovanni Chiorboli, G. Franco, M. Ostacoli, S. Mazzoleni:
Short test procedures for R-2R D/A converters by electrical modeling and application of the ambiguity algorithm. 145-155 - Ankan K. Pramanick, Sudhakar M. Reddy:
Efficient multiple path propagating tests for delay faults. 157-172 - Harry Hengster, Rolf Drechsler
, Bernd Becker:
On local transformations and path delay fault testability. 173-191 - T. Raju Damarla, Charles E. Stroud, Avinash Sathaye:
Multiple error detection and identification via signature analysis. 193-207 - Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller:
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. 209-221 - Claudio Costi, Micaela Serra, Donatella Sciuto:
A new DFT methodology for sequential circuits. 223-240 - Leendert M. Huisman:
Yield fluctuations and defect models. 241-254 - V. C. Prasad, N. Sarat Chandra Babu:
On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis. 255-258
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