ED&TC 1996: Paris, France

Session 1A: Formal Verification

Session 1B: System Design for Digital Broadband Telecom: Trends and System Design Challenges

Session 1C: BIST Pattern Generation

Session 2A: New Domains in High-Level Synthesis

Session 2C: Fault Analysis and Test Quality

Session 3A: Code Generation

Session 3B: IDDQ: You Heard the Hype, But What's Really Coming?

Session 3C: Test and BIST Beyond Chips

Session 4A: Transformations and Estimations

Session 4B: FPGA Placement and Routing

Session 4C: Self-Test Methodologies

Session 4D: Emerging Design Techniques

Session 5A: Low Power Design

Session 5B: Performance-Driven Routing

Session 5D: Test Generation for Mixed-Signal Circuits

Session 6A: Heterogeneous System Modelling and Design

Session 6B: Analysis in Digital Circuit Design

Session 6D: High Speed Signal Processing

Session 7A: Sequential Logic Synthesis

Session 7B: From High Level Verification to (Low Level) Extraction

Session 7C: Sequential Test Generation

Session 7D: Module Generators

Session 8A: Logic Synthesis

Session 8B: Memory Testing

Session 8C: Design Environments and CAD Tools for Microsystems Design

Session 9A: Partitioning in System Design

Session 9B: Synthesis and Testability

Session 9C: Novelties in Integrated System Design

Session 10A: Modelling and Design Strategies for Microsystems Design

Session 10C: New Technologies for Mixed-Signal Test

Session 11A: Recent Advances in Simulation

Session 11C: DFT Solutions and IDDQ

Poster Session

a service of Schloss Dagstuhl - Leibniz Center for Informatics