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ORCIDISED 2014: Surathkal, Mangalore, India
- 2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014. IEEE Computer Society 2014, ISBN 978-1-4799-6965-4
- Rolf Drechsler
, Ulrich Kühne:
Safe IP Integration Using Container Modules. 1-4 - Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
A Novel GNR Interconnect Model to Reduce Crosstalk Delay. 5-9 - Vipul Kumar Mishra, Anirban Sengupta:
PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis. 10-14 - P. Kavyashree, Siva Sankar Yellampalli:
The Design of Ultra Low Power CMOS CGLNA in Nanometer Technology. 15-19 - S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. 20-24 - U. Aparna, H. S. Mruthyunjaya, M. Sathish Kumar:
Plasmonic Lens Based on Elliptically Tapered Metallic Nano Slits. 25-28 - Sadeque Reza Khan, Rajsekhar Kr. Nath, M. S. Bhat:
GSM and GUI Based Remote Data Logging System. 29-32 - E. S. Shajahan, M. S. Bhat, B. Chenna Reddy:
Inductive Tuned High Isolation RF MEMS Capacitive Shunt Switches. 33-37 - Sovan Ghosh:
A Novel Temperature Stable Current Mode Bandgap for Wide Range of Supply Voltage Variation. 38-43 - Aditya Gour, Ramesh Sanga, R. P. Behera, Parashuram Sahoo, Nagarajan Murali, Sav Satyamurty:
Design and Development of FPGA and FPAA Based Remote Terminal Units for Nuclear Power Plants. 44-48 - Vijay Rao, P. P. Priyesh, Subrat Kar:
Pratham: A Low-Cost Wireless Node with Programmable Radio Range and Over-the-Air Programming Capability for Resource-Constrained Applications. 49-53 - D. N. Jagadish, M. S. Bhat:
Low Energy and Area Efficient Nonbinary Capacitor Array Based SAR ADC. 54-57 - D. N. Jagadish, M. S. Bhat:
A Low Voltage Inverter Based Differential Amplifier for Low Power Switched Capacitor Applications. 58-62 - Shailendra Kumar Tripathi, Mohammad Samar Ansari:
Tunable Active Biquad Filter in ±0.9V 32 Nm CNFET. 63-67 - Sudip Ghosh, Arijit Biswas, Santi P. Maity, Hafizur Rahaman:
Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA. 68-72 - Pranab Roy, Tamosa Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
Multilevel Homogeneous Detection Analyzer for Medical Diagnostic Application in Digital Microfluidic Biochips. 73-78 - Priya Meharde, Vandana Niranjan, Ashwani Kumar:
Low Voltage CMOS Active Inductor with Bandwidth and Linearity Improvement. 79-83 - Pramod Kaddi, Nagaveni Vamsi, Anil Appala, Ashudeb Dutta, Shiv Govind Singh, Nagarjuna Nallam:
Efficient Dual Band RF Energy Harvesting Front End for Ultra Low Power Sensitive Passive Wearable Devices. 84-88 - Bappaditya Mondal, Chandan Bandyopadhyay, Dipak Kumar Kole, Jimson Mathew, Hafizur Rahaman:
Diagnosis of SMGF in ESOP Based Reversible Logic Circuit. 89-93 - Manodipan Sahoo, Hafizur Rahaman:
Impact of Line Resistance Variations on Crosstalk Delay and Noise in Multilayer Graphene Nano Ribbon Interconnects. 94-98 - Manasi Das, Aritro Dey, Smita Sadhu, Tapan Kumar Ghoshal:
Joint Estimation of States and Parameters of a Reentry Ballistic Target Using Adaptive UKF. 99-103 - Chikku Abraham, R. Rakhee, Babita Roslind Jose:
A Multiple Input Multiple Output Switched Capacitor DC-DC Converter with Reduced Switch Count. 104-108 - A. Divya Rao, Piyush Kumar, Neha Nain, V. K. Agrawal:
MATLAB-Based GUI Development for Stochastic Noise Analysis of Tri-Axial Gyroscopes. 109-114 - Srinivas Sabbavarapu, Basireddy Karunakar Reddy, Amit Acharyya:
A New Dynamic Library Based IC Design Automation Methodology Using Functional Symmetry with NPN Class Representation Approach to Reduce NRE Costs and Time-to-Market. 115-119 - Naresh Vemishetty, Arpit Jain, Aashish Amber, Amit Acharyya:
A Low Complexity Architecture for Online On-chip Detection and Identification of f-QRS Feature for Remote Personalized Health Care Applications. 120-124 - Krishna Bharadwaj Chivukula, Naresh Vemishetty, Agathya Jagirdar, Amit Acharyya:
A Low-Complexity Onchip Real-Time Automated ECG Frame Identification Methodology Targeting Remote Health Care. 125-129 - R. Rajesh, Kannan Babu Ramia, Muralidhar Kulkarni:
Integration of LwIP Stack over Intel(R) DPDK for High Throughput Packet Delivery to Applications. 130-134 - Basireddy Karunakar Reddy, Srinivas Sabbavarapu, Amit Acharyya:
Effect of Constant One and Zero, Shared and Non-decomposed Nodes on Runtime and Graph Size of the Shannon Factor Graph (SFG). 135-139 - M. P. R. Sai Kiran, Y. Siva Krishna, Pachamuthu Rajalakshmi, Amit Acharyya:
System Architecture for Smart Ubiquitous Health Monitoring System with Area Optimization in Multiple On-chip Radios Scenario. 140-144 - Anish Morakhia, Sridhar Gunnam, Preejit Prakash, Sneha Kudli, Tonse Laxminidhi:
A Resolution Independent 2-Bits-per-Cycle SAR ADC. 145-149 - Navneet Upadhyay:
An Improved Multi-band Speech Enhancement Utilizing Masking Properties of Human Hearing System. 150-155 - Priyankar Talukdar:
Power-Aware Automated Pipelining of Combinational Circuits. 156-160 - Mamata Dalui, Biplab K. Sikdar:
CA Based Scalable Protocol Processor for Chip Multiprocessors. 161-165 - Bibhash Sen, Rijoy Mukherjee, Rajdeep Kumar Nath, Biplab K. Sikdar:
Design of Fault Tolerant Universal Logic in QCA. 166-170 - Rahul Shrestha, Roy Paily:
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique. 171-175 - Shrutika Joshi, A. Srinivas:
Power Aware Fault Tolerance in Wireless Networks with Heterogeneous Nodes. 176-181 - Arighna Deb, Debesh K. Das, Bhargab B. Bhattacharya:
Synthesis of Symmetric Boolean Functions Using a Three-Stage Network. 182-186 - C. Vasanthanayaki, A. Azhagu Jaisudhan Pazhani, Jincy Johnson:
VLSI Implementation of Low Power Multiple Single Input Change (MSIC) Test Pattern Generation for BIST Scheme. 187-191 - Neha Gupta, Ajay Kumar, Rishu Chaujar:
Impact of Channel Doping and Gate Length on Small Signal Behaviour of Gate Electrode Workfunction Engineered Silicon Nanowire MOSFET at THz Frequency. 192-196 - S. Murugan, D. Karthikesan, S. Sellathurai, E. Praveen, K. Jayakumar:
Design of Mechanical Sensing System Based on Nano BaTiO3 Embedded in Biopolymer Electret. 199-202 - Rajesh Mangalore Anand, Soujanya Ravula, M. A. Kalpashree, Soumya Satavisa:
Automated Physical Verification of I/O Pads in Full-Custom Environment. 203-205 - Jyoti Sharma, Mohammad Samar Ansari, Jankiballabh Sharma:
Electronically Tunable Resistor-less Universal Filter in ±0.5V 32nm CNFET. 206-207 - Swagata Roy Chatterjee, Soham Majumder, Bodhisatta Pramanik, Mohuya Chakraborty:
FPGA Implementation of Pipelined Blowfish Algorithm. 208-209 - Vasant Easwaran, Nagendra Gulur, Sushaanth Srirangapathi, Mihir Mody, Rahul Gulati, Prashant Karandikar, Prithvi Shankar:
Method to Determine Contrariety between Architectures Containing Stratified Memory Mapped Register Sets. 210-214 - Chandra Shaker Balure, M. Ramesh Kini:
A Survey - Super Resolution Techniques for Multiple, Single, and Stereo Images. 215-216 - S. Lalitha, Sahruday Patnaik, T. H. Arvind, Vivek Madhusudhan, Shikha Tripathi:
Emotion Recognition through Speech Signal for Human-Computer Interaction. 217-218 - Anush Bekal, Manish Goswami, B. R. Singh, Dipankar Pal:
A Low Power 8-Bit Asynchronous SAR ADC Design Using Charge Scaling DAC. 219-223 - Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika:
A New Design of an N-Bit Reversible Arithmetic Logic Unit. 224-225 - Yasha Jyothi M. Shirur, Lakshmi H. R., Veena S. Chakravarthi:
Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoC. 226-227 - S. V. VeenaDevi, A. G. Ananth:
Fixed Range Block Segmentation and Classification for Fractal Image Compression of Satellite Imageries. 228-231
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