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ORCID24th ASP-DAC 2019: Tokyo, Japan
- Toshiyuki Shibuya:
Proceedings of the 24th Asia and South Pacific Design Automation Conference, ASPDAC 2019, Tokyo, Japan, January 21-24, 2019. ACM 2019, ISBN 978-1-4503-6007-4
University design contest
- Kousuke Miyaji, Yuki Karasawa, Takanobu Fukuoka:
A wide conversion ratio, 92.8% efficiency, 3-level buck converter with adaptive on/off-time control and shared charge pump intermediate voltage regulator. 1-2 - Maya Matsunaga, Taiki Nakanishi, Atsuki Kobayashi, Kiichi Niitsu
:
A three-dimensional millimeter-wave frequency-shift based CMOS biosensor using vertically stacked spiral inductors in LC oscillators. 3-4 - Kenya Hayashi, Shigeki Arata, Ge Xu, Shunya Murakami, Cong Dang Bui, Takuyoshi Doike, Maya Matsunaga, Atsuki Kobayashi, Kiichi Niitsu:
Design of 385 x 385 μm2 0.165V 270pW fully-integrated supply-modulated OOK transmitter in 65nm CMOS for glasses-free, self-powered, and fuel-cell-embedded continuous glucose monitoring contact lens. 5-6 - Kiichi Niitsu, Taichi Sakabe, Mariko Miyachi, Yoshinori Yamanoi, Hiroshi Nishihara, Tatsuya Tomo, Kazuo Nakazato:
2D optical imaging using photosystem I photosensor platform with 32x32 CMOS biosensor array. 7-8 - Atsuki Kobayashi, Yuya Nishio, Kenya Hayashi, Shigeki Arata, Kiichi Niitsu:
Design of gate-leakage-based timer using an amplifier-less replica-bias switching technique in 55-nm DDC CMOS. 9-10 - Kiichi Niitsu, Yuuki Yamaji, Atsuki Kobayashi, Kazuo Nakazato:
A low-voltage CMOS electrophoresis IC using electroless gold plating for small-form-factor biomolecule manipulation. 11-12 - Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi:
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. 13-14 - Nobuaki Kobayashi, Tadayoshi Enomoto:
Development of a high stability, low standby power six-transistor CMOS SRAM employing a single power supply. 15-16 - Chihiro Matsui, Ken Takeuchi:
Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories. 17-18 - Taiki Nakanishi, Maya Matsunaga, Shunya Murakami, Atsuki Kobayashi, Kiichi Niitsu:
A 65-nm CMOS fully-integrated circulating tumor cell and exosome analyzer using an on-chip vector network analyzer and a transmission-line-based detection window. 19-20 - Nobuaki Kobayashi, Tadayoshi Enomoto:
Low standby power CMOS delay flip-flop with data retention capability. 21-22 - Mohammad Tahghighi, Wei Zhang:
Accelerate pattern recognition for cyber security analysis. 23-24 - Marco Winzker, Andrea Schwandt:
FPGA laboratory system supporting power measurement for low-power digital design. 25-26
Real-time embedded software
- Pedro Benedicte, Jaume Abella, Carles Hernández, Enrico Mezzetti, Francisco J. Cazorla:
Towards limiting the impact of timing anomalies in complex real-time processors. 27-32 - Petra R. Kleeberger, Juana Rivera, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
SeRoHAL: generation of selectively robust hardware abstraction layers for efficient protection of mixed-criticality systems. 33-38 - Yuanbin Zhou, Soheil Samii, Petru Eles, Zebo Peng:
Partitioned and overhead-aware scheduling of mixed-criticality real-time systems. 39-44
Hardware and system security
- Wenbin Xu, Lang Feng, Jeyavijayan Rajendran, Jiang Hu:
Layout recognition attacks on split manufacturing. 45-50 - Tung-Che Liang, Mohammed Shayan, Krishnendu Chakrabarty, Ramesh Karri:
Execution of provably secure assays on MEDA biochips to thwart attacks. 51-57 - Alexander Fell, Thinh Hung Pham, Siew-Kei Lam:
TAD: time side-channel attack defense of obfuscated source code. 58-63
Thermal- and power-aware design and optimization
- Xingxing Guo, Hai Wang, Chi Zhang, He Tang, Yuan Yuan:
Leakage-aware thermal management for multi-core systems using piecewise linear model based predictive control. 64-69 - Hsuan-Hsuan Hsiao, Hong-Wen Chiou, Yu-Min Lee:
Multi-angle bended heat pipe design using x-architecture routing with dynamic thermal weight on mobile devices. 70-75 - Dustin Peterson, Oliver Bringmann:
Fully-automated synthesis of power management controllers from UPF. 76-81
Reverse engineering: growing more mature - and facing powerful countermeasures
- Bernhard Lippmann, Michael Werner, Niklas Unverricht, Aayush Singla, Peter Egger, Anja Dübotzky, Horst A. Gieser, Martin Rasche, Oliver Kellermann, Helmut Graeb:
Integrated flow for reverse engineering of nanoscale technologies. 82-89 - Travis Meade, Jason Portillo, Shaojie Zhang, Yier Jin:
NETA: when IP fails, secrets leak. 90-95 - Johanna Baehr, Alessandro Bernardini, Georg Sigl, Ulf Schlichtmann:
Machine learning and structural characteristics for reverse engineering. 96-103 - Carina Wiesen, Nils Albartus, Max Hoffmann, Steffen Becker, Sebastian Wallat, Marc Fyrbiak, Nikol Rummel, Christof Paar:
Towards cognitive obfuscation: impeding hardware reverse engineering based on psychological insights. 104-111 - Maik Ender, Pawel Swierczynski, Sebastian Wallat, Matthias Wilhelm, Paul Martin Knopp, Christof Paar:
Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstream. 112-119
All about PIM
- Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
GraphSAR: a sparsity-aware processing-in-memory architecture for large-scale graph processing on ReRAMs. 120-126 - Shaahin Angizi, Zhezhi He, Deliang Fan:
ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks. 127-132 - Xizi Chen, Jingyang Zhu, Jingbo Jiang, Chi-Ying Tsui:
CompRRAE: RRAM-based convolutional neural network accelerator with reduced computations through a runtime activation estimation. 133-139 - Sheng Xu, Xiaoming Chen, Ying Wang, Yinhe Han, Xiaowei Li:
CuckooPIM: an efficient and less-blocking coherence mechanism for processing-in-memory systems. 140-145 - Jinshan Yue, Yongpan Liu, Fang Su, Shuangchen Li, Zhe Yuan, Zhibo Wang, Wenyu Sun, Xueqing Li, Huazhong Yang:
AERIS: area/energy-efficient 1T2R ReRAM based processing-in-memory neural network system-on-a-chip. 146-151
Design for reliability
- Ashkan Vakil, Houman Homayoun, Avesta Sasan:
IR-ATA: IR annotated timing analysis, a flow for closing the loop between PDN design, IR analysis & timing closure. 152-159 - Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, Bangqi Xu:
Learning-based prediction of package power delivery network quality. 160-166 - Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
Tackling signal electromigration with learning-based detection and multistage mitigation. 167-172 - Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi:
ROBIN: incremental oblique interleaved ECC for reliability improvement in STT-MRAM caches. 173-178 - Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang:
Aging-aware chip health prediction adopting an innovative monitoring strategy. 179-184
New advances in emerging computing paradigms
- Alwin Zulehner, Robert Wille:
Compiling SU(4) quantum circuits to IBM QX architectures. 185-190 - Toshinari Itoko, Rudy Raymond, Takashi Imamichi, Atsushi Matsuo, Andrew W. Cross:
Quantum circuit compilers using gate commutation rules. 191-196 - Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler:
Scalable design for field-coupled nanocomputing circuits. 197-202 - Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi:
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing. 203-209 - S. Rasoul Faraji, Kia Bazargan:
Hybrid binary-unary hardware accelerator. 210-215
Design, testing, and fault tolerance of neuromorphic systems
- Mengyun Liu, Lixue Xia, Yu Wang, Krishnendu Chakrabarty:
Fault tolerance in neuromorphic computing systems. 216-223 - Bing Li, Bonan Yan, Chenchen Liu, Hai (Helen) Li:
Build reliable and efficient neuromorphic design with memristor technology. 224-229 - Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Reliable in-memory neuromorphic computing using spintronics. 230-236
Memory-centric design and synthesis
- Alwin Zulehner, Kamalika Datta, Indranil Sengupta, Robert Wille:
A staircase structure for scalable and efficient synthesis of memristor-aided logic. 237-242 - Daewoo Kim, Sugil Lee, Jongeun Lee:
On-chip memory optimization for high-level synthesis of multi-dimensional data on FPGA. 243-248 - Houxiang Ji, Li Jiang, Tianjian Li, Naifeng Jing, Jing Ke, Xiaoyao Liang:
HUBPA: high utilization bidirectional pipeline architecture for neuromorphic computing. 249-254
Efficient modeling of analog, mixed signal and arithmetic circuits
- Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
Efficient sparsification of dense circuit matrices in model order reduction. 255-260 - Cunxi Yu, Tiankai Su, Atif Yasin, Maciej J. Ciesielski:
Spectral approach to verifying non-linear arithmetic circuits. 261-267 - Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan:
S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits. 268-273
Logic and precision optimization for neural network designs
- Mahdi Nazemi, Ghasem Pasandi, Massoud Pedram:
Energy-efficient, low-latency realization of neural networks through boolean logic minimization. 274-279 - Hyeon Uk Sim, Jongeun Lee:
Log-quantized stochastic computing for memory and computation efficient DNNs. 280-285 - Hanmin Park, Kiyoung Choi:
Cell division: weight bit-width reduction technique for convolutional neural network hardware accelerators. 286-291
Modern mask optimization: from shallow to deep learning
- Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan:
LithoROC: lithography hotspot detection with explicit ROC optimization. 292-298 - Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu:
Detecting multi-layer layout hotspots with adaptive squish patterns. 299-304 - Xingquan Li, Bei Yu, Jianli Chen, Wenxing Zhu:
A local optimal method on DSA guiding template assignment with redundant/dummy via insertion. 305-310 - Bo-Yi Yu, Yong Zhong, Shao-Yun Fang, Hung-Fei Kuo:
Deep learning-based framework for comprehensive mask optimization. 311-316
System level modelling methods I
- Yinghui Fan, Xiaoxi Wu, Jiying Dong, Zhi Qi:
AxDNN: towards the cross-layer design of approximate DNNs. 317-322 - Jiajun Li, Ying Wang, Bosheng Liu, Yinhe Han, Xiaowei Li:
Simulate-the-hardware: training accurate binarized neural networks for low-precision neural accelerators. 323-328 - Jingyu Wang, Zhe Yuan, Ruoyang Liu, Huazhong Yang, Yongpan Liu:
An N-way group association architecture and sparse data group association load balancing algorithm for sparse CNN accelerators. 329-334 - Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Maximizing power state cross coverage in firmware-based power management. 335-340
Testing and design for security
- Mason Chern, Shih-Wei Lee, Shi-Yu Huang, Yu Huang, Gaurav Veda, Kun-Han Hans Tsai, Wu-Tung Cheng:
Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. 341-346 - Tsai-Ling Tsai, Jin-Fu Li, Chun-Lung Hsu, Chi-Tien Sun:
Testing stuck-open faults of priority address encoder in content addressable memories. 347-351 - Lilas Alrahis, Muhammad Yasin, Hani H. Saleh, Baker Mohammad, Mahmoud Al-Qutayri, Ozgur Sinanoglu:
ScanSAT: unlocking obfuscated scan chains. 352-357 - Amin Rezaei, You Li, Yuanqi Shen, Shuyu Kong, Hai Zhou:
CycSAT-unresolvable cyclic logic encryption using unreachable states. 358-363
Network-centric design and system
- Mengquan Li, Weichen Liu, Lei Yang, Peng Chen, Duo Liu, Nan Guan:
Routing in optical network-on-chip: minimizing contention with guaranteed thermal reliability. 364-369 - Yuyang Wang, M. Ashkan Seyedi, Jared Hulme, Marco Fiorentino, Raymond G. Beausoleil, Kwang-Ting Cheng:
Bidirectional tuning of microring-based silicon photonic transceivers for optimal energy efficiency. 370-375 - Ning Lin, Hang Lu, Xin Wei, Xiaowei Li:
Redeeming chip-level power efficiency by collaborative management of the computation and communication. 376-381 - Moon Gi Seok, Hessam S. Sarjoughian, Daejin Park:
A high-level modeling and simulation approach using test-driven cellular automata for fast performance analysis of RTL NoC designs. 382-387
Advanced memory systems
- Jianfei Wang, Li Jiang, Jing Ke, Xiaoyao Liang, Naifeng Jing:
A sharing-aware L1.5D cache for data reuse in GPGPUs. 388-393 - Chuhan Min, Jiachen Mao, Hai Li, Yiran Chen:
NeuralHMC: an efficient HMC-based accelerator for deep neural networks. 394-399 - Xianwei Zhang, Rujia Wang, Youtao Zhang, Jun Yang:
Boosting chipkill capability under retention-error induced reliability emergency. 400-405
Learning: make patterning light and right
- Hao Geng, Haoyu Yang, Yuzhe Ma, Joydeep Mitra, Bei Yu:
SRAF insertion via supervised dictionary learning. 406-411 - Bentian Jiang, Hang Zhang, Jinglei Yang, Evangeline F. Y. Young:
A fast machine learning-based mask printability predictor for OPC acceleration. 412-419 - Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semi-supervised hotspot detection with self-paced multi-task learning. 420-425
Design and CAD for emerging memories
- Dawen Xu, Li Li, Ying Wang, Cheng Liu, Huawei Li:
Exploring emerging CNFET for efficient last level cache design. 426-431 - Lei Xie:
Mosaic: an automated synthesis flow for boolean logic based on memristor crossbar. 432-437 - Baogang Zhang, Necati Uysal, Deliang Fan, Rickard Ewetz:
Handling stuck-at-faults in memristor crossbar arrays using matrix transformations. 438-443
Optimized training for neural networks
- Zhuwei Qin, Fuxun Yu, Chenchen Liu, Xiang Chen:
CAPTOR: a class adaptive filter pruning framework for convolutional neural networks in mobile applications. 444-449 - Jiajun Li, Guihai Yan, Wenyan Lu, Shuhao Jiang, Shijun Gong, Jingya Wu, Junchao Yan, Xiaowei Li:
TNPU: an efficient accelerator architecture for training convolutional neural networks. 450-455 - Fuxun Yu, Chenchen Liu, Xiang Chen:
REIN: a robust training method for enhancing generalization ability of neural networks in autonomous driving systems. 456-461
New trends in biochips
- Sohini Saha, Debraj Kundu, Sudip Roy, Sukanta Bhattacharjee, Krishnendu Chakrabarty, Partha Pratim Chakrabarti, Bhargab B. Bhattacharya:
Factorization based dilution of biochemical fluids with micro-electrode-dot-array biochips. 462-467 - Tung-Che Liang, Yun-Sheng Chan, Tsung-Yi Ho, Krishnendu Chakrabarty, Chen-Yi Lee:
Sample preparation for multiple-reactant bioassays on micro-electrode-dot-array biochips. 468-473 - Zhanwei Zhong, Robert Wille, Krishnendu Chakrabarty:
Robust sample preparation on digital microfluidic biochips. 474-480
Power-efficient machine learning hardware design
- Setareh Behroozi, Jingjie Li, Jackson Melchert, Younghyun Kim:
SAADI: a scalable accuracy approximate divider for dynamic energy-quality scaling. 481-486 - Farhana Sharmin Snigdha, Ibrahim Ahmed, Susmita Dey Manasi, Meghna G. Mankalale, Jiang Hu, Sachin S. Sapatnekar:
SeFAct: selective feature activation and early classification for CNNs. 487-492 - Mohsen Imani, Sahand Salamat, Saransh Gupta, Jiani Huang, Tajana Rosing:
FACH: FPGA-based acceleration of hyperdimensional computing by reducing computational complexity. 493-498
Security of machine learning and machine learning for security: progress and challenges for secure, machine intelligent mobile systems
- Pu Zhao, Kaidi Xu, Sijia Liu, Yanzhi Wang, Xue Lin:
ADMM attack: an enhanced adversarial attack for deep neural networks with undetectable distortions. 499-505 - Tao Liu, Nuo Xu, Qi Liu, Yanzhi Wang, Wujie Wen:
A system-level perspective to understand the vulnerability of deep learning systems. 506-511 - Zirui Xu, Fuxun Yu, Chenchen Liu, Xiang Chen:
HAMPER: high-performance adaptive mobile security enhancement against malicious speech and image recognition. 512-517 - Hsin-Pai Cheng, Juncheng Shen, Huanrui Yang, Qing Wu, Hai Li, Yiran Chen:
AdverQuil: an efficient adversarial detection and alleviation technique for black-box neuromorphic computing systems. 518-525
System level modelling methods II
- Alessandro Cornaglia, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel:
SIMULTime: Context-sensitive timing simulation on intermediate code representation for rapid platform explorations. 526-531 - Amirhossein Esmaili, Mahdi Nazemi, Massoud Pedram:
Modeling processor idle times in MPSoC platforms to enable integrated DPM, DVFS, and task scheduling subject to a hard deadline. 532-537 - Hong-Wen Chiou, Yu-Min Lee, Shin-Yu Shiau, Chi-Wen Pan, Tai-Yu Chen:
Phone-nomenon: a system-level thermal simulator for handheld devices. 538-543 - Xiao Pan, Carna Zivkovic, Christoph Grimm:
Virtual prototyping of heterogeneous automotive applications: matlab, SystemC, or both? 544-549
Placement
- Sun ik Heo, Andrew B. Kahng, Minsoo Kim, Lutong Wang:
Diffusion break-aware leakage power optimization and detailed placement in sub-10nm VLSI. 550-556 - Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo:
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. 557-562 - Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
A shape-driven spreading algorithm using linear programming for global placement. 563-568 - Mateus Fogaça, Andrew B. Kahng, Ricardo Reis, Lutong Wang:
Finding placement-relevant clusters with fast modularity-based clustering. 569-576
Algorithms and architectures for emerging applications
- Shih-Yu Chen, Jie-Hong R. Jiang, Shou-Hung Welkin Ling, Shih-Hao Liang, Mao-Cheng Huang:
An approximation algorithm to the optimal switch control of reconfigurable battery packs. 577-584 - Sheng-Hao Lin, Tsung-Yi Ho:
Autonomous vehicle routing in multiple intersections. 585-590 - Minxuan Zhou, Mohsen Imani, Saransh Gupta, Yeseong Kim, Tajana Rosing:
GRAM: graph processing in a ReRAM-based computational memory. 591-596 - Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Arindam Basu:
ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing. 597-602
Embedded software for parallel architecture
- Milan Copic, Rainer Leupers, Gerd Ascheid:
Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration. 603-608 - Gereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen:
A heuristic for multi objective software application mappings on heterogeneous MPSoCs. 609-614 - Fang Wang, Zhaoyan Shen, Lei Han, Zili Shao:
ReRAM-based processing-in-memory architecture for blockchain platforms. 615-620
Machine learning and hardware security
- Song Bian, Masayuki Hiromoto, Takashi Sato:
Towards practical homomorphic email filtering: a hardware-accelerated secure naïve bayesian filter. 621-626 - Nimesh Shah, Manaar Alam, Durga Prasad Sahoo, Debdeep Mukhopadhyay, Arindam Basu:
A 0.16pJ/bit recurrent neural network based PUF for enhanced machine learning attack resistance. 627-632 - Wen Li, Ying Wang, Huawei Li, Xiaowei Li:
P3M: a PIM-based neural network model protection scheme for deep learning accelerator. 633-638
Memory architecture for efficient neural network computing
- Jilan Lin, Zhenhua Zhu, Yu Wang, Yuan Xie:
Learning the sparsity for ReRAM: mapping and pruning sparse neural network for ReRAM based accelerator. 639-644 - Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
In-memory batch-normalization for resistive memory based binary neural network hardware. 645-650 - Hyeon Uk Sim, Jason Helge Anderson, Jongeun Lee:
XOMA: exclusive on-chip memory architecture for energy-efficient deep learning acceleration. 651-656
Logic-level security and synthesis
- Yuanqi Shen, You Li, Amin Rezaei, Shuyu Kong, David Dlott, Hai Zhou:
BeSAT: behavioral SAT-based attack on cyclic logic encryption. 657-662 - Zhufei Chu, Mathias Soeken, Yinshui Xia, Lun-Yao Wang, Giovanni De Micheli:
Structural rewriting in XOR-majority graphs. 663-668 - Alwin Zulehner, Michael P. Frank, Robert Wille:
Design automation for adiabatic circuits. 669-674
Analysis and algorithms for digital design verification
- Samuel Hertz, Debjit Pal, Spencer Offenberger, Shobha Vasudevan:
A figure of merit for assertions in verification. 675-680 - Neil Veira, Zissis Poulos, Andreas G. Veneris:
Suspect2vec: a suspect prediction model for directed RTL debugging. 681-686 - Li-Jie Chen, Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo, Chi-Lai Huang:
Path controllability analysis for high quality designs. 687-692
FPGA and optics-based neural network designs
- Qin Li, Xiaofan Zhang, Jinjun Xiong, Wen-Mei Hwu, Deming Chen:
Implementing neural machine translation with bi-directional GRU and attention mechanism on FPGAs using HLS. 693-698 - Aidyn Zhakatayev, Jongeun Lee:
Efficient FPGA implementation of local binary convolutional neural network. 699-704 - Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan:
Hardware-software co-design of slimmed optical neural networks. 705-710
The resurgence of reconfigurable computing in the post moore era
- Vito Giovanni Castellana, Marco Minutoli, Antonino Tumeo, Marco Lattuada, Pietro Fezzardi, Fabrizio Ferrandi:
Software defined architectures for data analytics. 711-718 - Davide Giri, Paolo Mantovani, Luca P. Carloni:
Runtime reconfigurable memory hierarchy in embedded scalable platforms. 719-726 - Hosein Mohammadi Makrani, Hossein Sayadi, Tinoosh Mohsenin, Setareh Rafatirad, Avesta Sasan, Houman Homayoun:
XPPE: cross-platform performance estimation of hardware accelerators using machine learning. 727-732
Hardware acceleration
- Bosheng Liu, Xiaoming Chen, Ying Wang, Yinhe Han, Jiajun Li, Haobo Xu, Xiaowei Li:
Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. 733-738 - Daniel Peroni, Mohsen Imani, Tajana Rosing:
ALook: adaptive lookup for GPGPU acceleration. 739-746 - Abraham Addisie, Valeria Bertacco:
Collaborative accelerators for in-memory MapReduce on scale-up machines. 747-753
Routing
- Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young:
Detailed routing by sparse grid graph and minimum-area-captured path search. 754-760 - Necati Uysal, Wen-Hao Liu, Rickard Ewetz:
Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew. 761-766
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