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ORCIDGörschwin Fey
Person information
- affiliation: Hamburg University of Technology (TUHH), Institute of Embedded Systems, Germany
- affiliation: University of Bremen, Institute of Computer Science, Germany
- affiliation: German Aerospace Center (DLR), Bremen, Germany
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2020 – today
- 2024
[c156]Swantje Plambeck
, Aaron Bracht, Nemanja Hranisavljevic, Görschwin Fey:
FaMoS- Fast Model Learning for Hybrid Cyber-Physical Systems using Decision Trees. HSCC 2024: 7:1-7:10- [i9]Leandro Lanzieri, Lukasz Butkowski, Jirí Král, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt:
Studying the Degradation of Propagation Delay on FPGAs at the European XFEL. CoRR abs/2407.06643 (2024) - 2023
- [c155]Arne Grünhagen, Marina Tropmann-Frick, Annika Eichler, Görschwin Fey:
Predictive Maintenance for the Optical Synchronization System of the European XFEL: A Systematic Literature Survey. BTW 2023: 1023-1045 - [c154]Hany Abdelmaksoud, Zain Alabedin Haj Hammadeh, Görschwin Fey, Daniel Lüdtke:
DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate Representation. DATE 2023: 1-2 - [c153]Swantje Plambeck, Görschwin Fey:
Data-Driven Test Generation for Black-Box Systems From Learned Decision Tree Models. DDECS 2023: 27-32 - [c152]Ahmad Al-Zoubi, Benedikt Schaible, Gianluca Martino, Görschwin Fey:
Latency-Optimized Hardware Acceleration of Multilayer Perceptron Inference. DSD 2023: 235-241 - [c151]Leandro Lanzieri, Peter Kietzmann, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt:
Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. DSD 2023: 335-342 - [c150]Arne Grünhagen, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey:
Data-Based Condition Monitoring and Disturbance Classification in Actively Controlled Laser Oscillators. EJC 2023: 94-114 - [c149]Markus Knitt, Swantje Plambeck, Jan Christian Wieck, Julian Kohlisch, Stephan Balduin, Eric M. S. P. Veith, Jakob Schyga, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt:
Towards the Automatic Generation of Models for Prediction, Monitoring, and Testing of Cyber-Physical Systems. ETFA 2023: 1-4 - [c148]Khaled Galal Abdelwahab Abdelaziz, Ralph Görgen, Görschwin Fey:
FINaL: Driving High-Level Fault Injection Campaigns with Natural Language. ETS 2023: 1-4 - [c147]Bernhard J. Berger, Görschwin Fey:
Informatik für Ingenieure an der Technischen Universität Hamburg. GI-Jahrestagung 2023: 211-222 - [c146]Arne Grünhagen, Maximilian Schütte, Annika Eichler, Marina Tropmann-Frick, Görschwin Fey:
Enhancing Data Acquisition and Fault Analysis for Large-Scale Facilities: A Case Study on the Laser-Based Synchronization System at the European X-Ray Free-Electron Laser. LWDA 2023: 121-133 - [c145]Fin Hendrik Bahnsen, Bernhard J. Berger, Görschwin Fey:
GLRP: Guided by Layer-wise Relevance Propagation - Selecting Crucial Neurons in Artificial Neural Networks. MOCAST 2023: 1-6 - [i8]Leandro Lanzieri, Gianluca Martino, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt, Matthias Wählisch:
A Review of Techniques for Ageing Detection and Monitoring on Embedded Systems. CoRR abs/2301.06804 (2023) - [i7]Leandro Lanzieri, Peter Kietzmann, Görschwin Fey, Holger Schlarb, Thomas C. Schmidt:
Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning. CoRR abs/2307.06693 (2023) - 2022
- [c144]Swantje Plambeck, Görschwin Fey:
Regression Trees for System Models and Prediction. OVERLAY@AI*IA 2022: 57-61 - [c143]Swantje Plambeck, Lutz Schammer, Görschwin Fey:
On the Viability of Decision Trees for Learning Models of Systems. ASP-DAC 2022: 696-701 - [c142]Swantje Plambeck, Görschwin Fey:
Decision Tree Models of Continuous Systems. ETFA 2022: 1-8 - [c141]Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt:
Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. IPIN 2022: 1-8 - [c140]Lutz Schammer, Jan Runge, Paula Klimach, Görschwin Fey:
Design Understanding: Identifying Instruction Pipelines in Hardware Designs. MOCAST 2022: 1-6 - [c139]Görschwin Fey, Martin Fränzle, Rolf Drechsler:
Self-Explanation in Systems of Systems. RE Workshops 2022: 85-91 - [c138]Gianluca Martino, Görschwin Fey:
Runtime Monitoring of c-LTL Specifications on FPGAs Using HLS. SMACD 2022: 1-4 - [c137]Ahmad Al-Zoubi, Gianluca Martino, Fin Hendrik Bahnsen, Jun Zhu, Holger Schlarb, Görschwin Fey:
CNN Implementation and Analysis on Xilinx Versal ACAP at European XFEL. SOCC 2022: 1-6 - [i6]Jakob Schyga, Swantje Plambeck, Johannes Hinckeldeyn, Görschwin Fey, Jochen Kreutzfeldt:
Decision Trees for Analyzing Influences on the Accuracy of Indoor Localization Systems. CoRR abs/2207.03853 (2022) - 2021
- [c136]Arne Grünhagen, Julien Branlard, Annika Eichler, Gianluca Martino, Görschwin Fey, Marina Tropmann-Frick:
Fault Analysis of the Beam Acceleration Control System at the European XFEL using Data Mining. ATS 2021: 61-66 - [c135]Lutz Schammer, Swantje Plambeck, Fin Hendrik Bahnsen, Görschwin Fey:
Learning Models of Cyber-Physical Systems using Automata Learning. COMPSAC 2021: 1224-1229 - [c134]Gianluca Martino, Arne Grünhagen, Julien Branlard, Annika Eichler, Görschwin Fey, Holger Schlarb:
Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital Systems. DSD 2021: 123-130 - [c133]Swantje Plambeck, Gianluca Martino, Görschwin Fey:
Metrics for the Evaluation of Approximate Sequential Streaming Circuits. DSD 2021: 208-211 - [c132]Fin Hendrik Bahnsen, Jan Kaiser, Görschwin Fey:
Designing Recurrent Neural Networks for Monitoring Embedded Devices. ETS 2021: 1-4 - [c131]Fin Hendrik Bahnsen, Görschwin Fey:
YAPS - Your Open Examination System for Activating and emPowering Students. ICCSE 2021: 98-103 - [c130]Fin Hendrik Bahnsen, Vanessa Klebe, Görschwin Fey:
Effect Analysis of Low-Level Hardware Faults on Neural Networks using Emulated Inference. MOCAST 2021: 1-6 - [i5]Fin Hendrik Bahnsen, Görschwin Fey:
YAPS - Your Open Examination System for Activating and emPowering Students. CoRR abs/2105.06552 (2021) - [i4]Swantje Plambeck, Jakob Schyga, Johannes Hinckeldeyn, Jochen Kreutzfeldt, Görschwin Fey:
Automata Learning for Automated Test Generation of Real Time Localization Systems. CoRR abs/2105.11911 (2021) - 2020
- [c129]Gianluca Martino, Heinz Riener, Görschwin Fey:
Revisiting Explicit Enumeration for Exact Synthesis. DSD 2020: 29-34
2010 – 2019
- 2019
- [j21]Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck:
Synthesizing adaptive test strategies from temporal logic specifications. Formal Methods Syst. Des. 55(2): 103-135 (2019) - [c128]Fin Hendrik Bahnsen, Görschwin Fey:
Local Monitoring of Embedded Applications and Devices using Artificial Neural Networks. DSD 2019: 485-491 - [c127]Görschwin Fey, Alberto García Ortiz:
Symbolic Circuit Analysis under an Arc Based Timing Model. ETS 2019: 1-2 - [c126]Gianluca Martino, Görschwin Fey:
Syntax-Guided Enumeration of Temporal Properties. FDL 2019: 1-8 - [c125]Fin Hendrik Bahnsen, Görschwin Fey:
Approximation of Neural Networks for Verification. MBMV 2019: 1-10 - [c124]Görschwin Fey, Rolf Drechsler:
Self-Explaining Digital Systems - Some Technical Steps. MBMV 2019: 1-8 - [c123]Tara Ghasempouri, Jan Malburg, Alessandro Danese, Graziano Pravadelli, Görschwin Fey, Jaan Raik:
Engineering of an Effective Automatic Dynamic Assertion Mining Platform. VLSI-SoC 2019: 111-116 - 2018
- [c122]Abraham Temesgen Tibebu, Görschwin Fey:
Augmenting All Solution SAT Solving for Circuits with Structural Information. DDECS 2018: 117-122 - [c121]Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey:
Software-Level TMR Approach for On-Board Data Processing in Space Applications. DDECS 2018: 147-152 - [c120]Jan Malburg, Heinz Riener, Görschwin Fey:
Mining Latency Guarantees for RTL Designs. ISMVL 2018: 68-73 - [c119]Rolf Drechsler, Christoph Lüth, Görschwin Fey, Tim Güneysu:
Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW 2018: 1-6 - [c118]Görschwin Fey, Tara Ghasempouri, Swen Jacobs, Gianluca Martino, Jaan Raik, Heinz Riener:
Design Understanding: From Logic to Specification*. VLSI-SoC 2018: 172-175 - [i3]Roderick Bloem, Görschwin Fey, Fabian Greif, Robert Könighofer, Ingo Pill, Heinz Riener, Franz Röck:
Synthesizing Adaptive Test Strategies from Temporal Logic Specifications. CoRR abs/1809.01607 (2018) - 2017
- [j20]Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
A High-Level Approach to Analyze the Effects of Soft Errors on Lossless Compression Algorithms. J. Electron. Test. 33(1): 53-64 (2017) - [j19]Gökçe Aydos, Görschwin Fey:
Empirical results on parity-based soft error detection with software-based retry. Microprocess. Microsystems 48: 62-68 (2017) - [j18]Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017) - [c117]Jan Malburg, Tino Flenker, Görschwin Fey:
Property mining using dynamic dependency graphs. ASP-DAC 2017: 244-250 - [c116]Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
CEGAR-based EF synthesis of Boolean functions with an application to circuit rectification. ASP-DAC 2017: 251-256 - [c115]Tino Flenker, Görschwin Fey:
Mapping abstract and concrete hardware models for design understanding. DDECS 2017: 16-21 - [c114]Robert Schmidt, Alberto García Ortiz, Görschwin Fey:
Temporal redundancy latch-based architecture for soft error mitigation. IOLTS 2017: 240-243 - [c113]Tino Flenker, Jan Malburg, Görschwin Fey, Serhiy Avramenko, Massimo Violante, Matteo Sonza Reorda:
Towards Making Fault Injection on Abstract Models a More Accurate Tool for Predicting RT-Level Effects. ISVLSI 2017: 533-538 - [c112]Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
Counterexample-Guided EF Synthesis of Boolean Functions. MBMV 2017: 67-74 - 2016
- [j17]Jan Malburg, Alexander Finder, Görschwin Fey:
Debugging hardware designs using dynamic dependency graphs. Microprocess. Microsystems 47: 347-359 (2016) - [c111]Heinz Riener, Robert Könighofer, Görschwin Fey, Roderick Bloem:
SMT-Based CPS Parameter Synthesis. ARCH@CPSWeek 2016: 126-133 - [c110]Gökçe Aydos, Görschwin Fey:
Exploiting error detection latency for parity-based soft error detection. DDECS 2016: 3-8 - [c109]Niels Thole, Lorena Anghel, Görschwin Fey:
A hybrid algorithm to conservatively check the robustness of circuits. ETS 2016: 1-2 - [c108]Gadi Aleksandrowicz, Eli Arbel, Roderick Bloem, Timon D. ter Braak, Sergei Devadze, Görschwin Fey, Maksim Jenihhin, Artur Jutman, Hans G. Kerkhoff, Robert Könighofer, Jan Malburg, Shiri Moran, Jaan Raik, Gerard K. Rauwerda, Heinz Riener, Franz Röck, Konstantin Shibin, Kim Sunesen, Jinbo Wan, Yong Zhao:
Designing reliable cyber-physical systems overview associated to the special session at FDL'16. FDL 2016: 1-8 - [c107]Niels Thole, Heinz Riener, Görschwin Fey:
Equivalence checking on ESL utilizing a priori knowledge. FDL 2016: 1-8 - [c106]Heinz Riener, Görschwin Fey:
Exact diagnosis using boolean satisfiability. ICCAD 2016: 53 - [c105]Sandip Ray, Ian G. Harris, Görschwin Fey, Mathias Soeken:
Multilevel design understanding: from specification to logic (invited paper). ICCAD 2016: 133 - [c104]Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey, Jan-Gerd Mess, Robert Schmidt:
On the robustness of DCT-based compression algorithms for space applications. IOLTS 2016: 1-2 - [c103]Niels Thole, Görschwin Fey, Alberto García Ortiz:
A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. ISVLSI 2016: 278-283 - [c102]Heinz Riener, Görschwin Fey:
Counterexample-guided diagnosis. IVSW 2016: 1-6 - [c101]Serhiy Avramenko, Matteo Sonza Reorda, Massimo Violante, Görschwin Fey:
Analysis of the effects of soft errors on compression algorithms through fault injection inside program variables. LATS 2016: 14-19 - [c100]Pascal Pieper, Fabian Greif, Görschwin Fey:
Umgebung für automatisierte Tests von Dateisystemen auf NAND-Flash-Speichern. Echtzeit 2016: 127-132 - [c99]Niklas Krafczyk, Heinz Riener, Görschwin Fey:
WCET overapproximation for software in the context of a Cyber-Physical System. VLSI-SoC 2016: 1-6 - 2015
- [j16]Mehdi Dehbashi, Görschwin Fey:
Transaction-based online debug for NoC-based multiprocessor SoCs. Microprocess. Microsystems 39(3): 157-166 (2015) - [c98]Tino Flenker, André Sülflow, Görschwin Fey:
Diagnostic Tests and Diagnosis for Delay Faults Using Path Segmentation. ATS 2015: 145-150 - [c97]Niels Thole, Heinz Riener, Görschwin Fey:
Equivalence Checking on System Level Using a Priori Knowledge. DDECS 2015: 177-182 - [c96]Gökçe Aydos, Görschwin Fey:
Parity-based Soft Error Detection with Software-based Retry vs. Triplication-based Soft Error Correction - An Analytical Comparison on a Flash-based FPGA Architecture. GI-Jahrestagung 2015: 1415-1429 - [c95]Niels Thole, Görschwin Fey, Alberto García Ortiz:
Conservatively Analyzing Transient Faults. ISVLSI 2015: 50-55 - [c94]Heinz Riener, Michael Kirkedal Thomsen, Görschwin Fey:
Execution Tracing of C Code for Formal Analysis (Extended Abstract). MBMV 2015: 160-164 - [c93]Gökçe Aydos, Görschwin Fey:
Empirical results on parity-based soft error detection with software-based retry. NORCAS 2015: 1-4 - [c92]Gökçe Aydos, Görschwin Fey:
In-circuit Error Detection with Software-based Error Correction - An Alternative to TMR. SyDe Summer School 2015: 272-274 - [c91]Niels Thole, Görschwin Fey:
Formal Verification of Robustness. SyDe Summer School 2015: 305-307 - [c90]Heinz Riener, Rüdiger Ehlers, Görschwin Fey:
Path-Based Program Repair. FESCA 2015: 22-32 - 2014
- [j15]Alexander Finder, André Sülflow, Görschwin Fey:
Latency Analysis for Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(4): 643-647 (2014) - [j14]Jan Malburg, Alexander Finder, Görschwin Fey:
A Simulation-Based Approach for Automated Feature Localization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1886-1899 (2014) - [c89]Jan Malburg, Niklas Krafczyk, Görschwin Fey:
Automatically connecting hardware blocks via light-weight matching techniques. DDECS 2014: 21-26 - [c88]Mehdi Dehbashi, Görschwin Fey:
Sat-based speedpath debugging using waveforms. ETS 2014: 1-6 - [c87]Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler:
MetaSMT: a unified interface to SMT-LIB2. FDL 2014: 1-6 - [c86]Mehdi Dehbashi, Görschwin Fey:
SAT-based speedpath debugging using X traces. IDT 2014: 100-105 - [c85]Niels Thole, Görschwin Fey:
Equivalence Checking on System Level using Stepwise Induction. MBMV 2014: 197-200 - [c84]Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey:
A Logic for Cardinality Constraints (Extended Abstract). MBMV 2014: 217-220 - [c83]Jan Malburg, Emmanuelle Encrenaz-Tiphène, Görschwin Fey:
Mutation Based Feature Localization. MTV 2014: 49-54 - [c82]Mehdi Dehbashi, Görschwin Fey:
Transaction-Based Online Debug for NoC-Based Multiprocessor SoCs. PDP 2014: 400-404 - [c81]Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Synchronization Bugs at RTL. VLSID 2014: 44-49 - 2013
- [j13]Mehdi Dehbashi, Görschwin Fey:
Debug Automation for Logic Circuits Under Timing Variations. IEEE Des. Test 30(6): 60-69 (2013) - [j12]Daniel Große, Görschwin Fey, Rolf Drechsler:
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 62 (2013) - [j11]Mehdi Dehbashi, André Sülflow, Görschwin Fey:
Automated design debugging in a testbench-based verification environment. Microprocess. Microsystems 37(2): 206-217 (2013) - [c80]Robert C. Aitken, Görschwin Fey, Zbigniew T. Kalbarczyk, Frank Reichenbach, Matteo Sonza Reorda:
Reliability analysis reloaded: how will we survive? DATE 2013: 358-367 - [c79]Heinz Riener, Stefan Frehse, Görschwin Fey:
Improving fault tolerance utilizing hardware-software-co-synthesis. DATE 2013: 939-942 - [c78]Jan Malburg, Alexander Finder, Görschwin Fey:
Tuning dynamic data flow analysis to support design understanding. DATE 2013: 1179-1184 - [c77]Mehdi Dehbashi, Görschwin Fey:
Efficient automated speedpath debugging. DDECS 2013: 48-53 - [c76]Alexander Finder, Jan-Philipp Witte, Görschwin Fey:
Debugging HDL designs based on functional equivalences with high-level specifications. DDECS 2013: 60-65 - [c75]Heinz Riener, Görschwin Fey:
Yet a Better Error Explanation Algorithm (Extended Abstract). MBMV 2013: 193-194 - [e1]Lukás Sekanina, Görschwin Fey, Jaan Raik, Snorre Aunet, Richard Ruzicka:
16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2013, Karlovy Vary, Czech Republic, April 8-10, 2013. IEEE Computer Society 2013, ISBN 978-1-4673-6135-4 [contents] - 2012
- [c74]Mehdi Dehbashi, Görschwin Fey:
Automated Post-Silicon Debugging of Failing Speedpaths. Asian Test Symposium 2012: 13-18 - [c73]Jan Malburg, Alexander Finder, Görschwin Fey:
Automated feature localization for hardware designs using coverage metrics. DAC 2012: 941-946 - [c72]Mehdi Dehbashi, Görschwin Fey:
Automated debugging from pre-silicon to post-silicon. DDECS 2012: 324-329 - [c71]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
On Modeling and Evaluation of Logic Circuits under Timing Variations. DSD 2012: 431-436 - [c70]Mehdi Dehbashi, Görschwin Fey, Kaushik Roy, Anand Raghunathan:
Functional analysis of circuits under timing variations. ETS 2012: 1 - [c69]Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler:
Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90 - [c68]Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow:
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference 2012: 260-265 - [c67]Jan Malburg, Alexander Finder, Görschwin Fey:
Automated Feature Localization for Hardware Designs using Coverage Metrics. MBMV 2012: 85-96 - [c66]Heinz Riener, Görschwin Fey:
Model-based diagnosis versus error explanation. MEMOCODE 2012: 43-52 - [c65]Heinz Riener, Görschwin Fey:
FAuST: A Framework for Formal Verification, Automated Debugging, and Software Test Generation. SPIN 2012: 234-240 - [i2]Görschwin Fey, Masahiro Fujita, Natasa Miskov-Zivanov, Kaushik Roy, Matteo Sonza Reorda:
Verifying Reliability (Dagstuhl Seminar 12341). Dagstuhl Reports 2(8): 57-73 (2012) - 2011
- [j10]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1239-1252 (2011) - [c64]