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ORCIDISCAS 1999: Orlando, Florida, USA - Volume 6
- Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999. IEEE 1999, ISBN 0-7803-5471-0
- Axel Wenzler, Ernst Lücker:
Analysis of the periodic steady-state in nonlinear circuits using an adaptive function base. 1-4 - Domine M. W. Leenaerts:
Symbolic analysis of large signals in nonlinear systems. 5-8 - C. M. Arturi, Alessandro Gandelli, Sonia Leva, S. Marchi, Adriano Paolo Morando:
Multiresolution analysis of time-variant electrical networks. 9-13 - Takashi Hisakado, Kohshi Okumura:
Steady states prediction in nonlinear circuit by wavelet transform. 14-17 - Patrik Eriksson, Hannu Tenhunen:
A model for predicting sampler RF bandwidth and conversion loss. 18-21 - Dario D'Amore, Paolo Maffezzoni:
A new diode model formulation for electro-thermal analysis. 22-25 - Craig S. Petrie, J. Alvin Connelly:
The sampling of noise for random number generation. 26-29 - Kam-Weng Tam, P. Vitor, J. C. Freire, Rui Paulo Martins:
New microwave bandstop filter using lumped and transversal network. 30-32 - Atsushi Kamo, Takayuki Watanabe, Hideki Asai:
Expanded GMC for transient analysis of transmission line networks. 33-36 - Delmar Broglio Carvalho, Sidnei Noceti Filho, Rui Seara:
Design of phase equalizers via symmetry of the impulse response. 37-40 - Corneliu Rusu, Pauli Kuosmanen:
Logarithmic sampling of gain and phase approximation. 41-44 - Kisuk Yoo, Sanggee Kang, Jae-Ick Choi, Jong-Suk Chae:
Adaptive feed-forward linear power amplifier (LPA) for the IMT-2000 frequency band. 45-48 - David Báez-López, E. Jiménez-López:
A modified inverse-Chebyshev filter with an all positive elements ladder passive realization. 49-52 - Lawrence A. Carastro, Ravi Poddar, Emily Moon, Martin A. Brooke, Nan M. Jokerst:
Passive device modeling methodology using nonlinear optimization. 53-56 - Bor-Ren Lin, Hsin-Hung Lu:
Multilevel PWM for single-phase power factor pre-regulator. 57-60 - Michiel H. L. Kouwenhoven, Jan Mulder, Wouter A. Serdijn, Arthur H. M. van Roermund:
Analysis of noise in higher-order translinear filters. 61-64 - G. Efthivoulidis, Yannis P. Tsividis:
Signal analysis of externally linear filters. 65-68 - F. C. M. Kuijstermans, F. M. Diepstraten, Wouter A. Serdijn, Pieter van der Kloet, Arie van Staveren, Arthur H. M. van Roermund:
The linear time-varying approach applied to a first-order dynamic translinear filter. 69-72 - M. Keramat:
Theoretical bases of convolution technique in gradient estimation of average quality index of electronic circuits. 73-76 - Bor-Ren Lin, Yuen-Chou Hsieh:
High power factor of metal halide lamp with dimming control. 77-80 - Masahiro Yamauchi, Toshimasa Watanabe:
A heuristic algorithm SDS for scheduling with timed Petri nets. 81-84 - J. Martínez-Castillo, José Silva-Martínez:
Transimpedance amplifiers for optical fiber systems based on common-base transistors. 85-88 - Chang-Hyeon Lee, K. McCellan, John Choma Jr.:
Supply noise insensitive bandgap regulator using capacitive charge pump DC-DC converter. 89-92 - Laleh Behjat, Anthony Vannelli:
VLSI concentric partitioning using interior point quadratic programming. 93-96 - Adnan Harb, Mohamad Sawan:
New low-power low-voltage high-CMRR CMOS instrumentation amplifier. 97-100 - P. A. Ramamoorthy:
Nonlinear signal processor design: a building block approach. 101-104 - Ronald J. Pieper, Sherif Michael:
Circuit modeling to predict the performance of force-cooled cold plate structures. 105-108 - M. D. Bagewadi, B. G. Fernandes, R. V. S. Subrahmanyam:
A novel QRDCL circuit for zero voltage switched inverter. 109-112 - D. L. Youngblood:
Multi-mode impedance synthesis for subscriber line applications. 113-116 - Guo-Hui Lin, Guoliang Xue:
Balancing Steiner minimum trees and shortest-path trees in the rectilinear plane. 117-120 - Miuno Toshihiro, Toshimasa Watanabe:
Extracting nonplanar connections in a terminal-vertex graph. 121-124 - Guo-Hui Lin, Andrew P. Thurber, Guoliang Xue:
The 1-Steiner tree problem in lambda-3 geometry plane. 125-128 - Kiichiro Tsuji:
Structural properties for transformation of extended marked graphs. 129-132 - Rafael Vargas-Bernal, Arturo Sarmiento-Reyes:
A topology-based method for identifying flip-flop graphs in BJT circuits. 133-136 - Jun Inagaki, Miki Haseyama, Hideo Kitajima:
A genetic algorithm for determining multiple routes and its applications. 137-140 - J. Scanlon, N. Deo:
Graph-theoretic algorithms for image segmentation. 141-144 - Gregory Tumbush, Dinesh Bhatia:
Clustering to improve bi-partition quality and run time. 145-148 - Chen Liu, Mingde Dai, Xin-Yu Wu, Wai-Kai Chen:
A new algorithm for computing the overall network reliability. 149-152 - Hiroshi Tamura, Masakazu Sengoku, Keisuke Nakano, Shoji Shinoda:
Graph theoretic or computational geometric research of cellular mobile communications. 153-156 - Hongfang Liu, D. Frank Hsu, S. Horiguchi:
Generalized shuffle-exchange digraphs: Hamiltonian properties. 157-160 - Krishnaiyan Thulasiraman, Anindya Das, Kaiyuan Huang, Vinod K. Agarwal:
Correct diagnosis of almost all faulty units in a multiprocessor system. 161-164 - Toshinori Yamada, Satoshi Imai, Shuichi Ueno:
On VLSI decompositions for deBruijn graphs. 165-169 - Wai-Kei Mak, D. F. Wong
:
A fast hypergraph minimum cut algorithm. 170-173 - Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan:
Enumerating the min-cuts for applications to graph extraction under size constraints. 174-177 - Majid Sarrafzadeh, Toshihiko Takahashi:
A fast algorithm for routability testing. 178-181 - Guoliang Xue, Guo-Hui Lin, Ding-Zhu Du:
Grade of service Euclidean Steiner minimum trees. 182-185 - John P. Fishburn:
Optimization-based calibration of a static timing analyzer to path delay measurements. 186-189 - Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
Signal waveform characterization in RLC trees. 190-193 - Jinghong Chen, Sung-Mo Kang:
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits. 194-197 - Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. Polychronopoulos:
An analytical, transistor-level energy model for SRAM-based caches. 198-201 - Shanthi Pavan, Yannis P. Tsividis, Krishnaswamy Nagaraj:
Modeling of accumulation MOS capacitors for analog design in digital VLSI processes. 202-205 - Elmar Gondro, Peter Klein, Franz Schuler:
An analytical source-and-drain series resistance model of quarter micron MOSFETs and its influence on circuit simulation. 206-209 - Sang Won Song, Mohammed Ismail, Gyu Moon, Dong Yong Kim:
Accurate modeling of simultaneous switching noise in low voltage digital VLSI. 210-213 - Yi-Kan Cheng, Sung-Mo Kang:
Temperature-driven power and timing analysis for CMOS ULSI circuits. 214-217 - Anil Samavedam, Kartikeya Mayaram, Terri S. Fiez:
Design-oriented substrate noise coupling macromodels for heavily doped CMOS processes. 218-221 - Massimo Conti, Paolo Crippa, Simone Orcioni, Claudio Turchetti:
Statistical modeling of MOS transistor mismatch based on the parameters' autocorrelation function. 222-225 - J. H. Wang:
Event-overlapping processing in current waveform simulation. 226-229 - Takao Myono, E. Nishibe, S. Kikuchi, K. Iwatsu, Tatsuya Suzuki, Y. Sasaki, K. Itoh, Haruo Kobayashi:
Modeling and parameter extraction technique for high-voltage MOS device. 230-233 - Alexander Chatzigeorgiou, Spiridon Nikolaidis, Ioannis Tsoukalas, Odysseas G. Koufopavlou:
CMOS gate modeling based on equivalent inverter. 234-237 - Rex Lowther:
Compact modeling of interconnect and substrate coupling at GHz frequencies. 238-241 - Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar:
Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques. 242-245 - Zhong-Fang Jin, Jean-Jacques Laurin, Yvon Savaria, Pierre Garon:
A new approach to analyze interconnect delays in RC wire models. 246-249 - Ninglong Lu, Ibrahim N. Hajj:
A reduced-order scheme for coupled lumped-distributed interconnect simulation. 250-253 - Fenghao Mu, Christer Svensson:
Methodology of layout based schematic and its usage in efficient high performance CMOS design. 254-257 - Haksu Kim, Dian Zhou:
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles. 258-261 - D. Stroobannt:
PIN count prediction in ratio cut partitioning for VLSI and ULSI. 262-265 - Takayuki Watanabe, Hideki Asai:
Efficient synthesis technique of time-domain models for interconnects having 3-D structures based on FDTD method. 266-269 - Yen-Tai Lai, Chi-Chou Kao, Wu-Chien Shieh:
A quadratic programming method for interconnection crosstalk minimization. 270-273 - Yiqun Lin, Robert Lomenick, Rex Lowther, Wenhua Ni, Widad Rafie-Hibner, Orlando Ruiz, Jim Furino:
Interconnect model generation tool. 274-277 - Adrian Maxim, Danielle Andreu, Marc Cousineau, Jacques Boucher:
A novel SPICE behavioral macromodel of operational amplifiers including a high accuracy description of frequency characteristics. 278-281 - Robert H. Caverly, N. Quinn:
A SPICE model for simulating the impedance-frequency characteristics of high frequency PIN switching diodes. 282-285 - Ecevit Yilmaz, Michael M. Green:
Some standard SPICE dc algorithms revisited: why does SPICE still not converge? 286-289 - A. Dyes, E. Chan, H. Hofmann, W. Horia, Ljiljana Trajkovic:
Simple implementations of homotopy algorithms for finding DC solutions of nonlinear circuits. 290-293 - Zbigniew Galias:
Proving the existence of periodic solutions using global interval Newton method. 294-297 - Fabrizio Bonani, Marco Gilli:
A harmonic balance approach to bifurcation analysis of limit cycles. 298-301 - Lidia Daldoss, Paolo Gubian, Michele Quarantelli:
Transient sensitivity computation in circuit simulation. 302-305 - Mohammed A. Al-Saleh, Mustahsan Mir:
A modified univariate search algorithm. 306-309 - Leonard A. MacEachern:
Constrained circuit optimization via library table genetic algorithms. 310-313 - Yaser M. A. Khalifa, David H. Horrocks:
Isomorphism elimination for the enhancement of genetically generated analog circuits. 314-317 - Norihiko Shinomiya, Hitoshi Watanabe:
Distributed meta-heuristic method for network optimization problems in information network. 318-321 - Mikio Hasegawa, Tohru Ikeguchi, Kazuyuki Aihara:
A novel approach for combinatorial optimization problems using chaotic neurodynamics. 322-325 - Maitham Shams, Mohamed I. Elmasry:
A formulation for quick evaluation and optimization of digital CMOS circuits. 326-329 - Wei Wang, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang:
A high-speed residue-to-binary converter and a scheme for its VLSI implementation. 330-333 - Rajamohana Hegde, Naresh R. Shanbhag:
Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. 334-337 - Steve Hranilovic, David A. Johns:
A multilevel modulation scheme for high-speed wireless infrared communications. 338-341 - Chi Wai Yung, Hung Fai Fu, Chi-Ying Tsui, Roger S. Cheng, D. George:
Unequal error protection for wireless transmission of MPEG audio. 342-345 - Vuk Borich, Jack East, George Haddad:
A fixed-point harmonic balance approach for circuit simulation under modulated carrier excitation. 346-349 - Roman Genov, Gert Cauwenberghs:
16-channel single-chip current-mode track-and-hold acquisition system with 100 dB dynamic range. 350-353 - S. Nagavarapu, J. Yan, Edward K. F. Lee, Randall L. Geiger:
An asynchronous data recovery/retransmission technique with foreground DLL calibration. 354-357 - Meghanad D. Wagh, Chien-In Henry Chen:
High-level design synthesis with redundancy removal for high speed testable adders. 358-361 - Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri:
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis. 362-365 - Akihisa Yamada, Koichi Nishida, Ryoji Sakurai, Andrew Kay, Toshio Nomura, Takashi Kambe:
Hardware synthesis with the Bach system. 366-369 - J. O. Dedou, Daniel Chillet, Olivier Sentieys:
Behavioral synthesis of asynchronous systems: a methodology. 370-373 - Xiaowei Li, Paul Y. S. Cheung:
An approach to behavioral synthesis for loop-based BIST. 374-377 - Z. X. Shen, Ching-Chuen Jong:
A lower bound on general minimal resource interval scheduling with arbitrary component selection. 378-381 - M. B. Maaz, Magdy A. Bayoumi:
A non-zero clock skew scheduling algorithm for high speed clock distribution network. 382-385 - Ali M. Shatnawi, M. Omair Ahmad, M. N. S. Swamy:
Scheduling of DSP data flow graphs onto multiprocessors for maximum throughput. 386-389 - Ching-Han Tsai, Sung-Mo Kang:
Macrocell placement with temperature profile optimization. 390-393 - Frank Schmiedle, Rolf Drechsler, Bernd Becker:
Exact channel routing using symbolic representation. 394-397 - Paul Y. S. Cheung, S. K. Yeung, W. L. Ko:
A new optimization model for VLSI placement algorithms. 398-403 - Yehea I. Ismail, Eby G. Friedman:
Repeater insertion in RLC lines for minimum propagation delay. 404-407 - Xuan Zeng, J. Guan, Wenqing Zhao, Pushan Tang, Dian Zhou:
A constraint-based placement refinement method for CMOS analog cell layout. 408-411 - Markus Wolf, Ulrich Kleine:
Reliability driven module generation for analog layouts. 412-415 - Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
A cell selection strategy for low power applications. 416-419 - Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
Low power synthesis of sum-of-product computation in DSP algorithms. 420-423 - Franc Brglez, Rolf Drechsler:
Design of experiments in CAD: context and new data sets for ISCAS'99. 424-427 - Michael D. Hutton, Jonathan Rose:
Equivalence classes of clone circuits for physical-design benchmarking. 428-431 - Debabrata Ghosh, Franc Brglez:
Equivalence classes of circuit mutants for experimental design. 432-435 - Wolfgang Günther, Rolf Drechsler:
Creating hard problem instances in logic synthesis using exact minimization. 436-439 - Hemang Lavana, Franc Brglez, Robert B. Reese:
User-configurable experimental design flows on the web: the ISCAS'99 experiments. 440-443 - Matthias F. M. Stallmann, Franc Brglez, Debabrata Ghosh:
Evaluating iterative improvement heuristics for bigraph crossing minimization. 444-447 - Michael D. Hutton, Jonathan Rose:
Applications of clone circuits to issues in physical-design. 448-451 - Justin E. Harlow III, Franc Brglez:
Mirror, mirror, on the wall...is the new release any different at all? [BDDs]. 452-455 - S. J. Krolikoski, Frank Schirrmeister, B. Salefski, J. Rowson, Grant Martin:
Methodology and technology for virtual component driven hardware/software co-design on the system-level. 456-459 - P. P. Jain:
Cost-effective co-verification using RTL-accurate C models. 460-463 - G. J. Bunza:
Towards systems integration in a virtual environment: small steps, big results, and complications to come for embedded systems engineering in the next millennium. 464-467 - Graham R. Hellestrand:
Designing system on a chip products using systems engineering tools. 468-473 - Jim Kenney:
Co-verification as risk management: minimizing the risk of incorporating a new processor in your next embedded system design. 474-477 - Scott Davis, Jim Braatz, Jay Clement, Diane Honda:
Advanced instrument controller ASIC. 478-480 - Andrea Alimonda, Salvatore Carta, Luigi Raffo:
A modular digital VLSI architecture for stereo depth estimation in industrial applications. 481-484 - Gyung-Hae Han, Hwa-Young Yi, Bum-Suk Go, Dong-Geun Lee, In-Haeng Cho, Dong-Il Oh:
A new ASIC for washer controller. 485-488 - D. J. Alladi, M. L. Nagy, S. L. Gaverick:
An IC for closed-loop control of a micromotor with an electrostatically levitated rotor. 489-492 - Mohamad Rahal, Jeff Winter, John Taylor, Nick Donaldson:
Interference reduction in nerve cuff electrode recordings-a new approach. 493-496 - Jong-Nam Kim, Tae-Sun Choi:
Fast motion estimation using UESA, threshold-half-stop and adaptive partial sum scan from gradient magnitude. 497-500 - Mario Salerno, F. Sargeni, V. Bonaiuto, Sergio Taraglio, Andrea Zanela:
A dedicated hardware system for CNN stereo vision. 501-504 - Wen-Cheng Yen, Chung-Yu Wu:
A new compact neuron-bipolar cellular neural network structure with adjustable neighborhood layers and high integration level. 505-508 - Vijay K. Jain, S. Shrivastava, A. D. Snider, D. Damerow, D. Chester:
Hardware implementation of a nonlinear processor. 509-514
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