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ORCIDDATE 2003: Munich, Germany
- 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany. IEEE Computer Society 2003, ISBN 0-7695-1870-2
Volume I
Plenary: Keynote Session
- Emile H. L. Aarts, Raf Roovers:
IC Design Challenges for Ambient Intelligence. 10002-10007 - Andrea Cuomo:
Semiconductor Challenges. 10008-10009
Topic: Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts
- Menno Lindwer, Diana Marculescu, Twan Basten, Rainer Zimmermann, Radu Marculescu, Stefan Jung, Eugenio Cantatore:
Ambient Intelligence Visions and Achievements: Linking Abstract Ideas to Real-World Concepts. 10010-10017
Energy-Efficient Memory Systems
- Alberto Macii, Enrico Macii, Massimo Poncino:
Improving the Efficiency of Memory Partitioning by Address Clustering. 10018-10023 - Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon:
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. 10024-10029 - Peter Petrov, Alex Orailoglu:
Power Efficiency through Application-Specific Instruction Memory Transformations. 10030-10035 - Marcos Sánchez-Élez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida:
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. 10036-10043
Embedded Tutorial: Circuit, Platform Design and Test Challenges in Technologies Beyond 90nm
- Bill Grundmann, Rajesh Galivanche, Sandip Kundu:
Circuit and Platform Design Challenges in Technologies beyond 90nm. 10044-10049
Uncertainty
- Li-Da Huang, Hung-Ming Chen, D. F. Wong
:
Global Wire Bus Configuration with Minimum Delay Uncertainty. 10050-10055 - Hai Zhou:
Timing Verification with Crosstalk for Transparently Latched Circuits. 10056-10061 - Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula:
Statistical Timing Analysis Using Bounds. 10062-10067 - Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. 10068-10075
Hot Topic: Scaling into Ambient Intelligence
- Twan Basten, Luca Benini, Anantha P. Chandrakasan, Menno Lindwer, Jie Liu, Rex Min, Feng Zhao:
Scaling into Ambient Intelligence. 10076-10083
Power-Aware Design and Synthesis
- Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang:
Masking the Energy Behavior of DES Encryption. 10084-10089 - Dong Wu, Bashir M. Al-Hashimi, Petru Eles:
Scheduling and Mapping of Conditional Task Graphs for the Synthesis of Low Power Embedded Systems. 10090-10095 - Lih-Yih Chiou, Swarup Bhunia, Kaushik Roy:
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications. 10096-10103
Test Data Compression
- Wenjing Rao, Alex Orailoglu:
Virtual Compression through Test Vector Stitching for Scan Based Designs. 10104-10109 - Nahmsuk Oh, Rohit Kapur, Thomas W. Williams, Jim Sproch:
Test Pattern Compression Using Prelude Vectors in Fan-Out Scan Chain with Feedback Architecture. 10110-10115 - Michael J. Knieser, Francis G. Wolff, Christos A. Papachristou, Daniel J. Weyer, David R. McIntyre:
A Technique for High Ratio LZW Compression. 10116-10121 - Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski:
Fast Computation of Data Correlation Using BDDs. 10122-10129
Operating System Abstraction and Targeting (Embedded Software Forum)
- Andreas Gerstlauer, Haobo Yu, Daniel Gajski:
RTOS Modeling for System Level Design. 10130-10135 - Shaojie Wang, Sharad Malik, Reinaldo A. Bergamaschi:
Modeling and Integration of Peripheral Devices in Embedded Systems. 10136-10141 - Fernando Herrera, Hector Posadas, Pablo Sánchez, Eugenio Villar:
Systemic Embedded Software Generation from SystemC. 10142-10149
Analysis of Jitter and Noise for Analogue Systems and SD Modelling and Simulation
- Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi:
Noise Macromodel for Radio Frequency Integrated Circuits. 10150-10155 - Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney:
Approximation Approach for Timing Jitter Characterization in Circuit Simulators. 10156-10161 - Ewout Martens, Georges G. E. Gielen:
A Model of Computation for Continuous-Time ?-? Modulators. 10162-10167 - Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez:
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages. 10168-10175
Hot Topic: Securing Your Mobile Appliance: New Challenges for the System Designer
- Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater:
Securing Mobile Appliances: New Challenges for the System Designer. 10176-10183
Scheduling and Analysis of Embedded Systems
- Paul Pop, Petru Eles, Zebo Peng:
Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems. 10184-10189 - Samarjit Chakraborty, Simon Künzli, Lothar Thiele:
A General Framework for Analysing System Properties in Platform-Based Embedded System Designs. 10190-10195 - George Logothetis, Klaus Schneider:
Exact High Level WCET Analysis of Synchronous Programs by Symbolic State Space Exploration. 10196-10203 - Bernhard Rinner, Martin Schmid, Reinhold Weiss:
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures. 10204-10211
Recent Advances in DFT and BIST
- Muhammad Nummer, Manoj Sachdev:
DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers. 10212-10217 - Nisar Ahmed, Mohammad H. Tehranipour, Mehrdad Nourani:
Extending JTAG for Testing Signal Integrity in SoCs. 10218-10223 - Dhiraj K. Pradhan, Chunsheng Liu, Krishnendu Chakrabarty:
EBIST: A Novel Test Generator with Built-In Fault Detection Capability. 10224-10229 - Chunsheng Liu, Krishnendu Chakrabarty:
A Partition-Based Approach for Identifying Failing Scan Cells in Scan-BIST with Applications to System-on-Chip Fault Diagnosis. 10230-10237
Analogue and RF Modelling, Simulation and Optimisation
- Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors. 10238-10243 - Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney:
A New Simulation Technique for Periodic Small-Signal Analysis. 10244-10249 - Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Generalized Posynomial Performance Modeling. 10250-10255 - Bart De Smedt, Georges G. E. Gielen:
HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. 10256-10263
Architectural Level Synthesis
- María C. Molina, José M. Mendías, Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage. 10264-10269 - Sumit Gupta, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Dynamic Conditional Branch Balancing during the High-Level Synthesis of Control-Intensive Designs. 10270-10275 - Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya:
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. 10276-10281 - Kyeong Keol Ryu, Vincent John Mooney:
Automated Bus Generation for Multiprocessor SoC Design. 10282-10289
Scheduling in Reconfigurable Computing
- Herbert Walder, Marco Platzner:
Online Scheduling for Block-Partitioned Reconfigurable Devices . 10290-10295 - Bingfeng Mei, Serge Vernalde, Diederik Verkest, Hugo De Man, Rudy Lauwereins:
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. 10296-10301 - Sebastian Lange, Udo Kebschull:
Virtual Hardware Byte Code as a Design Platform for Reconfigurable Embedded Systems. 10302-10309
Delay Testing and Diagnosis
- Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara:
A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. 10310-10315 - Manan Syal, Michael S. Hsiao:
A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification. 10316-10321 - Saravanan Padmanaban, Spyros Tragoudas:
Non-Enumerative Path Delay Fault Diagnosis . 10322-10327 - Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir:
Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. 10328-10335
Embedded Tutorial: Embedded Operating Systems for SoC (Embedded Software Forum)
- Sungjoo Yoo, Ahmed Amine Jerraya:
Introduction to Hardware Abstraction Layers for SoC. 10336-10337 - Vincent John Mooney:
Hardware/Software Partitioning of Operating Systems. 10338-10339 - Michel Sarlotte, Bernard Candaele, Jérôme Quévremont, D. Merel:
Embedded Software in Digital AM-FM Chipset. 10340-10343
Networks-on-Chip
- Terry Tao Ye, Luca Benini, Giovanni De Micheli:
Packetized On-Chip Interconnect Communication Analysis for MPSoC. 10344-10349 - Edwin Rijpkema, Kees G. W. Goossens, Andrei Radulescu, John Dielissen, Jef L. van Meerbergen, Paul Wielage, Erwin Waterlander:
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. 10350-10355 - Frank Gilbert, Michael J. Thul, Norbert Wehn:
Communication Centric Architectures for Turbo-Decoding on Embedded Multiprocessors . 10356-10363
System Level Modelling
- Ingo Sander, Axel Jantsch, Zhonghai Lu:
Development and Application of Design Transformations in ForSyDe. 10364-10369 - Satnam Singh:
System Level Specification in Lava. 10370-10375 - Ashraf Salem:
Formal Semantics of Synchronous SystemC. 10376-10381 - Frederic Doucet, Sandeep K. Shukla, Rajesh K. Gupta:
Introspection in System-Level Language Frameworks: Meta-Level vs. Integrated. 10382-10387 - Alain Vachoux, Christoph Grimm, Karsten Einwich:
SystemC-AMS Requirements, Design Objectives and Rationale. 10388-10395
Hot Topic: Runtime Reconfigurable Systems on Chip - An Industry Perspective
- Kees A. Vissers:
Parallel Processing Architectures for Reconfigurable Systems. 10396-10397 - Bhusan Gupta, Michele Borgatti:
Different Approaches to Add Reconfigurability in a SoC Architecture. 10398 - Brandon Blodget, Scott McMillan, Patrick Lysaght:
A Lightweight Approach for Embedded Reconfiguration of FPGAs. 10399-10401
Hot Topic: Creating Value Through Test
- Erik Jan Marinissen, Bart Vermeulen, Robert Madge, Michael Kessler, Michael Müller:
Creating Value Through Test. 10402-10409
Software Optimisation for Embedded Systems (Embedded Software Forum
- Heiko Falk, Peter Marwedel:
Control Flow Driven Splitting of Loop Nests at the Source Code Level . 10410-10415 - Mahmut T. Kandemir, Guangyu Chen, Wei Zhang, Ibrahim Kolcu:
Data Space Oriented Scheduling in Embedded Systems. 10416-10421 - Satish Pillai, Margarida F. Jacome:
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling. 10422-10427 - Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev:
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. 10428-10435
Global Approaches to Layout Synthesis
- Jurjen Westra, Dirk-Jan Jongeneel, Ralph H. J. M. Otten, Chandu Visweswariah:
Time Budgeting in a Wireplanning Context. 10436-10441 - Ruibing Lu, Cheng-Kok Koh:
Interconnect Planning with Local Area Constrained Retiming. 10442-10447 - Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu:
A Novel Metric for Interconnect Architecture Performance. 10448-10455
Platform Design and IP Reuse Methods
- Jianwen Zhu, Wai Sum Mong:
Specification of Non-Functional Intellectual Property Components. 10456-10461 - Yuan Xie, Wayne H. Wolf, Haris Lekatsas:
Profile-Driven Selective Code Compression. 10462-10467 - Chengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi:
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. 10468-10475
Panel: Reconfigurable Computing - Different Perspectives
- Wolfgang Rosenstiel, Rudy Lauwereins, Ivo Bolsens, Chris Rowen, Yankin Tanurhan, Kees A. Vissers, S. Wang:
Panel Title: Reconfigurable Computing - Different Perspectives. 10476-10477
Analogue and Defect-Oriented Testing
- Doris Lupea, Udo Pursche, Hans-Joachim Jentschel:
RF-BIST: Loopback Spectral Signature Analysis. 10478-10483 - Zaid Al-Ars, Ad J. van de Goor, Jens Braun, Detlev Richter:
Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. 10484-10489 - Sujit T. Zachariah, Yi-Shing Chang, Sandip Kundu, Chandra Tirumurti:
On Modeling Cross-Talk Faults. 10490-10495 - Martin John Burbidge, Jim Tijou, Andrew Richardson:
Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops. 10496-10503
Energy Aware Software Techniques (Embedded Software Forum)
- Venkata Syam P. Rapaka, Diana Marculescu:
Pre-Characterization Free, Efficient Power/Performance Analysis of Embedded and General Purpose Software Applications. 10504-10509 - Mahmut T. Kandemir, Wei Zhang, Mustafa Karaköy:
Runtime Code Parallelization for On-Chip Multiprocessors. 10510-10515 - Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal:
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. 10516-10523
Interconnect Modelling and Signal Integrity
- Ferran Martorell, Diego Mateo, Xavier Aragonès:
Modeling and Evaluation of Substrate Noise Induced by Interconnects. 10524-10529 - Makram M. Mansour, Amit Mehrotra:
Model-Order Reduction Based on PRONY's Method. 10530-10535 - Stefano Grivet-Talocia, Igor S. Stievano, Ivan A. Maio, Flavio G. Canavero:
Combined FDTD/Macromodel Simulation of Interconnected Digital Devices. 10536-10541 - Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne H. Wolf:
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses. 10542-10549
System Level Simulation
- Sungjoo Yoo, Iuliana Bacivarov, Aimen Bouchhima, Yanick Paviot, Ahmed Amine Jerraya:
Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer. 10550-10555 - Wei Qin, Sharad Malik:
Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. 10556-10561 - Jürgen Schnerr, Gunter Haug, Wolfgang Rosenstiel:
Instruction Set Emulation for Rapid Prototyping of SoCs . 10562-10569
Design Space Exploration for Reconfigurable Computing
- Alberto La Rosa, Luciano Lavagno, Claudio Passerone:
Hardware/Software Design Space Exploration for a Reconfigurable Processor. 10570-10575 - João M. P. Cardoso, Markus Weinhardt:
From C Programs to the Configure-Execute Model. 10576-10581 - Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca:
FPGA-Based Implementation of a Serial RSA Processor. 10582-10589
On-Line Testing and Self-Repair
- Michael Nicolaidis, Nadir Achouri, Slimane Boutobza:
Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair. 10590-10595 - Petros Oikonomakos, Mark Zwolinski, Bashir M. Al-Hashimi:
Versatile High-Level Synthesis of Self-Checking Datapaths Using an On-Line Testability Metric. 10596-10601 - Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. 10602-10607 - Martin Omaña, Daniele Rossi, Cecilia Metra:
High Speed and Highly Testable Parallel Two-Rail Code Checker. 10608-10615
Hot Topic: Safe Automotive Software Development (Embedded Software Forum)
- Ken Tindell, Hermann Kopetz, Fabian Wolf, Rolf Ernst:
Safe Automotive Software Development. 10616-10623
Mixed-Signal Design Techniques
- Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay:
Analysis and White-Box Modeling of Weakly Nonlinear Time-Varying Circuits. 10624-10629 - Carsten Wegener, Michael Peter Kennedy:
Linear Model-Based Error Identification and Calibration for Data Converters. 10630-10635 - Miquel Albiol, José Luis González, Eduard Alarcón:
Improved Design Methodology for High-Speed High-Accuracy Current Steering D/A Converters. 10636-10641 - Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man:
Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. 10642-10649
Design Space Exploration
- Arijit Ghosh, Tony Givargis:
Analytical Design Space Exploration of Caches for Embedded Systems. 10650-10655 - Vladimir D. Zivkovic, Erwin A. de Kock, Pieter van der Wolf, Ed F. Deprettere:
Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. 10656-10661 - Laura Vanzago, Bishnupriya Bhattacharya, Joel Cambonie, Luciano Lavagno:
Design Space Exploration for a Wireless Protocol on a Reconfigurable Platform. 10662-10667 - William Fornaciari, P. Micheli, Fabio Salice, L. Zampella:
A First Step Towards Hw/Sw Partitioning of UML Specifications. 10668-10673 - Yannick Le Moullec, Nahla Ben Amor, Jean-Philippe Diguet, Mohamed Abid, Jean Luc Philippe:
Multi-Granularity Metrics for the Era of Strongly Personalized SOCs. 10674-10681
Low Power Architectures
- Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Energy Estimation for Extensible Processors. 10682-10687 - Jingcao Hu, Radu Marculescu:
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. 10688-10693 - Wei-Chung Cheng, Massoud Pedram:
Chromatic Encoding: A Low Power Encoding Technique for Digital Visual Interface. 10694-10699 - Hunsoo Choo, Khurram Muhammad, Kaushik Roy:
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters. 10700-10705 - Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi:
Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. 10706-10713
System-on-Chip Testing
- Nektarios Kranitis, George Xenoulis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian:
Low-Cost Software-Based Self-Testing of RISC Processor Cores. 10714-10719