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ORCIDDATE 2023: Antwerp, Belgium
- Design, Automation & Test in Europe Conference & Exhibition, DATE 2023, Antwerp, Belgium, April 17-19, 2023. IEEE 2023, ISBN 978-3-9819263-7-8
- Jianan Xu, Wenjie Fan, Jan Madsen
, Georgi Plamenov Tanev, Luca Pezzarossa:
AI-Based Detection of Droplets and Bubbles in Digital Microfluidic Biochips. 1-6 - Yichen Jiang, Shuo Wang, Renato Figueiredo, Yier Jin:
Warm-Boot Attack on Modern DRAMs. 1-2 - Jiaxi Zhang, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo:
Rethinking NPN Classification from Face and Point Characteristics of Boolean Functions. 1-6 - Alexander Schulz-Rosengarten, Reinhard von Hanxleden, Marten Lohstroh, Soroush Bateni, Edward A. Lee:
Polyglot Modal Models through Lingua Franca. 1-2 - Haibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
Split Additive Manufacturing for Printed Neuromorphic Circuits. 1-6 - Youngchang Choi, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang:
MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors. 1-5 - Yixian Shen, Sobhan Niknam, Anuj Pathania, Andy D. Pimentel:
Thermal Management for S-NUCA Many-Cores via Synchronous Thread Rotations. 1-6 - Tom Glint, Chandan Kumar Jha, Manu Awasthi, Joycee Mekie:
Analysis of Quantization Across DNN Accelerator Architecture Paradigms. 1-2 - Weihong Xu, Jaeyoung Kang, Tajana Rosing:
FSL-HD: Accelerating Few-Shot Learning on ReRAM using Hyperdimensional Computing. 1-6 - Lin Chen, Xiao Li, Fan Jiang, Chengeng Li, Jiang Xu:
Smart Knowledge Transfer-based Runtime Power Management. 1-6 - Biresh Kumar Joardar, Krishnendu Chakrabarty:
Attacking ReRAM-based Architectures using Repeated Writes. 1-6 - Alexander Kamkin, Mikhail M. Chupilko, Mikhail Lebedev, Sergey A. Smolov, Georgi Gaydadjiev:
High-Level Synthesis versus Hardware Construction. 1-6 - Luca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo:
Using High-Level Synthesis to model System Verilog procedural timing controls. 1-6 - Ying Yuan, Zhipeng Tan, Shitong Wei, Lihua Yang, Wenjie Qi, Xuanzhi Wang, Cong Liu:
TPP: Accelerate Application Launch via Two-Phase Prefetching on Smartphone. 1-6 - Samuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini:
MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. 1-2 - Unmesh D. Bordoloi, Samarjit Chakraborty, Markus Jochim, Prachi Joshi, Arvind Raghuraman, S. Ramesh:
Autonomy-driven Emerging Directions in Software-defined Vehicles. 1-6 - Christian Fibich, Martin Horauer, Roman Obermaisser:
Bitstream- Level Interconnect Fault Characterization for SRAM-based FPGAs. 1-2 - Hao-Jan Huang, Wen Sheng Lim, Chia-Heng Tu, Chun-Feng Wu, Yuan-Hao Chang:
Data Freshness Optimization on Networked Intermittent Systems. 1-6 - Christodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos:
ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining. 1-6 - Biswadeep Chakraborty, Uday Kamal, Xueyuan She, Saurabh Dash, Saibal Mukhopadhyay:
Brain-Inspired Spatiotemporal Processing Algorithms for Efficient Event-Based Perception. 1-6 - Samuel Isuwa, David Amos, Amit Kumar Singh, Bashir M. Al-Hashimi, Geoff V. Merrett:
Content- and Lighting-Aware Adaptive Brightness Scaling for Improved Mobile User Experience. 1-2 - Seyed Ahmad Mirsalari, Giuseppe Tagliavini, Davide Rossi, Luca Benini:
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes. 1-2 - Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, M. E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr:
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. 1-6 - Dilip S. V. Kumar, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede:
Low-Cost First-Order Secure Boolean Masking in Glitchy Hardware. 1-2 - Nadia Ibellaatti, Edouard Lepape, Alp Kiliç, Kaya Akyel, Kassem Chouayakh, Fabrizio Ferrandi, Claudio Barone, Serena Curzel, Michele Fiorito, Giovanni Gozzi, Miguel Masmano, Ana Risquez Navarro, Manuel Muñoz, Vicente Nicolau Gallego, Patricia López Cueva, Jean-noel Letrillard, Franck Wartel:
HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystem. 1-5 - Ke Liu, Hua Wang, Ke Zhou, Cong Li:
A Lightweight and Adaptive Cache Allocation Scheme for Content Delivery Networks. 1-6 - Michael T. Niemier, Xiaobo Sharon Hu, Liu Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan, Daniel C. Ralph:
Cross Layer Design for the Predictive Assessment of Technology-Enabled Architectures. 1-10 - Federico Cunico, Luigi Capogrosso, Alberto Castellini, Francesco Setti, Patrik Pluchino, Filippo Zordan, Valeria Santus, Anna Spagnolli, Stefano Cordibella, Giambattista Gennari, Mauro Borgo, Alberto Sozza, Stefano Troiano, Roberto Flor, Andrea Zanella, Alessandro Farinelli, Luciano Gamberini, Marco Cristani:
The Post-pandemic Effects on IoT for Safety: The Safe Place Project. 1-4 - Md. Imtiaz Rashid, Benjamin Carrion Schafer:
MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR. 1-6 - Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal:
PetaOps/W edge-AI $\mu$ Processors: Myth or reality? 1-6 - Aibin Yan, Zhen Zhou, Liang Ding, Jie Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard:
High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS Technology. 1-2 - Apurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen:
Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric. 1-2 - Shruti Yadav Narayana, Sumit K. Mandal, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras:
A Lightweight Congestion Control Technique for NoCs with Deflection Routing. 1-2 - Mahendra Rathor, Vishesh Mishra, Urbi Chatterjee:
Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers. 1-6 - Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi:
A Novel Delay Calibration Method Considering Interaction between Cells and Wires. 1-6 - Xingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao, Leibin Ni, Weikang Qian:
High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup Table. 1-6 - Kshitij Bhardwaj, Zishen Wan, Arijit Raychowdhury, Ryan A. Goldhahn:
Real-Time Fully Unsupervised Domain Adaptation for Lane Detection in Autonomous Driving. 1-2 - Yuming Liu, Angel Yanguas-Gil, Sandeep Madireddy, Yanjing Li:
Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Device and Circuit Behaviors. 1-6 - Sandeep Kumar, Abhisek Panda, Smruti R. Sarangi:
Perspector: Benchmarking Benchmark Suites. 1-6 - Yifan Zhang, Qiang Cao, Jie Yao, Hong Jiang:
R-LDPC: Refining Behavior Descriptions in HLS to Implement High-throughput LDPC Decoder. 1-6 - Yixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang, Ru Huang:
Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. 1-6 - Wenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li, Ulf Schlichtmann:
SteppingNet: A Stepping Neural Network with Incremental Accuracy Enhancement. 1-6 - Sai Usha Nagasri Goparaju, L. Lakshmanan, Abhinav Navnit, Rahul Biju, Lovish B, Deepak Gangadharan, Aftab M. Hussain:
Time Series-based Driving Event Recognition for Two Wheelers. 1-2 - Yuanchen Qu, Yu Ma, Pingqiang Zhou:
A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators. 1-6 - Sung-Yun Lee, Seonghyeon Park, Daeyeon Kim, Minjae Kim, Tuyen Pham Le, Seokhyeong Kang:
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. 1-6 - Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola:
Exploiting assertions mining and fault analysis to guide RTL-level approximation. 1-2 - Chang Meng, Jiajun Sun, Yuqi Mai, Weikang Qian:
MECALS: A Maximum Error Checking Technique for Approximate Logic Synthesis. 1-6 - Fan Yang, Chengqi Xiao, Jun Li, Zhibing Sha, Zhigang Cai, Jianwei Liao:
Out-of-channel data placement for balancing wear-out and I/O workloads in RAID-enabled SSDs. 1-6 - Xabier Iturbe, Nassim Abderrahmane, Jaume Abella, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov:
NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips. 1-6 - Ourania Spantidi, Iraklis Anagnostopoulos:
Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints. 1-6 - Chengcheng Tang, Jie Han:
Hardware Efficient Weight-Binarized Spiking Neural Networks. 1-6 - Shanquan Tian, Shayan Moini, Daniel E. Holcomb, Russell Tessier, Jakub Szefer:
A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs. 1-6 - Shiqing Li, Weichen Liu:
Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches. 1-6 - Yaoxing Chang, Petar Jokic, Stéphane Emery, Luca Benini:
An Ultra-Low-Power Serial Implementation for Sigmoid and Tanh Using CORDIC Algorithm. 1-2 - Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch, Hans-Joachim Wunderlich:
Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection. 1-2 - Akshay Karkal Kamath, Stefan Abi-Karam, Ashwin Bhat, Cong Hao:
M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search. 1-6 - You Li, Guannan Zhao, Yunqi He, Hai Zhou:
ObfusLock: An Efficient Obfuscated Locking Framework for Circuit IP Protection†. 1-6 - Chathura Rajapaksha, Leila Delshadtehrani, Manuel Egele, Ajay Joshi:
SIGFuzz: A Framework for Discovering Microarchitectural Timing Side Channels. 1-6 - David van Son, Floran de Putter, Sebastian Vogel, Henk Corporaal:
BOMP- NAS: Bayesian Optimization Mixed Precision NAS. 1-2 - Ziyue Zheng, Yangdi Lyu:
STSearch: State Tracing-based Search Heuristics for RTL Validation. 1-6 - Chaitali Sathe, Yiorgos Makris, Benjamin Carrion Schafer:
MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitS. 1-6 - Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon:
Securing a RISC-V architecture: A dynamic approach. 1-5 - Fangxin Liu, Wenbo Zhao, Zongwu Wang, Xiaokang Yang, Li Jiang:
SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN Acceleration. 1-2 - Daeyeon Kim, Jakang Lee, Seokhyeong Kang:
Routability Prediction using Deep Hierarchical Classification and Regression. 1-2 - Wenlu Xue, Jinyu Bai, Sifan Sun, Wang Kang:
Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement. 1-6 - Zejian Liu, Kun Zhao, Jian Cheng:
TBERT: Dynamic BERT Inference with Top-k Based Predictors. 1-6 - Gia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer:
ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. 1-6 - Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic:
Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs. 1-6 - Dimitris Theodoropoulos, Olivier Michel, Pavlos Malakonakis, Konstantinos Georgopoulos, Giovanni Isotton, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Gino Perna, Marisa Zanotti, Panagiotis Miliadis, Panagiotis Mpakos, Chloe Alverti, Aggelos Ioannou, Max Engelen, Albert Njoroge Kahira, Iakovos Mavroidis:
Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project Intermediate stage. 1-4 - Jingdian Ming, Yongbin Zhou, Wei Cheng, Huizhong Li:
Table Re-Computation Based Low Entropy Inner Product Masking Scheme. 1-6 - Lingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron, Mircea R. Stan, Ashish Venkat:
Hardware Trojans in eNVM Neuromorphic Devices. 1-6 - Sandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu:
A Novel Fault-Tolerant Architecture for Tiled Matrix Multiplication. 1-6 - Zhuanhao Wu, Marat Bekmyrza, Nachiket Kapre, Hiren D. Patel:
Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems. 1-6 - Zachery Utt, Daniel Volya, Prabhat Mishra:
Quantum Measurement Discrimination using Cumulative Distribution Functions. 1-6 - Songran Liu, Mingsong Lv, Wei Zhang, Xu Jiang, Chuancai Gu, Tao Yang, Wang Yi, Nan Guan:
Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT Devices. 1-6 - Van-Phu Ha, Olivier Sentieys:
Maximizing Computing Accuracy on Resource-Constrained Architectures. 1-6 - Sayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian, Mohammad Moshiur Rahman:
Analog Coverage-driven Selection of Simulation Corners for AMS Integrated Circuits. 1-6 - Qisheng Jiang, Lei Jia, Chundong Wang:
Atomic but Lazy Updating with Memory-mapped Files for Persistent Memory. 1-6 - Yujin Zheng, Alex Bystrov, Alex Yakovlev:
A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power Gating. 1-2 - Tianyu Fu, Chiyue Wei, Zhenhua Zhu, Shang Yang, Zhongming Yu, Guohao Dai, Huazhong Yang, Yu Wang:
CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable Memory. 1-6 - Annachiara Ruospo, Gabriele Gavarini, Corrado De Sio, J. Guerrero, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez, Riccardo Mariani, J. Aribido, Jyotika Athavale:
Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections. 1-6 - Ayesha Siddique, Khaza Anuarul Hoque:
Improving Reliability of Spiking Neural Networks through Fault Aware Threshold Voltage Optimization. 1-6 - Dwaipayan Choudhury, Ananth Kalyanaraman, Partha Pande:
GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing. 1-6 - Jina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee:
Developing an Ultra-low Power RISC-V Processor for Anomaly Detection. 1-2 - Dina A. Moussa, Michael Hefenbrock, Mehdi B. Tahoori:
Compact Test Pattern Generation For Multiple Faults In Deep Neural Networks. 1-2 - Nora Sperling, Alex Bendrick, Dominik Stöhrmann, Rolf Ernst, Bryan Donyanavard, Florian Maurer, Oliver Lenke, Anmol Surhonne, Andreas Herkersdorf, Walaa Amer, Caio Batista de Melo, Ping-Xiang Chen, Quang Anh Hoang, Rachid Karami, Biswadip Maity, Paul Nikolian, Mariam Rakka, Dongjoo Seo, Saehanseul Yi, Minjun Seo, Nikil D. Dutt, Fadi J. Kurdahi:
Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative Systems. 1-6 - Mahta Mayahinia, Hsiao-Hsuan Liu, Subrat Mishra, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori:
Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes. 1-6 - Huimin Li, Nele Mentens, Stjepan Picek:
Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions. 1-6 - Chao Lu, Christian Pilato, Kanad Basu:
Towards High-Level Synthesis of Quantum Circuits. 1-6 - Simeng Zheng, Chih-Hui Ho, Wenyu Peng, Paul H. Siegel:
Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets. 1-6 - Shashwat Khandelwal, Anneliese Walsh, Shanker Shreejith:
Quantised Neural Network Accelerators for Low-Power IDS in Automotive Networks. 1-2 - Ting-Yu Yeh, Yueh Cho, Yung-Chih Chen:
An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification. 1-6 - Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Yisong Chang, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou Shan:
MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior. 1-6 - Wenhui Ou, Zhuoyu Wu, Zheng Wang, Chao Chen, Yongkui Yang:
COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions. 1-6 - Mohammed Nabeel, Deepraj Soni, Mohammed Ashraf, Mizan Abraha Gebremichael, Homer Gamil, Eduardo Chielle, Ramesh Karri, Mihai Sanduleanu, Michail Maniatakos:
CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution. 1-2 - René Griessl, Florian Porrmann, Nils Kucza, Kevin Mika, Jens Hagemeyer, Martin Kaiser, Mario Porrmann, Marco Tassemeier, Marcel Flottmann, Fareed Qararyah, Muhammad Waqar Azhar, Pedro Trancoso, Daniel Ödman, Karol Gugala, Grzegorz Latosinski:
Evaluation of heterogeneous AIoT Accelerators within VEDLIoT. 1-6 - Thomas Dalgaty, Thomas Mesquida, Damien Joubert, Amos Sironi, Cyrille Soubeyrat, Pascal Vivet, Christoph Posch:
The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural Networks. 1-6 - Muhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor:
SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing. 1-6 - Fikret Basic, Christian Steger, Robert Kofler:
Establishing Dynamic Secure Sessions for ECQV Implicit Certificates in Embedded Systems. 1-6 - Bernhard Lippmann, Joel Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, Michaela Brunner, Tim Music, Michael Pehl, Tauseef Siddiqui, Ralf Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, Maurits Ortmanns, Robert Hesselbarth, Matthias Hiller:
VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting Implementations. 1-6 - Katharina Ruep, Daniel Große:
Improving Design Understanding of Processors leveraging Datapath Clustering. 1-2 - Masoomeh Karami, Sajad Shahsavari, Eero Immonen, M. Hashem Haghbayan, Juha Plosila:
A Coupled Battery State-of-Charge and Voltage Model for Optimal Control Applications. 1-2 - Anika Christmann, Robin Hapka, Rolf Ernst:
Formal Analysis of Timing Diversity for Autonomous Systems. 1-6 - Marcello Traiola, Angeliki Kritikakou, Olivier Sentieys:
A machine-learning-guided framework for fault-tolerant DNNs. 1-2 - Thilo L. Fischer, Heiko Falk:
WCET Analysis of Shared Caches in Multi -Core Architectures using Event-Arrival Curves. 1-2 - Ludovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer, Sergio A. Pertuz, Lester Kalms, Cornelia Wulf, Najdet Charaf, Luca Sterpone, Sarah Azimi, Daniele Rizzieri, Salvatore Gabriele La Greca, David Merodio Codinachs, Stephen King:
EuFRATE: European FPGA Radiation-hardened Architecture for Telecommunications. 1-6 - Pascal Nasahl, Martin Unterguggenberger, Rishub Nagpal, Robert Schilling, David Schrammel, Stefan Mangard:
SCFI: State Machine Control-Flow Hardening Against Fault Attacks. 1-6