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ORCIDVladimir Herdt
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2020 – today
- 2023
[j10]Sören Tempel
, Vladimir Herdt, Rolf Drechsler:
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. 10(11): 9544-9555 (2023)- [c54]Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Processor Verification using Symbolic Execution: A RISC-V Case-Study. DATE 2023: 1-6 - [c53]Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. FDL 2023: 1-8 - [c52]Tim Meywerk, Vladimir Herdt, Rolf Drechsler:
Coverage-Guided Fuzzing for Plan-Based Robotics. ICAART (2) 2023: 106-114 - [d3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. Zenodo, 2023
- 2022
- [j9]Vladimir Herdt, Rolf Drechsler:
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. 65(1) (2022) - [j8]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. 14(4): 195-198 (2022) - [j7]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. 126: 102456 (2022) - [j6]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. 133: 102757 (2022) - [c51]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC 2022: 160-165 - [c50]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA 2022: 77-82 - [c49]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC 2022: 1177-1182 - [c48]Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz:
The Scale4Edge RISC-V Ecosystem. DATE 2022: 808-813 - [c47]Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler:
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. DATE 2022: 1123-1126 - [c46]Milan Funck, Vladimir Herdt, Rolf Drechsler:
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. DDECS 2022: 14-19 - [c45]Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier:
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. DSD 2022: 134-141 - [c44]Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. FDL 2022: 1-8 - [c43]Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler:
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. FDL 2022: 1-6 - [c42]Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler:
3D Visualization of Symbolic Execution Traces. FDL 2022: 1-8 - [c41]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI 2022: 97-103 - [c40]Pascal Pieper, Vladimir Herdt, Rolf Drechsler:
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. ACM Great Lakes Symposium on VLSI 2022: 193-197 - [c39]Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt, Rolf Drechsler:
Simulation-Based Debugging of Formal Environment Models. MED 2022: 890-895 - [d2]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. Zenodo, 2022 - 2021
- [j5]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. 13(4): 202-205 (2021) - [j4]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116: 102135 (2021) - [c38]Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler:
Mutation-based Compliance Testing for RISC-V. ASP-DAC 2021: 55-60 - [c37]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. DAC 2021: 667-672 - [c36]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. DATE 2021: 218-221 - [c35]Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar:
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE 2021: 1905-1914 - [c34]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. FDL 2021: 1-7 - [c33]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. FDL 2021: 1-7 - [c32]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. MBMV 2021: 1-8 - [c31]Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC 2021: 1-6 - [d1]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. Zenodo, 2021 - 2020
- [j3]Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler:
RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. 109: 101756 (2020) - [c30]Vladimir Herdt, Daniel Große, Rolf Drechsler:
RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA 2020: 543-549 - [c29]Vladimir Herdt, Daniel Große, Rolf Drechsler:
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*. DAC 2020: 1-6 - [c28]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC 2020: 1-6 - [c27]Vladimir Herdt, Daniel Große, Rolf Drechsler:
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*. DATE 2020: 618-621 - [c26]Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards Specification and Testing of RISC-V ISA Compliance⋆. DATE 2020: 995-998 - [c25]Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler:
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL 2020: 1-7 - [c24]Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler:
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI 2020: 101-106 - [c23]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD 2020: 312-315 - [c22]Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler:
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) 2020: 326-347 - [c21]Vladimir Herdt, Rolf Drechsler:
Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow. ISVLSI 2020: 182-187 - [p1]Vladimir Herdt:
Verbessertes Virtual Prototyping für den Entwurfsablauf. Ausgezeichnete Informatikdissertationen 2020: 119-128
2010 – 2019
- 2019
- [b2]Vladimir Herdt:
Efficient modeling, verification and analysis techniques to enhance the virtual prototype based design flow for embedded systems. University of Bremen, Germany, 2019, pp. 1-286 - [j2]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. 21(5): 545-565 (2019) - [j1]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1359-1372 (2019) - [c20]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Maximizing power state cross coverage in firmware-based power management. ASP-DAC 2019: 335-340 - [c19]Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler:
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC 2019: 188 - [c18]Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler:
Verifying Instruction Set Simulators using Coverage-guided Fuzzing*. DATE 2019: 360-365 - [c17]Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD 2019: 129-136 - [c16]Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz:
Systematic RISC-V based Firmware Design⋆. FDL 2019: 1-8 - 2018
- [c15]Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Resilience evaluation via symbolic fault injection on intermediate code. DATE 2018: 845-850 - [c14]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards fully automated TLM-to-RTL property refinement. DATE 2018: 1508-1511 - [c13]Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler:
Extensible and Configurable RISC-V Based Virtual Prototype. FDL 2018: 5-16 - [c12]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards Automated Refinement of TLM Properties to RTL. MBMV 2018 - 2017
- [c11]Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler:
Data flow testing for virtual prototypes. DATE 2017: 380-385 - [c10]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL 2017: 1-8 - [c9]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) 2017: 25-44 - [c8]Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Early SoC security validation by VP-based static information flow analysis. ICCAD 2017: 400-407 - 2016
- [b1]Vladimir Herdt:
Complete Symbolic Simulation of SystemC Models - Efficient Formal Verification of Finite Non-Terminating Programs. BestMasters, Springer 2016, ISBN 978-3-658-12679-7, pp. 1-115 - [c7]Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler:
ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. CAV (2) 2016: 177-183 - [c6]Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards formal verification of real-world SystemC TLM peripheral models - a case study. DATE 2016: 1160-1163 - [c5]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. FDL 2016: 1-8 - [c4]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Compiled symbolic simulation for systemC. ICCAD 2016: 52 - 2015
- [c3]Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler:
Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. ATVA 2015: 228-233 - [c2]Vladimir Herdt, Hoang Minh Le, Rolf Drechsler:
Verifying SystemC using stateful symbolic simulation. DAC 2015: 49:1-49:6 - 2013
- [c1]Hoang Minh Le, Daniel Große, Vladimir Herdt, Rolf Drechsler:
Verifying SystemC using an intermediate verification language and symbolic simulation. DAC 2013: 116:1-116:6
Coauthor Index
aka: Hoang M. Le
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