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2020 – today
- 2020
[c21]Vijay Deep Bhatt, Wolfgang Ecker, Volkan Esen, Zhao Han, Daniela Sanchez Lopera
, Rituj Patel, Lorenzo Servadei, Sahil Singla, Sven Wenzek, Vijaydeep Yadav, Elena Zennaro:
SoC Design Automation with ML - It's Time for Research. MLCAD 2020: 35-36- [c20]Lorenzo Servadei, Jiapeng Zheng, Jose A. Arjona-Medina, Michael Werner, Volkan Esen, Sepp Hochreiter, Wolfgang Ecker, Robert Wille:
Cost Optimization at Early Stages of Design Using Deep Reinforcement Learning. MLCAD 2020: 37-42
2010 – 2019
- 2016
- [c19]Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker:
Automatically comparing analog behavior using Earth Mover's Distance. VLSI-SoC 2016: 1-8 - [c18]Alexander W. Rath, Sebastian Simon, Volkan Esen, Wolfgang Ecker:
Earth Mover's Distance as a Comparison Metric for Analog Behavior. VLSI-SoC (Selected Papers) 2016: 173-191 - 2014
- [c17]Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
A transaction-oriented UVM-based library for verification of analog behavior. ASP-DAC 2014: 806-811 - 2013
- [c16]Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
Comparison of analog transactions using statistics. ISSoC 2013: 1-6 - 2012
- [c15]Wolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu:
SystemC as completing pillar in industrial OVM based verification environments. CODES+ISSS 2012: 307-312 - [c14]Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen:
The system verification methodology for advanced TLM verification. CODES+ISSS 2012: 313-322 - 2011
- [c13]Allan Crone, Oliver Bringmann, C. Chevallaz, B. Dickman, Volkan Esen, M. Rohleder:
State of the art verification methodologies in 2015. DATE 2011: 1339 - [c12]Alexander W. Rath, Volkan Esen, Wolfgang Ecker:
Analog transaction level modeling. HLDVT 2011: 82 - 2010
- [c11]Wolfgang Ecker, Volkan Esen, Robert Schwencker, Thomas Steininger, Michael Velten:
TLM+ modeling of embedded HW/SW systems. DATE 2010: 75-80 - [c10]Wolfgang Ecker, Volkan Esen, Rainer Findenig, Thomas Steininger, Michael Velten:
Model reduction techniques for the formal verification of hardware dependent software. HLDVT 2010: 148-153
2000 – 2009
- 2008
- [b1]Volkan Esen:
A new assertion language covering multiple levels of abstraction. Technical University Munich, Germany, 2008, pp. 1-212 - 2007
- [c9]Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull:
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. DATE 2007: 767-772 - [c8]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Interactive presentation: Implementation of a transaction level assertion framework in SystemC. DATE 2007: 894-899 - [c7]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertion Refinement. IESS 2007: 1-14 - 2006
- [c6]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten:
Case Study on Transaction Level Modeling. FDL 2006: 209-215 - [c5]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Jacob Smit:
IP Library For Temporal SystemC Assertions. FDL 2006: 301-309 - [c4]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Michael Velten, Michael Hull:
Specification Language for Transaction Level Assertions. HLDVT 2006: 77-84 - [c3]Wolfgang Ecker, Volkan Esen, Michael Hull, Thomas Steininger, Michael Velten:
Requirements and Concepts for Transaction Level Assertions. ICCD 2006: 286-293 - [c2]Wolfgang Ecker, Volkan Esen, Michael Hull:
Execution semantics and formalisms for multi-abstraction TLM assertions. MEMOCODE 2006: 93-102 - 2004
- [c1]Wolfgang Ecker, Volkan Esen, Thomas Steininger, Martin Zambaldi:
Memory Models for the Formal Verification of Assembler Code Using Bounded Model Checking. ISORC 2004: 129-135
Coauthor Index
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