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ORCIDDATE 2025: Lyon, France
- Design, Automation & Test in Europe Conference, DATE 2025, Lyon, France, March 31 - April 2, 2025. IEEE 2025, ISBN 978-3-9826741-0-0
Reconfigurable Systems
- Fuyu Wang, Minghua Shen:
Poros: One-Level Architecture-Mapping Co-Exploration for Tensor Algorithms. 1-7 - Jungi Hyun, Minseok Seo, Seongho Jeong, Hyuk-Jae Lee, Xuan Truong Nguyen:
DEAR-PIM: Processing-in-Memory Architecture with Disaggregated Execution of All-bank Requests. 1-7 - Zain Taufique
, Aman Vyas, Antonio Miele, Pasi Liljeberg, Anil Kanduri:
HiDP: Hierarchical DNN Partitioning for Distributed Inference on Heterogeneous Edge Platforms. 1-7 - Alptekin Vardar, Franz Müller, Gonzalo Cuñarro, Nellie Laleni, Nandakishor Yadav, Thomas Kämpfe:
Genetic Algorithm-Driven IMC Mapping for CNNs Using Mixed Quantization and MLC FeFETs. 1-7 - Homer Gamil, Oleg Mazonka, Michail Maniatakos:
Coala: Coalescion-Based Acceleration of Polynomial Multiplication for GPU Execution. 1-7 - Qinghang Zhao, Yixi Ji, Jiaqi Wang, Jinjian Wu, Guangming Shi:
Simultaneous Denoising and Compression for DVS with Partitioned Cache-Like Spatiotemporal Filter. 1-7 - Yujin Nam, Abhishek Moitra, Yeshwanth Venkatesha, Xiaofan Yu, Gabrielle De Micheli, Xuan Wang, Minxuan Zhou, Augusto Vega, Priyadarshini Panda, Tajana Rosing:
Rhychee-FL: Robust and Efficient Hyperdimensional Federated Learning with Homomorphic Encryption. 1-7 - Alex Bendrick, Daniel Tappe, Nora Sperling, Rolf Ernst, Andrea Nota, Selma Saidi, Frank Diermeyer:
Teleoperation as a Step Towards Fully Autonomous Systems. 1-8 - Davide Bellassai, Gerlando Sciangula, Claudio Scordino, Daniel Casini, Alessandro Biondi:
Modeling the SL-LET Paradigm in AUTOSAR Adaptive. 1-7 - Xiaorang Guo, Jonas Winklmann, Dirk Stober, Amr Elsharkawy, Martin Schulz:
Design of an FPGA-Based Neutral Atom Rearrangement Accelerator for Quantum Computing. 1-6 - Siwei Ye, Minqing Sun, Huifeng Zhu, Yier Jin, An Zou:
RT-VirtIO: Towards the Real-Time Performance of VirtIO in a Two-Tier Computing Architecture. 1-7 - Francesca Palumbo, Francesco Ratto, Claudio Rubattu, Maria Katiuscia Zedda, Tiziana Fanni, Veena Rao, Bart Driessen, Jerónimo Castrillón:
Multi-Partner Project: Key Enabling Technologies for Cognitive Computing Continuum - MYRTUS Project Perspective. 1-7 - Mariam Elgamal, Abdulrahman Mahmoud, Gu-Yeon Wei, David Brooks, Gage Hills:
PFASware: Quantifying the Environmental Impact of Per- and Polyfluoroalkyl Substances (PFAS) in Computing Systems. 1-2 - Ruicheng Dai, Xuan Wang, Wenhui Liang, Xiaolong Shen, Menghui Xu, Leibin Ni, Gezi Li, Weikang Qian:
Efficient Approximate Logic Synthesis with Dual-Phase Iterative Framework. 1-7 - Yuting He, Jingjin Li, Chengtai Li, Qingyu Yang, Zheng Wang, Heshan Du, Jianfeng Ren, Heng Yu:
De2r: Unifying DVFS and Early-Exit for Embedded AI Inference via Reinforcement Learning. 1-7 - Mohammad Hamad, Christian Prehofer, Mikael Asplund, Tobias Löhr, Lucas Bublitz, Alexander Zeh, Mridula Singh, Sebastian Steinhorst:
Cybersecurity Challenges of Autonomous Systems. 1-10 - Li Cai, Zhibing Sha, Jun Li, Jiaojiao Wu, Huanhuan Tian, Zhigang Cai, Jianwei Liao:
A Two-level SLC Cache Hierarchy for Hybrid SSDs. 1-7 - Chuyu Wang, Ke Hu, Fan Yang, Keren Zhu, Xuan Zeng:
DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement. 1-7 - Severin Bochem, Victor J. B. Jung, Arpan Suravi Prasad, Francesco Conti, Luca Benini:
Distributed Inference with Minimal Off-Chip Traffic for Transformers on Low-Power MCUs. 1-7 - Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang:
Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. 1-7 - Tong Liu, Zijun Jiang, Yangdi Lyu:
CPP-SGS: Cycle-Accurate Power Prediction Framework via SNN and Genetic Signal Selection. 1-2 - Haonan Du, Chenyi Wen, Zhengrui Chen, Li Zhang, Qi Sun, Zheyu Yan, Cheng Zhuo:
Algorithm-Hardware Co-Design of a Unified Accelerator for Non-Linear Functions in Transformers. 1-7 - Minwoo Kang, Mingjie Liu, Ghaith Bany Hamad, Syed M. Suhaib, Haoxing Ren:
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware. 1-6 - Marko S. Andjelkovic, Fabian Vargas, Milos Krstic, Luigi Dilillo, Alain Michez, Frederic Wrobel, Davide Bertozzi, Mikel Luján, Christos Georgakidis, Nikolaos Chatzivangelis, Katerina Tsilingiri, Nikolaos Zazatis, Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Christos P. Sotiriou:
Multi-Partner Project: Twinning for Excellence in Reliable Electronics (TWIN-RELECT). 1-6 - Luca Colagrande, Jayanth Jonnalagadda, Luca Benini:
Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors. 1-2 - Enrico Russo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania:
Optimizing Qubit Assignment in Modular Quantum Systems via Attention-Based Deep Reinforcement Learning. 1-7 - Yingnan Zhao, Ke Wang, Ahmed Louri:
A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks. 1-7 - Odysseas Chatzopoulos, George Papadimitriou, Dimitris Gizopoulos, Harish Dattatraya Dixit, Sriram Sankar:
From Gates to SDCs: Understanding Fault Propagation Through the Compute Stack. 1-7 - Anup Das:
Exploring Dendritic Computation in Bio-Inspired Architectures for Dynamic Programming. 1-6 - Ioannis Chrysakis, Evangelos Agorogiannis, Nikoleta Tsampanaki, Michalis Vourtzoumis, Eva Chondrodima, Yannis Theodoridis, Domen Mongus, Ben Capper, Martin Wagner, Aris Sotiropoulos, Fábio André Coelho, Cláudia Vanessa Brito, Panos Protopapas, Despina Brasinika, Ioanna Fergadiotou, Christos Doulkeridis:
Multi-Partner Project: Green.Dat.AI: A Data Spaces Architecture for Enhancing Green AI Services. 1-7 - Bangqi Fu, Lixin Liu, Qijing Wang, Yutao Wang, Martin D. F. Wong, Evangeline F. Y. Young:
Fast Dynamic IR-Drop Prediction with Dual-Path Spatial-Temporal Attention. 1-7 - Xiangyu Wang, Yuan Li, Zhijie Yang, Chao Xiao, Xun Xiao, Renzhi Chen, Weixia Xu, Lei Wang:
ASNPC: An Automated Generation Framework for SNN and Neuromorphic Processor Co-Design. 1-7 - Debraj Kundu, Tsun-Ming Tseng, Shigeru Yamashita, Ulf Schlichtmann:
Loading-Aware Mixing-Efficient Sample Preparation on Programmable Microfluidic Device. 1-2 - Lukas Krupp, Ian O'Connor, Luca Benini, Christoph Studer, Joachim Rodrigues, Norbert Wehn:
Improving Chip Design Enablement for Universities in Europe - A Position Paper. 1-7 - Lang Feng, Rongjian Liang, Hongxin Kong:
Hybrid Exact and Heuristic Efficient Transistor Network Optimization for Multi-Output Logic. 1-7 - Sunil Sudhakaran, Clark W. Barrett, Mark Horowitz:
Application of Formal Methods (SAT/SMT) to the Design of Constrained Codes. 1-7 - Kota Fukuda, Guanqin Zhang, Zhenya Zhang, Yulei Sui, Jianjun Zhao:
Adaptive Branch-and-Bound Tree Exploration for Neural Network Verification. 1-7 - Panagiota Nikolaou, Antonis Savva, Ioannis Sorokos, Koorosh Aslansefat, Sondess Missaoui, Mohammed Naveed Akram, Daniel Hillen, Marc Lorenz, Martin D. Walker, Manos Papoutsakis, Simos Gerasimou, Panayiotis Kolios, Yiannis Papadopoulos, Jan Reich, Sotiris Ioannidis, Maria K. Michael:
Multi-Partner Project: Safe, Secure and Dependable Multi-UAV Systems for Search and Rescue Operations. 1-7 - Alper Kanak, Salih Ergün, Ibrahim Arif, Ali Serdar Atalay, Serhat Ege Inanç, Oguzhan Herkiloglu, Ahmet Yazici, Yunus Sabri Kirca, Muhammed Ozberk, Alim Kerem Erdogmus, Ali Kafali, Dilara Bayar, Muhammed Oguz Tas, Luca Davoli, Laura Belli, Gianluigi Ferrari, Badar Muneer, Valentina Palazzi, Luca Roselli, Fabio Gelati:
Multi-Partner Project: Electric Vehicle Data Acquisition and Valorisation: A Perspective from the OPEVA Project. 1-7 - Yujie Zhang, Shivam Aggarwal, Tulika Mitra:
DAOP: Data-Aware Offloading and Predictive Pre-Calculation for Efficient MoE Inference. 1-7 - Zhen Yu, Jinhao Li, Jiaming Xu, Shan Huang, Jiancai Ye, Ningyi Xu, Guohao Dai:
DyLGNN: Efficient LM-GNN Fine-Tuning with Dynamic Node Partitioning, Low-Degree Sparsity, and Asynchronous Sub-Batch. 1-7 - Yassaman Ebrahimzadeh Maboud, Muhammad Adnan, Divya Mahajan, Prashant J. Nair:
Slipstream: Semantic-Based Training Acceleration for Recommendation Models. 1-7 - Hassan Nassar, Ming-Liang Wei, Chia-Lin Yang, Jörg Henkel, Kuan-Hsun Chen:
REAP-NVM: Resilient Endurance-Aware NVM-Based PUF Against Learning-Based Attacks. 1-2 - Simone Manoni, Paul Scheffler, Luca Zanatta, Andrea Acquaviva, Luca Benini, Andrea Bartolini:
SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions. 1-7 - Hsiang-Chun Cheng, RuiJie Wang, TingTing Hwang:
Using OFF-set only for Corrupting Circuit to Resist Structural Attack in CAC Locking. 1-7 - Dingyang Zou, Gaoche Zhang, Kairui Sun, Zhe Wen, Meiqi Wang, Zhongfeng Wang:
LLM4GV: An LLM-Based Flexible Performance-Aware Framework for GEMM Verilog Generation. 1-2 - Fabio T. Ramos, Pedro E. F. Realino, Wagner A. Junior, Alex Borges Vieira, Ricardo S. Ferreira, José Augusto Miranda Nacif:
SmartMap: Architecture-Agnostic CGRA Mapping Using Graph Traversal and Reinforcement Learning. 1-7 - Jingkui Yang, Mei Wen, Junzhong Shen, Jianchao Yang, Yasong Cao, Jun He, Minjin Tang, Zhaoyun Chen, Yang Shi:
SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity. 1-7 - Ashton Snelgrove, Daniel Wakeham, Skylar Stockham, Scott Temple, Pierre-Emmanuel Gaillardon:
OpenMFDA: Microfluidic Design Automation in Three Dimensions. 1-7 - Safin Bayes, Mohamed Hassan:
Criticality and Requirement Aware Heterogeneous Coherence for Mixed Criticality Systems. 1-7 - M. Dhilipkumar, Priyanka Bagade, Debapriya Basu Roy:
Three Eyed Raven: An On-Chip Side Channel Analysis Framework for Run-Time Evaluation. 1-7 - Tianyao Lu, Anlin Liu, Bingjie Xia, Peng Liu:
Comprehensive RISC- V Floating-Point Verification: Efficient Coverage Models and Constraint-Based Test Generation. 1-7 - Patrick Hopf, Nils Quetschlich, Laura Brandon Schulz, Robert Wille:
Improving Figures of Merit for Quantum Circuit Compilation. 1-7 - Xin Hong, Dingchao Gao, Sanjiang Li, Shenggang Ying, Mingsheng Ying:
Image Computation for Quantum Transition Systems. 1-7 - Jinnuo Li, Chi Cheng, Muyan Shen, Peng Chen, Qian Guo, Dongsheng Liu, Liji Wu, Jian Weng:
Grafted Trees Bear Better Fruit: An Improved Multiple-Valued Plaintext-Checking Side-Channel Attack Against Kyber. 1-7 - Can Joshua Lehmann, Lars Bauer, Hassan Nassar, Heba Khdr, Jörg Henkel:
Hardware/Software Co-Analysis for Worst Case Execution Time Bounds. 1-2 - Zain Alabedin Haj Hammadeh, Mohammad Hamad, Andrzej Olchawa, Milenko Starcik, Ricardo Fradique, Stefan Langhammer, Manuel Hoffmann, Florian Göhler, Daniel Lüdtke, Michael Felderer, Sebastian Steinhorst:
Designing Secure Space Systems. 1-10 - Mohammad Hamad, Michael Kühr, Haralambos Mouratidis, Eleni-Maria Kalogeraki, Christos A. Gizelis, Dimitris Papanikas, Athanasios Bountioukos-Spinaris, Charilaos Skandylas, Evangelos Raptis, Andreas Alexopoulos, Grigorios Chrysos, Mina Marmpena, Sevasti Politi, Konstantinos Lieros, Papagiannopoulos Nikolaos, Iordanis Xanthopoulos, Spyros Papastergiou, Sotiris Ioannidis, Mikael Asplund, Marc-Oliver Pahl, Sebastian Steinhorst:
Multi-Partner Project: CyberSecDome - Framework for Secure, Collaborative, and Privacy-Aware Incident Handling for Digital Infrastructure. 1-7 - Yongho Lee, Junbum Park, Osang Kwon, Sungbin Jang, Seokin Hong:
Buddy ECC: Making Cache Mostly Clean in CXL-Based Memory Systems for Enhanced Error Correction at Low Cost. 1-7 - Jun Li, Xiaofei Xu, Zhibing Sha, Xiaobai Chen, Jieming Yin, Jianwei Liao:
CoupledCB: Eliminating Wasted Pages in Copyback-based Garbage Collection for SSDs. 1-7 - Bernhard Lippmann, Johanna Baehr, Alexander Hepp, Horst A. Gieser:
Multi-Partner Project: Reverse Engineering Methods for Trusted Chip Design (RESEC). 1-7 - Yuhao Leng, Jinglin Han, Yining Wang, Peng Wang:
TPC-GAN: Batch Topology Synthesis for Performance-Compliant Operational Amplifiers Using Generative Adversarial Networks. 1-7 - Yifan Guo, Jiawei Chen, Yexin Li, Yunxiang Zhang, Qing Zhang, Yuhang Zhang, Yongfu Li:
SEDG: Stitch-Compatible End-to-End Layout Decomposition Based on Graph Neural Network. 1-7 - Nathan Eli Miller, Laith A. Shamieh, Saibal Mukhopadhyay:
Low-Latency Digital Feedback for Stochastic Quantum Calibration Using Cryogenic CMOS. 1-7 - Xin Ju, Jun He, Mei Wen, Jing Feng, Yasong Cao, Junzhong Shen, Zhaoyun Chen, Yang Shi:
WinAcc: Window-based Acceleration of Neural Networks Using Block Floating Point. 1-7 - Zongwu Wang, Fangxin Liu, Peng Xu, Qingxiao Sun, Junping Zhao, Li Jiang:
EVASION: Efficient KV CAche CompreSsion vIa PrOduct QuaNtization. 1-2 - Myeongjae Jang, Jesung Kim, Haejin Nam, Sihyun Kim, Soontae Kim:
C2C: A Framework for Critical Token Classification in Transformer-Based Inference Systems. 1-2 - Ye Cai, Chuyu Zheng, Wei He, Dan Tang:
Verilua: An Open Source Versatile Framework for Efficient Hardware Verification and Analysis Using LuaJIT. 1-2 - Tara Gheshlaghi, Priyanjana Pal, Haibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori:
ADAPT-pNC: Mitigating Device Variability and Sensor Noise in Printed Neuromorphic Circuits with SO Adaptive Learnable Filters. 1-7 - Taesoo Lim, Hyeonjin Kim, Jingu Park, Bogil Kim, William J. Song:
RoTA: Rotational Torus Accelerator for Wear Leveling of Neural Processing Elements. 1-7 - Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace:
EDA-Aware RTL Generation with Large Language Models. 1-6 - Yunhao Dong, Zhaoyu Zhong, Yi Wang, Chenlin Ma, Tianyu Wang:
Dancer: Dynamic Compression and Quantization Architecture for Deep Graph Convolutional Network. 1-7 - Haoyu Yang, Qijing Huang, Nathaniel Ross Pinckney, Walker J. Turner, Wenfei Zhou, Yanqing Zhang, Chia-Tung Ho, Chen-Chia Chang, Haoxing Ren:
ChipVQA: Benchmarking Visual Language Models for Chip Design. 1-6 - Wujie Zhong, Yangdi Lyu:
DuSGAI: A Dual-Side Sparse GEMM Accelerator with Flexible Interconnects. 1-2 - Xiangfei Hu, Yuyang Ye, Tinghuan Chen, Hao Yan, Bei Yu:
Timing-Driven Approximate Logic Synthesis Based on Double-Chase Grey Wolf Optimizer. 1-7 - Renzhi Xiao, Dan Feng, Yuchong Hu, Yucheng Zhang, Lanlan Cui, Lin Wang:
Write-Optimized Persistent Hash Index for Non-Volatile Memory. 1-7 - Varatheepan Paramanayakam, Andreas Karatzas, Iraklis Anagnostopoulos, Dimitrios Stamoulis:
Less is More: Optimizing Function Calling for LLM Execution on Edge Devices. 1-7 - Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler:
Polynomial Formal Verification of Sequential Circuits Using Weighted-AIGs. 1-7 - Junjiao Sun, Laura Gutiérrez-Martín, Celia López-Ongil, José Miranda, Jorge Portilla, Andrés Otero:
Solving the Cold-Start Problem for the Edge: Clustering and Adaptive Deep Learning for Emotion Detection. 1-7 - Xiangrong Xu, Yuanqiu Lv, Liang Wang, Limin Xiao, Meng Han, Runnan Shen, Jinquan Wang:
Swift-Sim: A Modular and Hybrid GPU Architecture Simulation Framework. 1-7 - Mario Libro, Sebastiano Gaiardelli, Marco Panato, Stefano Spellini, Michele Lora, Franco Fummi:
Exploiting SysML v2 Modeling for Automatic Smart Factories Configuration. 1-7 - Niko Zurstraßen, Nils Bosbach, Rainer Leupers:
FloppyFloat: An Open Source Floating Point Library for Instruction Set Simulators. 1-6 - Marc Boyer, Rafik Henia:
Multi-Partner Project: Resilient Time-Sensitive Networks (ResTSN). 1-4 - Yinchen Ni, Jiace Zhu, Yier Jin, An Zou:
RTHeter: Simulating Real-Time Scheduling of Multiple Tasks on Heterogeneous Architectures. 1-7 - Giuseppe Spadavecchia, Marco Fiore, Marina Mongiello, Daniela De Venuto:
Decentralizing IoT Data Processing: The Rise of Blockchain-Based Solutions. 1-2 - Quansen Wang, Vasilis F. Pavlidis, Yuanqing Cheng:
A Comprehensive Inductance-Aware Modeling Approach to Power Distribution Network in Heterogeneous 3D Integrated Circuits. 1-2 - Josef Salzmann, Ulrich Schmid:
Signal Prediction for Digital Circuits by Sigmoidal Approximations Using Neural Networks. 1-2 - Siou-Sian Lin, Shih-Yu Chen, Yu-Ping Huang, Tzu-Chuan Lin, Hung-Ming Chen, Wei-Zen Chen:
Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis. 1-7 - Huseyin Ekin Sumbul, Arne Symons, Lita Yang, Huichu Liu, Tony F. Wu, Matheus Trevisan Moreira, Debabrata Mohapatra, Abhinav Agarwal, Kaushik Ravindran, Chris Thompson, Yuecheng Li, Edith Beigné:
A 3D Design Methodology for Integrated Wearable SoCs: Enabling Energy Efficiency and Enhanced Performance at Iso-Area Footprint. 1-7 - Vaishnavi Pulavarthi, Deeksha Nandal, Soham Dan, Debjit Pal:
Are LLMs Ready for Practical Adoption for Assertion Generation? 1-7 - Guy Eichler, Joseph Zuckerman, Luca P. Carloni:
KalmMind: A Configurable Kalman Filter Design Framework for Embedded Brain-Computer Interfaces. 1-2 - Goerschwin Fey, Harry Foster, Tara Ghasempuri, Badri Gopalan, Jörg Müller, Manish Pandey:
Specification Mining Facing Generative AI. 1 - Aikata Aikata, Daniel Sanz Sobrino, Sujoy Sinha Roy:
Pasta on Edge: Cryptoprocessor for Hybrid Homomorphic Encryption. 1-7 - Po-Shao Chen, Wei Tang, Zhengya Zhang:
Practical MU-MIMO Detection and LDPC Decoding Through Digital Annealing. 1-7 - Osang Kwon, Yongho Lee, Seokin Hong:
Improving Address Translation in Tagless DRAM Cache by Caching PTE Pages. 1-7 - Zelin Du, Kecheng Huang, Tianyu Wang, Xin Yao, Renhai Chen, Zili Shao:
A Practical Learning-Based FTL for Memory Constrained Mobile Flash Storage. 1-7 - Stefano Mercogliano, Alessandro Cilardo:
Umbra: An Efficient Framework for Trusted Execution on Modern TrustZone-Enabled Microcontrollers. 1-2 - Hefei Wang, Jianghao Su, Junhe Xue, Haoran Lyu, Junhua Zhang, Longyang Lin, Kai Chen, Lijuan Yang, Shenghua Zhou:
Post-Layout Automated Optimization for Capacitor Array in Digital-to-Time Converter. 1-5 - Yujia Wang, Jiaxing Wang, Dan Feng, Yuzhe Ma, Kang Liu:
Location is All You Need: Efficient Lithographic Hotspot Detection Using Only Polygon Locations. 1-7 - Bolun Zhu, Yu Hua:
Arbiter: Alleviating Concurrent Write Amplification in Persistent Memory. 1-7 - Rune Krauss, Jan Zielasko, Rolf Drechsler:
FrEDDY: Modular and Efficient Framework to Engineer Decision Diagrams Yourself. 1-2 - Priyanshu Tyagi, Sparsh Mittal:
A 101 TOPS/W and 1.73 TOPS/mm2 6T SRAM-Based Digital Compute-in-Memory Macro Featuring a Novel 2T Multiplier. 1-7 - Giulio Galderisi, Andreas Kramer, Andreas Fuchsberger, Jose Maria Gonzalez-Medina, Yuxuan He, Lee-Chi Hung, Marrit Jen Hong Li, Julian Kulenkampff, Maximilian Reuter, Lukas Wind, Masiar Sistani, Thomas Mikolajick, Bruno Neckel Wesling, Marina Deng, Cristell Maneux, Pieter Harpe, Sonia Prado-López, Oskar Baumgartner, Chhandak Mukherjee, Eugenio Cantatore, Sandro Carrara, Klaus Hofmann, Walter M. Weber, Jens Trommer:
Multi-Partner Project: Smart Sensor Analog Front-Ends Powered by Emerging Reconfigurable Devices (SENSOTERIC). 1-4 - Paolo Bernardi, B. Borio, Giorgio Insinga, B. Mendicino, M. Battilana, M. Coppetta, N. Mautone, Pierre Scaramuzza, F. Tengler, Rudolf Ullmann:
Late Breaking Results: A Data Compaction Strategy for Extensive Test Flows of Memories Embedded in Automotive SoCs. 1-2 - Anastassis Kapetanakis, Aggelos Ferikoglou, George Anagnostopoulos, Sotirios Xydis:
Dataflow Optimized Reconfigurable Acceleration for FEM-Based CFD Simulations. 1-6 - Hasini Witharana, Hansika Weerasena, Prabhat Mishra:
Security Assertions for Trusted Execution Environments. 1-6 - Yipu Zhang, Jiawei Liang, Jian Peng, Jiang Xu, Wei Zhang:
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices. 1-7 - Yu Chen Wang, Ing-Chao Lin, Yuan-Hao Chang:
SegTransformer: Enhancing Softmax Performance Through Segmentation with a ReRAM-Based PIM Accelerator. 1-2 - Junbum Park, Yongho Lee, Sungbin Jang, Wonyoung Lee, Seokin Hong:
SPB: Towards Low-Latency CXL Memory via Speculative Protocol Bypassing. 1-7 - Chunmyung Park, Jicheon Kim, Eunjae Hyun, Xuan Truong Nguyen, Hyuk-Jae Lee:
Leveraging Hot Data in a Multi-Tenant Accelerator for Effective Shared Memory Management. 1-7 - Lei Cai, Guojing Ge, Guibo Zhu, Jixin Zhang, Jinqiao Wang, Bowen Jia, Ning Xu:
SACPlace: Multi-Agent Deep Reinforcement Learning for Symmetry-Aware Analog Circuit Placement. 1-7 - Jiechen Huang, Shuailong Liu, Wenjian Yu:
A Parallel Floating Random Walk Solver for Reproducible and Reliable Capacitance Extraction. 1-7 - Kunming Shao, Fengshi Tian, Xiaomeng Wang, Jiakun Zheng, Jia Chen, Jingyu He, Hui Wu, Jinbo Chen, Xihao Guan, Yi Deng, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui:
SynDCIM: A Performance-Aware Digital Computing-in-Memory Compiler with Multi-Spec-Oriented Subcircuit Synthesis. 1-7 - Xiaoze Lin, Liyang Lai, Huawei Li, Biwei Xie, Xingquan Li:
An Efficient Parallel Fault Simulator for Functional Patterns on Multi-Core Systems. 1-7 - Luis Bertran Alvarez, Ghassan Chehaibar, Stephen Busch, Pascal Benoit, David Novo:
c2c-gem5: Full System Simulation of Cache-Coherent Chip-to-Chip Interconnects. 1-7 - Yuchao Wu, Xiaofei Yu, Hao Chen, Yang Luo, Yeyu Tong, Yuzhe Ma:
PICBench: Benchmarking LLMs for Photonic Integrated Circuits Design. 1-6 - Mu Nie, Shidong Zhu, Aibin Yan, Cheng Zhuo, Xiaoqing Wen, Tianming Ni:
Efficient Modulated State Space Model for Mixed-Type Wafer Defect Pattern Recognition. 1-6 - Andreas Karatzas, Dimitrios Stamoulis, Iraklis Anagnostopoulos:
RankMap: Priority-Aware Multi-DNN Manager for Heterogeneous Embedded Devices. 1-7 - Md Mizanur Rahaman Nayan, Ritik Raj, Shaik Gouse Basha, Tushar Krishna, Azad J. Naeemi:
Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col. 1-7 - Julian Demicoli, Sebastian Steinhorst:
Designing Resilient Autonomous Systems with the Reflex Pattern. 1-7 - Mariam Rakka, Jinhao Li, Guohao Dai, Ahmed M. Eltawil, Mohammed E. Fouda, Fadi J. Kurdahi:
SoftmAP: Software-Hardware Co-Design for Integer-Only Softmax on Associative Processors. 1-7 - Yuhang Qiu, Wenming Li, Tianyu Liu, Zhen Wang, Zhiyuan Zhang, Zhihua Fan, Xiaochun Ye, Dongrui Fan, Zhimin Tang:
Accelerating Authenticated Block Ciphers via RISC-V Custom Cryptography Instructions. 1-7 - M. Lakshmi Varshika, Jonathan Hollenbach, Nicolas Bohm Agostini, Ankur Limaye, Antonino Tumeo, Anup Das:
Online Learning for Dynamic Structural Characterization in Electron Energy Loss Spectroscopy. 1-7 - Jinghao Ding, Jiazhi Wen, Hao Tang, Zhaoqi Fu, Mengshi Gong, Yuanrui Qi, Wenxin Yu, Jinjia Zhou:
An Effective and Efficient Cross-Link Insertion for Non-Tree Clock Network Synthesis. 1-7 - Changmin Ye, Yonguk Sim, Youngchae Kim, SeongMin Jin, Doo Seok Jeong:
IterL2Norm: Fast Iterative L2-Normalization. 1-7 - Jehun Lee, Jae-Joon Kim:
Integer Unit-Based Outlier-Aware LLM Accelerator Preserving Numerical Accuracy of FP-FP GEMM. 1-7 - Akshansh Yadav, Anadi Goyal, Palash Das:
Hybrid Token Selector based Accelerator for ViTs. 1-7 - Minqing Sun, Ruiqi Sun, Yingtao Shen, Wei Yan, Qinfen Hao, An Zou:
SSMDVFS: Microsecond-Scale DVFS on GPGPUs with Supervised and Self-Calibrated ML. 1-7 - Mahdi Benkhelifa, Shivendra Singh Parihar, Anirban Kar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch:
Pushing the Boundaries of AI Chips: From Monolithic 3D CMOS to Cryogenic Computing. 1-6 - Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
CorrectBench: Automatic Testbench Generation with Functional Self-Correction using LLMs for HDL Design. 1-7 - Gelei Xu, Ningzhi Tang, Jun Xia, Ruiyang Qin, Wei Jin, Yiyu Shi:
Enabling Memory-Efficient On-Device Learning via Dataset Condensation. 1-7 - Benedikt Ohse, Jürgen Kampe, Christopher Schneider:
Circuits in a Box: Computing High-Dimensional Performance Spaces for Analog Integrated Circuits. 1-7 - Rui Chen, Ingo Sander:
Towards Coherent Semantics: A Quantitatively Typed EDSL for Synchronous System Design. 1-2 - Joyjit Kundu, Debjyoti Bhattacharjee, Nathan Josephsen, Ankit Pokhrel, Udara De Silva, Wenzhe Guo, Steven Van Winckel, Steven Brebels, Quentin Herr, Anna Herr, Manu Perumkunnil:
A System Level Performance Evaluation for Superconducting Digital Systems. 1-7 - Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini:
AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors. 1-7 - Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng:
HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. 1-6 - Xiaolin Li, Wei Yan, Hongwei Liu, Yong Zhang, Qinfen Hao, Yong Liu, Ninghui Sun:
Accelerating Oblivious Transfer with a Pipelined Architecture. 1-2 - Jan Drewniok, Marcel Walter, Samuel Sze Hang Ng, Konrad Walus, Robert Wille:
Towards Fast Automatic Design of Silicon Dangling Bond Logic. 1-2 - Jiayi Li, Hongxiao Zhao, Wenshuo Yue, Yihan Fu, Daijing Shi, Anjunyi Fan, Yuchao Yang, Bonan Yan:
PEARL: FPGA-Based Reinforcement Learning Acceleration with Pipelined Parallel Environments. 1-7 - Gianmarco Mongelli, Eric Faehn, Dylan Robins, Patrick Girard, Arnaud Virazel:
Accelerating Cell-Aware Model Generation for Sequential Cells using Graph Theory. 1-7 - Davide Basso, Luca Bortolussi, Mirjana S. Videnovic-Misic, Husni Habal:
Effective Analog ICs Floorplanning with Relational Graph Neural Networks and Reinforcement Learning. 1-7 - Louis Morge-Rollet, Camélia Slimani, Laurent Lemarchand, Frédéric Le Roy, David Espes, Jalil Boukhobza:
DisPEED: Distributing Packet flow analyses in a swarm of heterogeneous EmbEddeD platforms. 1-7 - Qinkai Xu, Yijin Liu, Yuan Meng, Yang Chen, Yunlong Mao, Li Li, Yuxiang Fu:
LT-OAQ: Learnable Threshold Based Outlier-Aware Quantization and its Energy-Efficient Accelerator for Low-Precision On-Chip Training. 1-6 - Yasmine Abu-Haeyeh, Thomas Bartelsmeier, Tobias Ladner, Matthias Althoff, Lars Hedrich, Markus Olbrich:
Formally Verifying Analog Neural Networks with Device Mismatch Variations. 1-7 - Ilkin Aliyev, Jesus Lopez, Tosiron Adegbija:
Exploring the Sparsity-Quantization Interplay on a Novel Hybrid SNN Event-Driven Architecture. 1-7 - Renjie Wei, Zechun Liu, Yuchen Fan, Runsheng Wang, Ru Huang, Meng Li:
SCALES: Boost Binary Neural Network for Image Super-Resolution with Efficient Scalings. 1-7 - Mohammad Reza Heidari Iman, Sergio Vinagrero Gutierrez, Elena-Ioana Vatajelu, Giorgio Di Natale:
Late Breaking Results: Automatic Anomaly Detection Method in Physical Unclonable Functions using Data Mining Techniques. 1-2 - Ludwig Schmid, Tom Peham, Lucas Berent, Markus Müller, Robert Wille:
Deterministic Fault-Tolerant State Preparation for Near-Term Quantum Error Correction: Automatic Synthesis Using Boolean Satisfiability. 1-7 - Kyungjun Min, Seonghyeon Park, Hyeonwoo Park, Jinoh Cho, Seokhyeong Kang:
Improving LLM-Based Verilog Code Generation with Data Augmentation and RL. 1-7 - Nan Wang, Kai Li, Lijun Lu, Zhiwei Zhao, Zhiyuan Ma:
Protecting Cyber-Physical Systems via Vendor-Constrained Security Auditing with Reinforcement Learning. 1-7 - Mohammad Ebrahimabadi, Raphael Viera, Sylvain Guilley, Jean-Luc Danger, Jean-Max Dutertre, Naghmeh Karimi:
Multi-Sensor Data Fusion for Enhanced Detection of Laser Fault Injection Attacks in Cryptographic Hardware: Practical Results. 1-2 - Huijun Jin, Jieun Lee, Shengmin Piao, Sangmin Seo, Sein Kwon, Sanghyun Park:
Efficient Approximate Nearest Neighbor Search via Data-Adaptive Parameter Adjustment in Hierarchical Navigable Small Graphs. 1-7 - Javier Diaz-Fortuny, Vishal Nayar:
Transistor Aging and Circuit Reliability at Cryogenic Temperatures. 1-4 - Shucheng Wang, Zhiguo Xu, Zhandong Guo, Jian Sheng, Kaiye Zhou, Qiang Cao:
LCache: Log-Structured SSD Caching for Training Deep Learning Models. 1-7 - Shaoqi Li, Tianyu Wang, Yongbiao Zhu, Chenlin Ma, Yi Wang, Zhaoyan Shen, Zili Shao:
One Gray Code Fits All: Optimizing Access Time with Bi-Directional Programming for QLC SSDs. 1-2 - Ming-Chun Wei, Chun-Wei Shen, Hsun-Ping Hsieh:
Spatial Modeling with Automated Machine Learning and Gaussian Process Regression Techniques for Imputing Wafer Acceptance Test Data. 1-7 - Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi:
Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring. 1-7 - Wei Tao, Bin Zhang, Xiaoyang Qu, Jiguang Wan, Jianzong Wang:
Cocktail: Chunk-Adaptive Mixed-Precision Quantization for Long-Context LLM Inference. 1-7 - Victor Marot, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Elliott Worsey, Roshan Weerasekera, Dinesh Pamunuwa:
Nanoelectromechanical Binary Comparator for Edge-Computing Applications. 1-7 - Jan Spieck, Dominik Walter, Jan Waschkeit, Jürgen Teich:
Co-Design of Sustainable Embedded Systems-on-Chip. 1-2 - Tengyu Zhang, Yufei Xue, Ling Liang, Zhen Gu, Yuan Wang, Runsheng Wang, Ru Huang, Meng Li:
FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic Encryption. 1-7 - Huifan Zhang, Yun Hu, Pingqiang Zhou:
Time-Domain 3D Electromagnetic Fields Estimation Based on Physics-Informed Deep Learning Framework. 1-7 - Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Yu-Che Lee, Jia-Wei Lin, Hsun-Wei Pao, Peng-Wen Chen, Po-Yu Chen, Hao-Yun Chen, Yung-Chih Chen, Chun-Yao Wang, Shih-Chieh Chang:
Dynamic IR-Drop Prediction Through a Multi-Task U-Net with Package Effect Consideration. 1-7 - Ismet Dagli, James Crea, Soner Seçkiner, Yuanchao Xu, Selçuk Köse, Mehmet E. Belviranli:
${MC}^{3}$: Memory Contention-Based Covert Channel Communication on Shared DRAM System-on-Chips. 1-7 - Dhoui Lim, Heechun Park:
Timing-Driven Detailed Placement with Unsupervised Graph Learning. 1-7 - Joongho Jo, Jongsun Park:
PS-GS: Group-Wise Parallel Rendering with Stage-Wise Complexity Reductions for Real-Time 3D Gaussian Splatting. 1-7 - Klajd Zyla, Marco Liess, Thomas Wild, Andreas Herkersdorf:
HiPerNoC: A High-Performance Network-an-Chip for Flexible and Scalable FPGA-Based SmartNICs. 1-7 - Anand Yeolekar, Ravindra Metta, Samarjit Chakraborty:
SMT-Based Repairing Real-Time Task Specifications. 1-7 - Surendra Hemaram, Mahta Mayahinia, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Tommaso Marinelli, Anita Farokhnejad, Gouri Sankar Kar:
InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM. 1-2 - Xilang Zhou, Haodong Lu, Tianchen Wang, Zhuoheng Wan, Jianli Chen, Jun Yu, Kun Wang:
TaiChi: Efficient Execution for Multi-DNNs Using Graph-Based Scheduling. 1-7 - Manfred Schlägl, Daniel Große:
Fast Interpreter-Based Instruction Set Simulation for Virtual Prototypes. 1-7 - Linhao Lu, Wenxin Yu, Hongwei Tian, Chengjin Li, Xinmiao Li, Zhaoqi Fu, Zhengjie Zhao, Jingwei Lu:
Timing-Driven Global Placement With Hybrid Heuristics and Nadam-Based Net Weighting. 1-7 - Elijah Seth Cishugi, Sebastian Buschjäger, Martijn Noorlander, Marco Ottavi, Kuan-Hsun Chen:
TrackScorer: Skyrmion Logic-in-Memory Accelerator for Tree-Based Ranking Models. 1-7 - Jonas Hansen, Srinidhi Srinivasan, Geoffrey Nelissen, Kim G. Larsen:
Exact Schedulability Analysis for Limited-Preemptive Parallel Applications Using Timed Automata in UPPAAL. 1-7 - Shambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone:
HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization. 1-7 - Matthew Bozoukov, Nguyen Anh Vu Doan, Bryan Donyanavard:
Generating and Predicting Output Perturbations in Image Segmenters. 1-6 - Cristian Tirelli, Rodrigo Otoni, Laura Pozzi:
Monomorphism-Based CGRA Mapping Via Space and Time Decoupling. 1-7 - Ki-Dong Kang, Gyeongseo Park, Daehoon Kim:
Co-UP: Comprehensive Core and Uncore Power Management for Latency-Critical Workloads. 1-7 - Chang Meng, Wayne P. Burleson, Weikang Qian, Giovanni De Micheli:
Gradient Approximation of Approximate Multipliers for High-Accuracy Deep Neural Network Retraining. 1-7 - Joan Bushi, Alberto Battistello, Guido Bertoni, Vittorio Zaccaria:
Design, Implementation and Validation of NSCP: A New Secure Channel Protocol for Hardened IoT. 1-7 - Hong Pang, Carmine Cappetta, Riccardo Massa, Athanasios Vasilopoulos, Elena Ferro, Gamze Islamoglu, Angelo Garofalo, Francesco Conti, Luca Benini, Irem Boybat, Thomas Boesch:
Multi-Mode Borderguard Controllers for Efficient On-Chip Communication in Heterogeneous Digital/Analog Neural Processing Units. 1-7 - Gaurav Kumar, Ashfaq Hussain Shaik, Anjum Riaz, Yamuna Prasad, Satyadev Ahlawat:
Compatibility Graph Assisted Automatic Hardware Trojan Insertion Framework. 1-7 - Lennart Weingarten, Kamalika Datta, Rolf Drechsler:
Late Breaking Results: Towards Efficient Formal Verification of Dot Product Architectures. 1-2 - Benedikt Dietrich, Rasmus Müller-Both, Heba Khdr, Jörg Henkel:
Federated Reinforcement Learning for Optimizing the Power Efficiency of Edge Devices. 1-7 - Hasin Ishraq Reefat, Alec Aversa, Ioannis Savidis, Naghmeh Karimi:
TARN: Trust Aware Routing to Enhance Security in 3D Network-on-Chips. 1-7 - Yashvardhan Biyani, Rajendra Bishnoi, Theofilos Spyrou, Said Hamdioui:
C3CIM: Constant Column Current Memristor-Based Computation-in-Memory Micro-Architecture. 1-7 - Jiayao Ling, Gang Li, Qinghao Hu, Xiaolong Lin, Cheng Gu, Jian Cheng, Xiaoyao Liang:
SBQ: Exploiting Significant Bits for Efficient and Accurate Post-Training DNN Quantization. 1-7 - Lunshuai Pan, Shiqing Wang, Pushen Zuo, Zhong Sun:
GRAMC: General-Purpose and Reconfigurable Analog Matrix Computing Architecture. 1-2 - Davide Baroffio, Tomas Antonio Lopez, Federico Reghenzani, William Fornaciari:
Evaluating Compiler-Based Reliability with Radiation Fault Injection. 1-2 - Devin Pohl, Aaron R. Young, Kazi Asifuzzaman, Narasinga Rao Miniskar, Jeffrey S. Vetter:
Mapping Spiking Neural Networks to Heterogeneous Crossbar Architectures using Integer Linear Programming. 1-7 - Feng Guo, Jianwang Zhai, Jingyu Jia, Jiawei Liu, Kang Zhao, Bei Yu, Chuan Shi:
IR-Fusion: A Fusion Framework for Static IR Drop Analysis Combining Numerical Solution and Machine Learning. 1-7 - Pragnya Sudershan Nalla, Emad Haque, Yaotian Liu, Sachin S. Sapatnekar, Jeff Zhang, Chaitali Chakrabarti, Yu Cao:
CLAIRE: Composable Chiplet Libraries for AI Inference. 1-7 - Hazem H. Hammam, Hassan Aboushady, Haralampos-G. Stratigopoulos:
Analog Circuit Anti-Piracy Security by Exploiting Device Ratings. 1-7 - Cyril Koenig, Enrico Zelioli, Luca Benini:
Evaluating IOMMU-Based Shared Virtual Addressing for RISC-V Embedded Heterogeneous SoCs. 1-7 - Zhenyu Liu, Xilang Zhou, Faxian Sun, Jianli Chen, Jun Yu, Kun Wang:
AttentionLib: A Scalable Optimization Framework for Automated Attention Acceleration on FPGA. 1-7 - Donato Ferraro, Andrea Bastoni, Alexander Zuepke, Andrea Marongiu:
Enabling Security on the Edge: A CHERI Compartmentalized Network Stack. 1-7 - Xiangyu Li, Weichong Chen, Ruida Hong, Jinghai Wang, Ningyuan Yin, Zhiyi Yu:
FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation. 1-7 - Melisande Zonta-Roudes, Nora Hinderling, Shweta Shinde:
Xray: Detecting and Exploiting Vulnerabilities in Arm AXI Interconnects. 1-7 - Neethu Bal Mallya, Panagiotis Strikos, Bhavishya Goel, Ahsen Ejaz, Ioannis Sourdis:
A Performance Analysis of Chiplet-Based Systems. 1-7 - Michael Paulweber, Andreas Eckel, Paolo Azzoni:
Multi-Partner Project: Shaping the Vehicle of the Future - How FEDERATE and HAL4SDV are Steering Europe's Software-Defined Vehicle Ecosystem. 1-4 - Jiawei Liu, Zhiyan Liu, Xun He, Jianwang Zhai, Zhengyuan Shi, Qiang Xu, Bei Yu, Chuan Shi:
WideGate: Beyond Directed Acyclic Graph Learning in Subcircuit Boundary Prediction. 1-7 - Filippo Ziche, Nicola Bombieri:
OLORAS: Online LOng Range Action Segmentation for Edge Devices. 1-7 - Zhidan Zheng, Meng Lian, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann:
SRing: A Sub-Ring Construction Method for Application-Specific Wavelength-Routed Optical NoCs. 1-7 - Lihao Liu, Yunhui Li, Beisi Lu, Li Shang, Fan Yang:
GTN-Cell: Efficient Standard Cell Characterization Using Graph Transformer Network. 1-7 - Florian Krieger, Florian Hirner, Sujoy Sinha Roy:
Exploring Large Integer Multiplication for Cryptography Targeting In-Memory Computing. 1-7 - Junyoung Lee, Shinhyoung Jang, Seohyun Kim, Jongho Park, Ilhong Suh, Hoon Sung Chwa, Yeseong Kim:
Late Breaking Results: Dynamically Scalable Pruning for Transformer-Based Large Language Models. 1-2 - Dimosthenis Georgoulas, Yiorgos Tsiatouhas, Vasileios Tenentes:
CAS-PUF: Current-Mode Array-Type Strong PUF for Secure Computing in Area Constrained SoCs. 1-7 - Ilias Papalamprou, Aimilios Leftheriotis, Apostolis Garos, Georgios Gardikis, Maria Christopoulou, George Xilouris, Lampros Argyriou, Antonia Karamatskou, Nikolaos Papadakis, Emmanouil Kalotychos, Nikolaos Chatzivasileiadis, Dimosthenis Masouros, George Theodoridis, Dimitrios Soudris:
Multi-Partner Project: Secure Hardware Accelerated Data Analytics for 6G Networks: The PRIVATEER Approach. 1-4 - Corentin Delacour:
Self-Adaptive Ising Machines for Constrained Optimization. 1-7 - Dohun Kim, Sunghye Park, Seokhyeong Kang:
Neural Circuit Parameter Prediction for Efficient Quantum Data Loading. 1-6 - Sangbeom Jeong, Seungil Lee, Hyun Kim:
LowGradQ: Adaptive Gradient Quantization for Low-Bit CNN Training via Kernel Density Estimation-Guided Thresholding and Hardware-Efficient Stochastic Rounding Unit. 1-2 - Mehdi B. Tahoori, Jürgen Becker, Jörg Henkel, Wolfgang Kunz, Ulf Schlichtmann, Georg Sigl, Jürgen Teich, Norbert Wehn:
Multi-Partner Project: Open-Source Design Tools for Co-Development of AI Algorithms and AI Chips: (Initial Stage). 1-6 - Jiangbin Dong, Xinhua Chen, Mingyu Gao:
A Unified Vector Processing Unit for Fully Homomorphic Encryption. 1-7 - Lars Wolfgang Folkerts, Nektarios Georgios Tsoutsos:
Testing Robustness of Homomorphically Encrypted Split Model LLMs. 1-7 - Filip Masar, Vojtech Mrazek, Lukás Sekanina:
Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators. 1-2 - Samuele Germiniani, Daniele Nicoletti, Graziano Pravadelli:
A Baseline Framework for the Qualification of LTL Specification Miners. 1-7 - Bo Ding, Wei Tong, Yu Hua, Yuchong Hu, Dong Huang, Qiankun Liu, Zhangyu Chen, Xueliang Wei, Dan Feng:
MPFS: A Scalable User-Space Persistent Memory File System for Multiple Processes. 1-7 - Jacopo Sini, Mohammadreza Amel Solouki, Massimo Violante, Giorgio Di Natale:
Improving Software Reliability with Rust: Implementation for Enhanced Control Flow Checking Methods. 1-7 - Diyou Shen, Yichao Zhang, Marco Bertuletti, Luca Benini:
TCDM Burst Access: Breaking the Bandwidth Barrier in Shared-L1 RVV Clusters Beyond 1000 FPUs. 1-7 - Jiho Shin, Hoeseok Yang, Youngmin Yi:
SparseInfer: Training-free Prediction of Activation Sparsity for Fast LLM Inference. 1-7 - Andrew McCrabb, Ivris Raymond, Valeria Bertacco:
GLEAM: Graph-Based Learning Through Efficient Aggregation in Memory. 1-7 - Fatma Jebali, Caaliph Andriamisaina, Mathieu Jan, Wolfgang Ecker, Florian Egert, Bernhard Fischer, Alessio Burrello, Daniele Jahier Pagliari, Sara Vinco, Giuseppe Tagliavini, Ingo Feldner, Andreas Mauderer, Axel Sauer, Arnór Kristmundsson, Alexander Schober, Téo Bernier, Matti Käyrä, Ulf Schlichtmann, Rocco Jonack:
Multi-Partner Project: Advancing the EDA Tools Landscape for the European RISC-V Ecosystem in TRISTAN. 1-6 - Zhouquan Liu, Libo Huang, Ling Yang, Gang Chen, Wei Liu, Mingche Lai, Yongwen Wang:
Late Breaking Results: AFS: Improving Accuracy of Quantized Mamba via Aggressive Forgetting Strategy. 1-2 - Hyunseob Shin, Jaeha Kung:
FlexENM: A Flexible Encrypting-Near-Memory with Refresh-Less eDRAM-Based Multi-Mode AES. 1-7 - Tianfan Peng, Tianhua Xia, Jiajun Qin, Sai Qian Zhang:
HAAN: A Holistic Approach for Accelerating Normalization Operations in Large Language Models. 1-7 - Michael Kuhn, Patrick Schmid, Oliver Bringmann:
A Hardware-Assisted Approach for Non-Invasive and Fine-Grained Memory Power Management in MCUs. 1-7 - Zain Ul Abideen, Levent Aksoy, Samuel Pagliarini:
Late Breaking Results: Is Reconfigurable-Based Obfuscation Secure? 1-2 - Ruibin Zhou, Jian Huang, Xianping Liu, Yuhan Wang, Xinrui Zhang, Yungen Peng, Zhiyi Yu:
A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash Memory. 1-7 - Isabella Venancia Gardner, Marcel Walter, Yukio Miyasaka, Robert Wille, Michael Cochez:
Bias by Design: Diversity Quantification to Mitigate Structural Bias Effects in AIG Logic Optimization. 1-7 - Sami Ben Ali, Silviu-Ioan Filip, Olivier Sentieys, Guy G. Lemieux:
MPTorch-FPGA: A Custom Mixed-Precision Framework for FPGA-Based DNN Training. 1-7 - You Li, Guannan Zhao, Yunqi He, Hai Zhou:
DE2: SAT-Based Sequential Logic Decryption with a Functional Description. 1-7 - Manolis Katsaragakis, Orfeas Filippopoulos, Christos Sad, Dimosthenis Masouros, Dimitrios Spatharakis, Ioannis Dimolitsas, Nikos Filinis, Anastasios Zafeiropoulos, Kostas Siozios, Dimitrios Soudris, Symeon Papavassiliou:
Multi-Partner Project: Orchestrating Deployment and Real-Time Monitoring - NEPHELE Multi-Cloud Ecosystem. 1-6 - Sangyeon Kim, Hyunmin Kim, Sungju Ryu:
Thanos: Energy-Efficient Keyword Spotting Processor with Hybrid Time-Feature-Frequency-Domain Zero-Skipping. 1-7 - Prabhu Vellaisamy, Harideep Nair, Thomas Kang, Yichen Ni, Haoyang Fan, Bin Qi, Jeff Chen, R. D. Shawn Blanton, John Paul Shen:
Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. 1-7 - Jiyoon Kim, Kang Eun Jeon, Yulhwa Kim, Jong Hwan Ko:
Column-wise Quantization of Weights and Partial Sums for Accurate and Efficient Compute-In-Memory Accelerators. 1-7 - Nezam Rohbani, Mohammad Arman Soleimani, Behzad Salami, Osman S. Unsal, Adrián Cristal Kestelman, Hamid Sarbazi-Azad:
BIMAX: A Bitwise In-Memory Accelerator Using 6T-SRAM Structure. 1-7 - Cristian Turetta, Muhammad Toqeer Ali, Florenc Demrozi, Graziano Pravadelli:
A Lightweight CNN for Real-Time Pre-Impact Fall Detection. 1-7 - Juan A. Montiel-Nelson, Marco Ottella, Paolo Azzoni:
Multi-Partner Project: Enabling Digital Technologies for Holistic Health-Lifestyle Motivational and Assisted Supervision Supported by Artificial Intelligence Network (H2TRAIN). 1-7 - Jiaping Tang, Jianan Mu, Silin Liu, Zizhen Liu, Feng Gu, Xinyu Zhang, Leyan Wang, Shengwen Liang, Jing Ye, Huawei Li, Xiaowei Li:
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy. 1-7 - C. A. J. Hanselaar, M. M. Selva Kumar, Yuting Fu, Andrei Terechko, R. R. Venkatesha Prasad, Emilia Silvas:
Identification of Hazardous Driving Scenarios Using Cross-Channel Safety Performance Indicators. 1-7 - Sumit Diware, Yingzhou Dong, Mohammad Amin Yaldagard, Said Hamdioui, Rajendra Bishnoi:
Adaptive Multi-Threshold Encoding for Energy-Efficient ECG Classification Architecture Using Spiking Neural Network. 1-7 - Donguk Kim, Donkyu Baek, Yukai Chen, Enrico Macii, Massimo Poncino:
Energy-Aware Error Correction Method for Indoor Positioning and Tracking. 1-2 - Jin Xue, Yuhong Song, Yang Guo, Zili Shao:
Ensuring Data Freshness for In-Storage Computing with Cooperative Buffer Manager. 1-7 - Yingjie Zhou, Renzhi Chen, Xinyu Li, Jingkai Wang, Zhigang Fang, Bowei Wang, Wenqiang Bai, Qilin Cao, Lei Wang:
VToT: Automatic Verilog Generation via LLMs with Tree of Thoughts Prompting. 1-2 - Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar:
Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. 1-7 - Huize Li, Dan Chen, Tulika Mitra:
HyAtten: Hybrid Photonic-Digital Architecture for Accelerating Attention Mechanism. 1-7 - Liangji Wu, Shuaibo Huang, Ziqi Wang, Shiyang Wu, Yang Chen, Hao Yan, Longxing Shi:
An Imitation Augmented Reinforcement Learning Framework for CGRA Design Space Exploration. 1-7 - Pingchuan Ma, Zhengqi Gao, Meng Zhang, Haoyu Yang, Mark Ren, Z. Rena Huang, Duane S. Boning, Jiaqi Gu:
MAPS: Multi-Fidelity AI-Augmented Photonic Simulation and Inverse Design Infrastructure. 1-6 - Jamin Seo, Akshat Ramachandran, Yu-Chuan Chuang, Anirudh Itagi, Tushar Krishna:
AIRCHITECT v2: Learning the Hardware Accelerator Design Space Through Unified Representations. 1-7 - Luca Davoli, Laura Belli, Veronica Mattioli, Riccardo Raheli, Gianluigi Ferrari, Lorenzo Priano, Jaromir Hubalek, Lukás Smital, Andrea Nemcová, Daniela Chlibkova, Vlastimil Benes, Johan Plomp:
Multi-Partner Project: Sports Performance and Health Assessment in the DistriMuse Project. 1-7 - Sohan Salahuddin Mugdho, Yuanbo Guo, Ethan G. Rogers, Weiwei Zhao, Yiyu Shi, Cheng Wang:
FairXbar: Improving the Fairness of Deep Neural Networks with Non-Ideal in-Memory Computing Hardware. 1-7 - Songyu Feng, Mo Zou, Tian Zhi, Zidong Du:
CISGraph: A Contribution-Driven Accelerator for Pairwise Streaming Graph Analytics. 1-7 - Weikai Xu, Meng Li, Qianqian Huang, Ru Huang:
Compact Non-Volatile Lookup Table Architecture Based on Ferroelectric FET Array Through In-Situ Combinatorial One-Hot Encoding for Reconfigurable Computing. 1-7 - Aoxiang Qin, Minghua Shen, Nong Xiao:
Operation Dependency Graph-Based Scheduling for High-Level Synthesis. 1-7 - Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti:
SoftEx: A Low Power and Flexible Softmax Accelerator with Fast Approximate Exponentiation. 1-2 - Wei Wang, Hongxu Jiang, Runhua Zhang, Yongxiang Cao, Yaochen Han:
SparDR: Accelerating Unstructured Sparse DNN Inference via Dataflow Optimization. 1-7 - Alessio Bucaioni, Romina Eramo, Luca Berardinelli, Hugo Bruneliere, Benoît Combemale, Djamel Eddine Khelladi, Vittoriano Muttillo, Andrey Sadovykh, Manuel Wimmer:
Multi-Partner Project: A Model-Driven Engineering Framework for Federated Digital Twins of Industrial Systems (MATISSE). 1-6 - Chenlin Ma, Xiaochuan Zheng, Kaoyi Sun, Tianyu Wang, Yi Wang:
EF-IMR: Embedded Flash with Interlaced Magnetic Recording Technology. 1-2 - Spyridon Raptis, Haralampos-G. Stratigopoulos:
Minimum Time Maximum Fault Coverage Testing of Spiking Neural Networks. 1-7 - Hao Liu, Qing Wang, Marco Zuniga:
SolarML: Optimizing Sensing and Inference for Solar-Powered TinyML Platforms. 1-7 - Yuying Zhang, Sharad Sinha, Jiang Xu, Wei Zhang:
UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE. 1-7 - Bo Zhou, Mengxi Liu, Sizhen Bian, Daniel Geißler, Paul Lukowicz, José Miranda, Jonathan Dan, David Atienza, Mohamed Amine Riahi, Norbert Wehn, Russel N. Torah, Sheng Yong, Jidong Liu, Stephen P. Beeby, Magdalena Kohler, Berit Greinke, Junchun Yu, Vincent Nierstrasz, Leila Sheldrick, Rebecca Stewart, Tommaso Nieri, Matteo Maccanti, Daniele Spinelli:
Multi-Partner Project: Sustainable Textile Electronics (STELEC). 1-5 - Taehoon Kim, Minjeong Kim, Hankyu Chi, Byungjun Kang, Eunji Song, Woo-Seok Choi:
ML-Based Fast and Accurate Performance Modeling and Prediction for High-Speed Memory Interfaces Across Different Technologies. 1-7 - Adrian Evans, Victor Roux-Sibillon, Joe Saad, Ivan Miro-Panades, Tetiana Aksenova, Lorena Anghel:
Enabling a Portable Brain Computer Interface for Rehabilitation of Spinal Cord Injuries. 1-2 - Sungheon Jeong, Hamza Errahmouni Barkam, Sanggeon Yun, Yeseong Kim, Shaahin Angizi, Mohsen Imani:
Exploiting Boosting in Hyperdimensional Computing for Enhanced Reliability in Healthcare. 1-7 - Niko Zurstraßen, Nils Bosbach, Lennart M. Reimann, Rainer Leupers:
Static Global Register Allocation for Dynamic Binary Translators. 1-6 - Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic:
SimGen: Simulation Pattern Generation for Efficient Equivalence Checking. 1-7 - Yuchao Wu, Weilong Guan, Yeyu Tong, Yuzhe Ma:
Automatic Routing for Photonic Integrated Circuits Under Delay Matching Constraints. 1-2 - Hao Zhang, Yiwen Gao, Yongbin Zhou, Jingdian Ming:
Side-Channel Collision Attacks Against ASCON. 1-6 - Ruiqi Chen, Jiayu Liu, Shidi Tang, Yang Liu, Yanxiang Zhu, Ming Ling, Bruno Da Silva:
ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization. 1-6 - Bokyung Kim:
A DRAM-Based Processing-in-Memory Accelerator for Privacy-Protecting Machine Learning. 1-2 - Shlomo Engelberg, Osnat Keren:
PESEC - A Simple Power-Efficient Single Error Correcting Coding Scheme for RRAM. 1-7 - Niels Mook, Erwin de Kock, Bas Arts, Soham Chakraborty, Arie van Deursen:
Modeling and Analysis Technique for the Formal Verification of System-on-Chip Address Maps: Extended Abstract. 1-2 - Yongchao Liu, Lianlong Sun, Michael C. Huang, Hui Wu:
Integrated Hardware Annealing Based on Langevin Dynamics for Ising Machines. 1-6 - Wenjing Jiang, Jin Yan, Sachin S. Sapatnekar:
ML-Based AIG Timing Prediction to Enhance Logic Optimization. 1-2 - Yiyao Yang, Fu Teng, Pengju Liu, Mengnan Qi, Chenyang Lv, Ji Li, Xuhong Zhang, Zhezhi He:
HaVen: Hallucination-Mitigated LLM for Verilog Code Generation Aligned with HDL Engineers. 1-7 - Kuangjie Zou, Yifan Zhang, Zicheng Zhang, Guoyu Li, Jianli Chen, Kun Wang, Jun Yu:
PreVV: Eliminating Store Queue via Premature Value Validation for Dataflow Circuit on FPGA. 1-7 - Tingting Li, Ziming Zhao, Liqiang Lu, Siwei Tan, Jianwei Yin:
Empowering Quantum Error Traceability with MoE for Automatic Calibration. 1-7 - Xuan Tang, Zicong Wang, Shuiyi He, Dezun Dong, Xiangke Liao:
Amphi: Practical and Intelligent Data Prefetching for the First-Level Cache. 1-2 - Yiming Ma, Chaoyao Shen, Linfeng Jiang, Tao Xu, Meng Zhang:
TKD: An Efficient Deep Learning Compiler with Cross-Device Knowledge Distillation. 1-7 - Jiseung Kim, Hyunsei Lee, Tajana Rosing, Mohsen Imani, Yeseong Kim:
Late Breaking Results: Hyperdimensional Regression with Fine-Grained and Scalable Confidence-Based Learning. 1-2 - Jianing Zheng, Gang Chen:
LoopLynx: A Scalable Dataflow Architecture for Efficient LLM Inference. 1-7 - Renjie Wei, Songqiang Xu, Linfeng Zhong, Zebin Yang, Qingyu Guo, Yuan Wang, Runsheng Wang, Meng Li:
LightMamba: Efficient Mamba Acceleration on FPGA with Quantization and Hardware Co-design. 1-7 - Lichao Wu, Mohamadreza Rostami, Huimin Li, Ahmad-Reza Sadeghi:
HFL: Hardware Fuzzing Loop with Reinforcement Learning. 1-7 - Marie-Aïnhoa Nicolas, Jordane Lorandel, Christophe Moy:
Late Breaking Results: SoC-FPGA HW Trojan Leaking Data through EM Covert Channel. 1-2 - Jindong Li, Tenglong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng:
Pushing up to the Limit of Memory Bandwidth and Capacity Utilization for Efficient LLM Decoding on Embedded FPGA. 1-7 - Seungho Lee, Donghyun Nam, Jeongwoo Park:
RGHT-Q: Reconfigurable GEMM Unit for Heterogeneous-Homogeneous Tensor Quantization. 1-2 - Yuanfang Wang, Yu Li, Jianli Chen, Jun Yu, Kun Wang:
FAMERS: An FPGA Accelerator for Memory-Efficient Edge-Rendered 3D Gaussian Splatting. 1-7 - Gyeonghwan Park, Sanghyeok Han, Byungkuk Yoon, Jae-Joon Kim:
DOTS: DRAM-PIM Optimization for Tall and Skinny GEMM Operations in LLM Inference. 1-2 - Haomin Li, Fangxin Liu, Zongwu Wang, Dongxu Lyu, Shiyuan Huang, Ning Yang, Qi Sun, Zhuoran Song, Li Jiang:
TAIL: Exploiting Temporal Asynchronous Execution for Efficient Spiking Neural Networks with Inter-Layer Parallelism. 1-7 - Gongjian Sun, Mingyu Yan, Dengke Han, Runzhen Xue, Xiaochun Ye, Dongrui Fan:
LiGNN: Accelerating GNN Training Through Locality-Aware Dropout. 1-7 - Inhwan Lee, Jehun Lee, Jaeyong Jang, Jae-Joon Kim:
An eDRAM Digital In-Memory Neural Network Accelerator for High-Throughput and Extended Data Retention Time. 1-7 - Lizi Zhang, Azadeh Davoodi, Rasit Onur Topaloglu:
ReBERT: LLM for Gate-Level to Word-Level Reverse Engineering. 1-7 - Yanfang Liu, Wei W. Xing:
FUSIS: Fusing Surrogate Models and Importance Sampling for Efficient Yield Estimation. 1-7 - Nicholas Wendt, Mahesh Ketkar, Valeria Bertacco:
SPIRE: Inferring Hardware Bottlenecks from Performance Counter Data. 1-7 - William H. Widen, Marilyn Claire Wolf:
Law as a Design Consideration for Automated Vehicles Suitable to Transport Intoxicated Persons. 1-7 - Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection. 1-7 - Fangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, Qi Sun, Li Jiang:
OPS: Outlier-Aware Precision-Slice Framework for LLM Acceleration. 1-2 - Tianyi Li, Zhexin Tang, Tao Wu, Bei Yu, Jingyi Yu, Hao Geng:
LLM-SRAF: Sub-Resolution Assist Feature Generation Using Large Language Model. 1-7 - Salma Afifi, Ishan G. Thakkar, Sudeep Pasricha:
SafeLight: Enhancing Security in Optical Convolutional Neural Network Accelerators. 1-7 - Yi Zhong, Zilin Wang, Yipeng Gao, Xiaoxin Cui, Xing Zhang, Yuan Wang:
NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing. 1-7 - Wenyong Zhou, Zhengwu Liu, Taiqiang Wu, Chenchen Ding, Yuan Ren, Ngai Wong:
Towards Robust RRAM-Based Vision Transformer Models with Noise-Aware Knowledge Distillation. 1-2 - Zhixin Pan, Ziyu Shu:
Hardware-Assisted Ransomware Detection Using Automated Machine Learning. 1-7 - Enhao Tang, Shun Li, Hao Zhou, Guohao Dai, Jun Lin, Kun Wang:
AiSpGEMM: Accelerating Imbalanced SpGEMM on FPGAs with Flexible Interconnect and Intra-row Parallel Merging. 1-7 - Seohyun Kim, Jang Hyun Kim, Jongmin Lee:
A Synthesizable Thyristor-Like Leakage-Based True Random Number Generator. 1-7 - Chengxuan Yu, Yanshuang Teng, Wenhao Dai, Yongjiang Li, Wei W. Xing, Xiao Wu, Dan Niu, Zhou Jin:
LaRED: Efficient IR Drop Predictor with Layout-Preserving Rebuilder-Encoder-Decoder Architecture. 1-7 - Tianchu Dong, Shaoxuan Li, Yihang Zuo, Hongwu Jiang, Yuzhe Ma, Shanshi Huang:
OpenC2: An Open-Source End-to-End Hardware Compiler Development Framework for Digital Compute-in-Memory Macro. 1-2 - Yilmaz Ege Gonul, Baris Taskin:
A Multi-Stage Potts Machine Based on Coupled CMOS Ring Oscillators. 1-7 - Munhyeon Kim, Yulhwa Kim, Jae-Joon Kim:
Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cells. 1-7 - Jing Li, Bingrui Zhang, Yuquan Sun, Wei Xing, Yuanqing Cheng:
Cool3D: Cost-Optimized and Efficient Liquid Cooling for 3D Integrated Circuits. 1-7 - Spyridon Besias, Ilias Sertaridis, Florentia Afentaki, Konstantinos Balaskas, Georgios Zervakis:
Late Breaking Results: Energy-Efficient Printed Machine Learning Classifiers with Sequential SVMs. 1-2 - Xilong Xie, Liang Wang, Limin Xiao, Meng Han, Lin Sun, Shuai Zheng, Xiangrong Xu:
FineQ: Software-Hardware Co-Design for Low-Bit Fine-Grained Mixed-Precision Quantization of LLMs. 1-7 - Mohamed Alla Eddine Bahi, Maria Mendez Real, Maxime Pelcat:
Comb Frequency Division Multiplexing: A Non-Binary Modulation for AirGap Covert Channel Transmission. 1-2 - Cheng Gu, Gang Li, Xiaolong Lin, Jiayao Ling, Jian Cheng, Xiaoyao Liang:
BMP-SD: Marrying Binary and Mixed-Precision Quantization for Efficient Stable Diffusion Inference. 1-7 - Tianyi Yu, Zhonghao Chen, Yiming Chen, Shuang Wang, Yongpan Liu, Huazhong Yang, Xueqing Li:
DSC-ROM: A Fully Digital Sparsity-Compressed Compute-in-ROM Architecture for on-Chip Deployment of Large-Scale DNNs. 1-6 - Yukai Chen, Subrat Mishra, Julien Ryckaert, Dwaipayan Biswas, James Myers:
Late Breaking Results: Thermal Feasibility of Backside Integrated LDOs in 2.5D/3D System-in-Package Using Nanosheet Technology. 1-2 - Hunjong Lee, Jihun Lee, Jaewon Seo, Yunho Oh, Myung Kuk Yoon, Gunjae Koo:
HyMM: A Hybrid Sparse-Dense Matrix Multiplication Accelerator for GCNs. 1-7 - Sophie Andrews, Matthew Sotoudeh, Clark Barrett:
Efficient SAT-Based Bounded Model Checking of Evolving Systems. 1-7 - Jinyi Shen, Fan Yang, Li Shang, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng:
INTO-OA: Interpretable Topology Optimization for Operational Amplifiers. 1-7 - Xiaohan Jiang, Yinyi Liu, Peiyu Chen, Wei Zhang, Jiang Xu:
PICELF: An Automatic Electronic Layer Layout Generation Framework for Photonic Integrated Circuits. 1-7 - Simon Hofmann, Marcel Walter, Robert Wille:
Late Breaking Results: Physical Co-Design for Field-Coupled Nanocomputing. 1-2 - Quan Cheng, Wang Liao, Ruilin Zhang, Hao Yu, Longyang Lin, Masanori Hashimoto:
HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation. 1-7 - Hao Wang, Erjia Xiao, Songhuan He, Zhongyi Ni, Lingfeng Zhang, Xiaokun Zhan, Yifei Cui, Jinguo Liu, Cheng Wang, Zhongrui Wang, Renjing Xu:
CIM-Based Parallel Fully FFNN Surface Code High-Level Decoder for Quantum Error Correction. 1-2 - Dingcui Yu, Jialin Liu, Yumiao Zhao, Wentong Li, Ziang Huang, Zonghuan Yan, Mengyang Ma, Liang Shi:
ConZone: A Zoned Flash Storage Emulator for Consumer Devices. 1-7 - Kentaroh Katoh, Toru Nakura, Haruo Kobayashi:
A 10ps-Order Flexible Resolution Time-to-Digital Converter with Linearity Calibration and Legacy FPGA. 1-2 - Geancarlo Abich:
Assessing Soft Error Reliability in Vectorized Kernels: Vulnerability and Performance Trade-Offs on Arm and RISC-V ISAs. 1-2 - Kevin Lopez, Amin Rezaei:
Cute-Lock: Behavioral and Structural Multi-Key Logic Locking Using Time Base Keys. 1-7 - Shamiul Alam, Ahmedullah Aziz:
Ferroelectric-Superconducting Synergy for Future Computing. 1-6 - Abhishek Balasubramaniam, Febin P. Sunny, Sudeep Pasricha:
UPAQ: A Framework for Real-Time and Energy-Efficient 3D Object Detection in Autonomous Vehicles. 1-7 - Anurup Saha, Chandramouli N. Amarnath, Kwondo Ma, Abhijit Chatterjee:
EGIS: Entropy Guided Image Synthesis for Dataset-Agnostic Testing of RRAM-Based DNNs. 1-7 - Ruofei Tang, Xuliang Zhu, Lei Chen, Xing Li, Xin Huang, Mingxuan Yuan, Jianliang Xu:
Maximum Fanout-Free Window Enumeration: Towards Multi-Output Sub-Structure Synthesis. 1-7 - Seongsik Park, Jongkil Park, Hyun Jae Jang, Jaewook Kim, YeonJoo Jeong, Gye Weon Hwang, Inho Kim, Jong-Keuk Park, Kyeong Seok Lee, Suyoun Lee:
Late Breaking Results: Improving Deep SNNs with Gradient Clipping and Noise Exploitation in Neuromorphic Devices. 1-2 - Louis Savary, Simon Rokicki, Steven Derrien:
Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores. 1-7 - Hongyang Pan, Keren Zhu, Fan Yang, Zhufei Chu, Xuan Zeng:
ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis. 1-7 - Aikaterini Maria Panteleaki, Konstantinos Balaskas, Georgios Zervakis, Hussam Amrouch, Iraklis Anagnostopoulos:
Late Breaking Results: Leveraging Approximate Computing for Carbon-Aware DNN Accelerators. 1-2 - Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang:
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. 1-7 - Ranyang Zhou, Jacqueline T. Liu, Sabbir Ahmed, Shaahin Angizi, Adnan Siraj Rakin:
Compromising the Intelligence of Modern DNNs: On the Effectiveness of Targeted RowPress. 1-7 - Sanggeon Yun, Ryozo Masukawa, William Youngwoo Chung, Minhyoung Na, Nathaniel D. Bastian, Mohsen Imani:
Continuous GNN-Based Anomaly Detection on Edge Using Efficient Adaptive Knowledge Graph Learning. 1-7 - Milad Kokhazadeh, Georgios Keramidas, Vasilios I. Kelefouras, Iakovos Stamoulis:
A CNN Compression Methodology for Layer-Wise Rank Selection Considering Inter-Layer Interactions. 1-7 - Penghao Sun, Shengan Zheng, Kaijiang Deng, Guifeng Wang, Jin Pu, Jie Yang, Maojun Yuan, Feng Zhu, Shu Li, Linpeng Huang:
TxISC: Transactional File Processing in Computational SSDs. 1-7 - Chongyi Yang, Bohan Hu, Peiyu Chen, Yinyi Liu, Wei Zhang, Jiang Xu:
BEAM: A Multi-Channel Optical Interconnect for Multi-GPU Systems. 1-7 - Xiaolu Hu, Xinkuang Geng, Zhigang Mao, Jie Han, Honglan Jiang:
A Low-Power Mixed-Precision Integrated Multiply-Accumulate Architecture for Quantized Deep Neural Networks. 1-7 - Zhangying He, Hossein Sayadi:
REACT: Randomized Encryption with AI-Controlled Targeting for Next-Gen Secure Communication. 1-2 - Hagen Heermann, Christoph Grimm:
Bridging the Gap Between Anomaly Detection and Runtime Verification: H-Classifiers. 1-7 - Alessandra Dolmeta, Stefano Di Matteo, Emanuele Valea, Mikael Carmona, Antoine Loiseau, Maurizio Martina, Guido Masera:
TYRCA: A RISC-V Tightly-Coupled Accelerator for Code-Based Cryptography. 1-7 - Yi Fan, Yajuan Du, Sam H. Noh:
RemapCom: Optimizing Compaction Performance of LSM Trees via Data Block Remapping in SSDs. 1-7 - Eduardo Ortega, Jungyoun Kwak, Shimeng Yu, Krishnendu Chakrabarty:
Runtime Security Analysis of Monolithic 3D Embedded DRAM with Oxide-Channel Transistor. 1-7 - Akhil Singampalli, Danish Gufran, Sudeep Pasricha:
SAFELOC: Overcoming Data Poisoning Attacks in Heterogeneous Federated Machine Learning for Indoor Localization. 1-7 - Rajendra Bishnoi, Mohammad Amin Yaldagard, Said Hamdioui, Kanishkan Vadivel, Manolis Sifalakis, Nicolas Daniel Rodriguez, Pedro Julián, Lothar Ratschbacher, Maen Mallah, Yogesh Ramesh Patil, Rashid Ali, Fabian Chersi:
Multi-Partner Project: A Deep Learning Platform Targeting Embedded Hardware for Edge-AI Applications (NEUROKIT2E). 1-7 - Nicolas Bohm Agostini, Connah G. M. Johnson, William R. Cannon, Antonino Tumeo:
ChemComp: Compiling and Computing with Chemical Reaction Networks. 1-7 - Anouar Nechi, Yasin Ghafourian, Belal Abu-Naim, Thomas Gutt, George Dimitrakopoulos, Amira Moualhi, Mladen Berekovic, Pál Varga, Markus Tauber:
Multi-Partner Project: Artificial Intelligence in Manufacturing Leading to Sustainability and the Consideration of Human Aspects (AIMS5.0). 1-4 - Yanfeng Yang, Yi Zou, Zhibiao Xue, Liuyang Zhang:
SHWCIM: A Scalable Heterogeneous Workload Computing-in-Memory Architecture. 1-7 - Sven Argo, Henk Corporaal, Alejandro Garza, Marc Geilen, Manil Dev Gomony, Tim Güneysu, Adrian Marotzke, Fouwad Jamil Mir, Jan Richter-Brockmann, Jeffrey Smith, Mottaqiallah Taouil, Said Hamdioui:
Multi-Partner Project: Securing Future Edge-AI Processors in Practice (CONVOLVE). 1-7 - Yu-En Lin, Yi-Yu Liu:
Wire-Bonding Finger Placement for FBGA Substrate Layout Design with Finger Orientation Consideration. 1-6 - Jiayu Yang, Luyi Guo, Yicheng Li, Wang Wang, Zixu Li, Manni Li, Zijian Huang, Yinyin Lin, Yun Yin, Hongtao Xu:
Linearization of Quadrature Digital Power Amplifiers by Neural Network of ULR_LSTM: Unsupervised Learning Residual LSTM. 1-7 - Sukhyun Han, Seongwook Kim, Gwangeun Byeon, Jihun Yoon, Seokin Hong:
Zebra: Leveraging Diagonal Attention Pattern for Vision Transformer Accelerator. 1-7 - Prashanth Mohan, Siddharth Das, Oguz Atli, Josh Joffrion, Ken Mai:
A Soft Error Tolerant Flip-Flop for eFPGA Configuration Hardening in 22nm FinFET Process. 1-6 - Xinkuang Geng, Siting Liu, Hui Wang, Jie Han, Honglan Jiang:
Lookup Table Refactoring: Towards Efficient Logarithmic Number System Addition for Large Language Models. 1-7 - Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Jan Henrik Weinstock, Lukas Jünger, Rainer Leupers:
High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms. 1-7 - Yayue Hou, Hsinyu Tsai, Kaoutar El Maghraoui, Tayfun Gokmen, Geoffrey W. Burr, Liu Liu:
NORA: Noise-Optimized Rescaling of LLMs on Analog Compute-in-Memory Accelerators. 1-7 - Francesco Biondani, Luigi Capogrosso, Nicola Dall'Ora, Enrico Fraccaroli, Marco Cristani, Franco Fummi:
Human-Centered Digital Twin for Industry 5.0. 1-2 - Afolabi Ige, Jennifer Hasler:
ASHES 1.5: Analog Computing Synthesis for FPAAs and ASICs. 1-6 - Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni:
Enabling SNN-Based Near-MEA Neural Decoding with Channel Selection: An Open-HW Approach. 1-7 - Hemin Rahimi, Amir Moradi:
One More Motivation to Use Evaluation Tools This Time for Hardware Multiplicative Masking of AES. 1-7 - Qingcai Jiang, Buxin Tu, Hong An:
NDPage: Efficient Address Translation for Near-Data Processing Architectures via Tailored Page Table. 1-7 - Fangxin Liu, Haomin Li, Zongwu Wang, Dongxu Lyu, Li Jiang:
HyperDyn: Dynamic Dimensional Masking for Efficient Hyper-Dimensional Computing. 1-7 - Zhantong Zhu, Hongou Li, Wenjie Ren, Meng Wu, Le Ye, Ru Huang, Tianyu Jia:
Leveraging Compute-in-Memory for Efficient Generative Model Inference in TPUs. 1-7 - Haiyun Li, Jixin Zhang:
MegaRoute: Universal Automated Large-Scale PCB Routing Method with Adaptive Step-Size Search. 1-7 - Hao Chen, Yuzhe Ma, Yeyu Tong:
Bi-Level Optimization Accelerated DRC-Aware Physical Design Automation for Photonic Devices. 1-7 - Pingchuan Ma, Zhengqi Gao, Amir Begovic, Meng Zhang, Haoyu Yang, Haoxing Ren, Z. Rena Huang, Duane S. Boning, Jiaqi Gu:
BOSON-1: Understanding and Enabling Physically-Robust Photonic Inverse Design with Adaptive Variation-Aware Subspace Optimization. 1-7 - Mohanad Odema, Luke Chen, Hyoukjun Kwon, Mohammad Abdullah Al Faruque:
Performance Implications of Multi-Chiplet Neural Processing Units on Autonomous Driving Perception. 1-7 - Jihoon Park, Jeongin Choe, Dohyun Kim, Jae-Joon Kim:
COMPASS: A Compiler Framework for Resource-Constrained Crossbar-Array Based In-Memory Deep Learning Accelerators. 1-7 - Jai-Ming Lin, Zong-Ze Lee, Nan-Chu Lin:
Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RL. 1-7 - Mohammadamin Hajikhodaverdian, Sherief Reda, Ayse K. Coskun:
Fast Machine Learning Based Prediction for Temperature Simulation Using Compact Models. 1-2 - Giovanni Pollo, Alessio Burrello, Enrico Macii, Massimo Poncino, Sara Vinco, Daniele Jahier Pagliari:
Coupling Neural Networks and Physics Equations For Li-Ion Battery State-of-Charge Prediction. 1-7 - Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang:
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC. 1-7 - Kang Eun Jeon, Johnny Rhe, Jong Hwan Ko:
Low-Rank Compression for IMC Arrays. 1-7 - Junyao Zhang, Guanglei Zhou, Feng Cheng, Jonathan Ku, Qi Ding, Jiaqi Gu, Hanrui Wang, Hai Helen Li, Yiran Chen:
qGDP: Quantum Legalization and Detailed Placement for Superconducting Quantum Computers. 1-7 - Zhiyuan Yan, Hongce Zhang:
Word-Level Counterexample Reduction Methods for Hardware Verification. 1-7 - Aibin Yan, Wangjin Jiang, Han Bao, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard:
NVSRLO: A FeFET-Based Non-Volatile and SEU-Recoverable Latch Design with Optimized Overhead. 1-2 - Yannick Stade, Ludwig Schmid, Lukas Burgholzer, Robert Wille:
Optimal State Preparation for Logical Arrays on Zoned Neutral Atom Quantum Computers. 1-7 - Shivam Bhasin, Dirmanto Jap, Prasanna Ravi, Marina Krcek, Stjepan Picek:
Late Breaking Results: Practical Electromagnetic Fault Injection on Intel Neural Compute Stick 2. 1-2 - Danielle Grey-Stewart, David Kong, Mariam Elgamal, Georgios Kyriazidis, Jalil Morris, Gage Hills:
Quantifying Trade-Offs in Power, Performance, Area, and Total Carbon Footprint of Future Three-Dimensional Integrated Computing Systems. 1-7 - Haisheng Zheng, Haoyuan Wu, Zhuolun He, Yuzhe Ma, Bei Yu:
iRw: An Intelligent Rewriting. 1-2 - Oguzhan Herkiloglu, Ali Serdar Atalay, Ibrahim Arif, Salih Ergün, Alper Kanak:
Multi-Partner Project: BIM-Powered Environmental Data Agent for More Resilient and Trustworthy Data Centers. 1-4 - Xuqi Zhu, Jiacheng Zhu, Huaizhi Zhang, Tamim M. Al-Hasan, Klaus D. McDonald-Maier, Xiaojun Zhai:
Late Breaking Results: Approximated LUT-Based Neural Networks for FPGA Accelerated Inference. 1-2 - Hengrui Zhao, Lei Xun, Jagmohan Chauhan, Geoff V. Merrett:
Power- and Deadline-Aware Dynamic Inference on Intermittent Computing Systems. 1-7 - Arash Ardakani, Minwoo Kang, Kevin He, Qijing Huang, John Wawrzynek:
High-Throughput SAT Sampling. 1-7 - Ruiyang Qin, Pengyu Ren, Zheyu Yan, Liu Liu, Dancheng Liu, Amir Nassereldine, Jinjun Xiong, Kai Ni, X. Sharon Hu, Yiyu Shi:
NVCiM-PT: An NVCiM-Assisted Prompt Tuning Framework for Edge LLMs. 1-7 - Kiho Chung, Youjin Choi, Donguk Seo, Yoonmyung Lee:
An Efficient On-Chip Reference Search and Optimization Algorithms for Variation-Tolerant STT-MRAM Read. 1-7 - Taehwan Kim, Jongsun Park:
Speeding-Up Successive Read Operations of STT-MRAM via Read Path Alternation for Delay Symmetry. 1-2 - Boyan Chen, Qingni Shen, Lei Xue, Jiarui She, Xiaolei Zhang, Xiapu Luo, Xin Zhang, Wei Chen, Zhonghai Wu:
SACK: Enabling Environmental Situation-Aware Access Control for Vehicles in Linux Kernel. 1-7 - Do Yeong Kang, Yeong Hwan Oh, Chanwook Hwang, Jinhee Kim, Kang Eun Jeon, Jong Hwan Ko:
MEMHD: Memory-Efficient Multi-Centroid Hyperdimensional Computing for Fully-Utilized In-Memory Computing Architectures. 1-7 - Cristina Silvano, Fabrizio Ferrandi, Serena Curzel, Daniele Ielmini, Stefania Perri, Fanny Spagnolo, Pasquale Corsonello, Sebastiano Fabio Schifano, Cristian Zambelli, Angelo Garofalo, Francesco Conti, Luca Benini:
Multi-Partner Project: Architectures and Design Methodologies to Accelerate AI Workloads. The ICSC Flagship 2 Project. 1-7 - Sashidhar Jakkamsetti, Youngil Kim, Andrew Searles, Gene Tsudik:
EILID: Execution Integrity for Low-end IoT Devices. 1-7 - Douglas J. Townsell, Mimi Xie, Bin Wang, Fathi Amsaad, Varshitha Reddy Thanam, Wen Zhang:
AeroDiffusion: Complex Aerial Image Synthesis with Keypoint-Aware Text Descriptions and Feature-Augmented Diffusion Models. 1-7 - Sören Tempel, Tobias Brandt, Christoph Lüth, Christian Dietrich, Rolf Drechsler:
Accurate and Extensible Symbolic Execution of Binary Code Based on Formal ISA Semantics. 1-7 - Amit Ranjan Trivedi, Sina Tayebati, Hemant Kumawat, Nastaran Darabi, Divake Kumar, Adarsh Kumar Kosta, Yeshwanth Venkatesha, Dinithi Jayasuriya, Nethmi Jayasinghe, Priyadarshini Panda, Saibal Mukhopadhyay, Kaushik Roy:
Intelligent Sensing-to-Action for Robust Autonomy at the Edge: Opportunities and Challenges. 1-10 - Wanru Mao, Hanjie Liu, Guangyao Wang, Tianshuo Bai, Jingcheng Gu, Han Zhang, Xitong Yang, Aifei Zhang, Xiaohang Wei, Meng Wang, Wang Kang:
HyIMC: Analog-Digital Hybrid In-Memory Computing SoC for High-Quality Low-Latency Speech Enhancement. 1-2 - Lakshmi Likhitha Mankali, Jitendra Bhandari, Manaar Alam, Ramesh Karri, Michail Maniatakos, Ozgur Sinanoglu, Johann Knechtel:
RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation. 1-7 - Jintao Chen, Yuankai Xu, Yinchen Ni, An Zou, Yehan Ma:
RICH: Heterogeneous Computing for Real-Time Intelligent Control. 1-7 - Mason Conkel, Wen Zhang, Mimi Xie, Yufang Jin, Chen Pan:
Autonomous UAV-Assisted IoT Systems with Deep Reinforcement Learning Based Data Ferry. 1-7 - Lanlan Cui, Yichuan Wang, Renzhi Xiao, Miao Li, Xiaoxue Liu, Xinhong Hei:
DHD: Double Hard Decision Decoding Scheme for NAND Flash Memory. 1-7 - Erxiang Ren, Cheng Qu, Li Luo, Yonghua Li, Zheyu Liu, Xinghua Yang, Qi Wei, Fei Qiao:
Dcha: Distributed-Centralized Heterogeneous Architecture Enables Efficient Multi-Task Processing for Smart Sensing. 1-7 - Shunxiang Lan, Min Tang, Jun Ma:
Flexible Thermal Conductance Model (TCM) for Efficient Thermal Simulation of 3-D ICs and Packages. 1-6 - Johannes Geier, Leonidas Kontopoulos, Daniel Mueller-Gritschneder, Ulf Schlichtmann:
Rapid Fault Injection Simulation by Hash-Based Differential Fault Effect Equivalence Checks. 1-7 - Michelangelo Bartolomucci, David Kingston, Teo Cupaiuolo, Alessandra Nardi, Riccardo Cantoro:
Early Functional Safety and PPA Evaluation of Digital Designs. 1-2 - Ilia Polian, Xianyue Zhao, Li-Wei Chen, Felix Bayhurst, Ziang Chen, Heidemarie Schmidt, Nan Du:
Optimal Synthesis of Memristive Mixed-Mode Circuits. 1-7 - Lishuo Deng, Changwei Yan, Cai Li, Zhuo Chen, Weiwei Shan:
Efficient Hold Buffer Optimization by Supply Noise-Aware Dynamic Timing Analysis. 1-7 - Jakub Lojda, Josef Strnadel, Pavel Smrz, Václav Simek:
Multi-Partner Project: LoLiPoP-IoT - Design and Simulation of Energy-Efficient Devices for the Internet of Things. 1-7 - Heng Liu, Ming Han, Jin Wu, Ye Wang, Jian Dong:
MCTA: A Multi-Stage Co-Optimized Transformer Accelerator with Energy-Efficient Dynamic Sparse Optimization. 1-7 - Dekang Zhang, Dan Niu, Zhou Jin, Yichao Dong, Jingweijia Tan, Changyin Sun:
A Novel Frequency-Spatial Domain Aware Network for Fast Thermal Prediction in 2.5D ICs. 1-7 - Yunqi Shi, Siyuan Xu, Shixiong Kai, Xi Lin, Ke Xue, Mingxuan Yuan, Chao Qian:
Timing-Driven Global Placement by Efficient Critical Path Extraction. 1-7 - Yizhou Shi, Liying Li, Yue Zeng, Peijin Cong, Junlong Zhou:
Joint DNN Partition and Thread Allocation Optimization for Energy-Harvesting MEC Systems. 1-7 - Gaurav Narang, Janardhan Rao Doppa, Partha Pratim Pande:
Odin: Learning to Optimize Operation Unit Configuration for Energy-efficient DNN Inferencing. 1-7 - Hao Gu, Xinglin Zheng, Youwen Wang, Keyu Peng, Ziran Zhu, Jun Yang:
Multiscale Feature Attention and Transformer Based Congestion Prediction for Routability-Driven FPGA Macro Placement. 1-7 - Shuanglong Liu, Shiyu Peng, Wan Shen:
FPGA-Based Acceleration of MCMC Algorithm through Self-Shrinking for Big Data. 1-7 - Wenqing Wang, Ziming Chen, Quan Deng, Liang Fang:
PFP: Parallel Floating-Point Vector Multiplication Acceleration in MAGIC ReRAM. 1-7 - Dhruv Thapar, Arjun Chaudhuri, Christopher Bailey, Ravi Mahajan, Krishnendu Chakrabarty:
On the Impact of Warpage on BEOL Geometry and Path Delays in Fan-out Wafer-Level Packaging. 1-2 - Xinkuang Geng, Yunjie Lu, Hui Wang, Honglan Jiang:
Segment-Wise Accumulation: Low-Error Logarithmic Domain Computing for Efficient Large Language Model Inference. 1-7 - Ashish Reddy Bommana, Farshad Firouzi, Chukwufumnanya Ogbogu, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
DEAR: Dependable 3D Architecture for Robust DNN Training. 1-7 - Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. 1-7 - Omar Sharif, Christos-Savvas Bouganis:
A Resource-Aware Residual-Based Gaussian Belief Propagation Accelerator Toolflow. 1-7 - Tiago Rocha, Nuno Neves, Nuno Roma, Pedro Tomás, Leonel Sousa:
RVEBS: Event-Based Sampling on RISC-V. 1-7 - Shuhan Bai, Haowen Luo, Burong Dong, Jian Zhou, Fei Wu:
Locality-Aware Data Placement for NUMA Architectures: Data Decoupling and Asynchronous Replication. 1-7
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last updated on 2025-07-09 21:37 CEST by the dblp team
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