default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISCAS 2010: Paris, France
- International Symposium on Circuits and Systems (ISCAS 2010), May 30 - June 2, 2010, Paris, France. IEEE 2010, ISBN 978-1-4244-5308-5
- Ming Liu, Qi Liu, Shibing Long, Weihua Guan:
Formation and annihilation of Cu conductive filament in the nonpolar resistive switching Cu/ZrO2: Cu/Pt ReRAM. 1-4 - Victor Erokhin
:
Organic memristors : Basic principles. 5-8 - Davide Sacchetto, M. Haykel Ben Jamaa, Sandro Carrara, Giovanni De Micheli, Yusuf Leblebici:
Memristive devices fabricated with silicon nanowire schottky barrier transistors. 9-12 - Sung Hyun Jo, Kuk-Hwan Kim, Ting Chang, Siddharth Gaba, Wei Lu:
Si Memristive devices applied to memory and neuromorphic circuits. 13-16 - Shanthi Pavan:
Understanding weak loop filter nonlinearities in continuous time ΔΣ converters. 17-20 - Ahmed Ashry, Hassan Aboushady:
A generalized approach to design CT ΣΔMs based on FIR DAC. 21-24 - Chen-Yen Ho, Yung-Yu Lin, Tsung-Hsien Lin:
Dual-mode Continuous-Time Quadrature Bandpass ΔΣ modulator with Pseudo-random Quadrature mismatch shaping algorithm for Low-IF receiver application. 25-28 - Wagdy M. Gaber, Mootaz Allam, Hassan Aboushady, Marie-Minerve Louërat, El-Sayed Eid:
Systematic design of continuous-time ΣΔ modulator with VCO-based quantizer. 29-32 - J. Gerardo García-Sánchez, José M. de la Rosa:
Multirate hybrid CT/DT cascade ΣΔ modulators with decreasing OSR of back-end DT stages. 33-36 - Massimo Alioto, Paolo Bennati, Roberto Giorgi:
Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. 37-40 - Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. 41-44 - Xiaoxiao Zhang, Amine Bermak, Farid Boussaïd:
Dynamic voltage and frequency scaling for low-power multi-precision reconfigurable multiplier. 45-48 - Mohammad Ghasemazar, Ehsan Pakbaznia, Massoud Pedram:
Minimizing energy consumption of a chip multiprocessor through simultaneous core consolidation and DVFS. 49-52 - Pritesh Vora, Masud H. Choudhary:
Prospects and implementation of Non-DVFS dynamic thermal management techniques. 53-56 - Yuan-Pei Lin, Yi-De Liu, See-May Phoong:
Finding the minimum sampling frequency of multi-band signals: An efficient iterative algorithm. 57-60 - Di He:
Breaking the SNR wall of spectrum sensing in cognitive radio by using the chaotic stochastic resonance. 61-64 - Navin Michael, A. Prasad Vinod, Christophe Moy, Jacques Palicot:
Design paradigm for standard agnostic channelization in flexible mobile radios. 65-68 - Yihu Xu, Myoung-Seob Lim:
Split-radix FFT pruning for the reduction of computational complexity in OFDM based Cognitive Radio system. 69-72 - Aziz S. Inan:
What did Gustav Robert Kirchhoff stumble upon 150 years ago? 73-76 - Joos Vandewalle:
Important questions related to the education of the mathematics of circuits and systems. 77-80 - Jan C. Willems:
Terminals and ports. 81-84 - John Hu, Mark Haffner, Samantha Yoder, Gursharan Reehal, Mark Scott, Mohammed Ismail:
An industry-driven laboratory development for mixed-signal IC test education. 85-88 - Abdulhadi Shoufan:
A compact course on VHDL-AMS. 89-92 - Yingxue Wang, Shih-Chii Liu:
Motion detection using an aVLSI network of spiking neurons. 93-96 - Srinjoy Mitra, Giacomo Indiveri, Ralph Etienne-Cummings:
Synthesis of log-domain integrators for silicon synapses with global parametric control. 97-100 - Sheng-Feng Yen, John G. Harris:
An adaptive neuron circuit for signal compression. 101-104 - Christian Mayr, Marko Noack, Johannes Partzsch, René Schüffny:
Replicating experimental spike and rate based neural learning in CMOS. 105-108 - Chenling Huang, Shantanu Chakrabartty:
A temperature compensated array of CMOS floating-gate analog memory. 109-112 - Hung-Chih Lin, Hsueh-Ming Hang:
Fast algorithm on selecting bi-directional prediction type in H.264/AVC scalable video coding. 113-116 - Xiaozheng Huang, Jie Liang, Hongfei Du, Jiangchuan Liu:
Lloyd-Max quantization-based priority index assignment for the scalable extension of H.264/AVC. 117-120 - Pei-Kuei Tsung, Hsin-Jung Yang, Pin-Chih Lin, Kuan-Yu Chen, Liang-Gee Chen:
Hybrid color compensation for virtual view synthesis in multiview video applications. 121-124 - Jui-Chiu Chiang, Kuan-Liang Chen, Chi-Ju Chou, Chang-Ming Lee, Wen-Nung Lie:
Block-based distributed video coding with variable block modes. 125-128 - Nelson Okafor, Bashar Zahawi, Damian Giaouris, Soumitro Banerjee:
Chaos, coexisting attractors, and fractal basin boundaries in DC drives with full-bridge converter. 129-132 - Kuntal Mandal, Soumitro Banerjee, Chandan Chakraborty:
Bifurcations in load resonant DC-DC converters. 133-136 - Marcus Rogerio De Castro, Bruno Gérard Michel Robert, Clément Goeldel:
Analysis of aperiodic and chaotic motions in a switched reluctance linear motor. 137-140 - Norberto Garcia:
Periodic steady-state solutions of nonlinear circuits based on a differentiation matrix. 141-144 - Jiantao Zhou, Oscar C. Au:
Cryptanalysis of chaotic convolutional coder. 145-148 - Renyan Zhou, Leibo Liu, Shouyi Yin, Ao Luo, Xinkai Chen, Shaojun Wei:
A VLSI design of sensor node for wireless image sensor network. 149-152 - Juan Núñez, Maria J. Avedillo, José M. Quintana:
Single phase MOS-NDR mobile networks. 153-156 - Naoya Onizawa, Takahiro Hanyu:
High-throughput protocol converter based on an independent encoding/decoding scheme for asynchronous Network-on-Chip. 157-160 - Mohammad Hosseinabady, José L. Núñez-Yáñez:
Effective modelling of large NoCs using SystemC. 161-164 - Zewen Shi, Kaidi You, Yan Ying, Bei Huang, Xiaoyang Zeng, Zhiyi Yu:
A scalable and fault-tolerant routing algorithm for NoCs. 165-168 - Wu-Sheng Lu, Takao Hinamoto:
Digital filters with sparse coefficients. 169-172 - Palghat P. Vaidyanathan, Ching-Chih Weng:
Active beamforming with interpolated FIR filterin. 173-176 - Dong Shi, Ya Jun Yu:
Low-complexity linear phase fir filters in cascade form. 177-180 - Anton Blad, Oscar Gustafsson:
Redundancy reduction for high-speed fir filter architectures based on carry-save adder trees. 181-184 - Chia-Yu Yao, Chung-Lin Sha:
Fixed-point FIR filter design and implementation in the expanding subexpression space. 185-188 - Norio Chujo, Takehito Kamimura, Goichi Ono, Fumio Yuki:
A 25 Gbps inductorless receiver front-end in 65-nm CMOS for serial links. 189-192 - Jiho Han, Hankyu Chi, Deog-Kyoon Jeong:
A clock synchronization system with IEEE 1588-2008 adapters over existing Gigabit Ethernet equipment. 193-196 - Yunzhi Dong, Kenneth W. Martin:
Analog front-end for a 3 Gb/s POF receiver. 197-200 - Hung-Wen Lin, Yingchieh Ho, YingLin Fa, Chauchin Su:
A 5Gb/s pulse signaling interface for low power on-chip data communication. 201-204 - Dustin Dunwell, Anthony Chan Carusone:
A 15-Gb/s preamplifier with 10-dB gain control and 8-mV sensitivity in 65-nm CMOS. 205-208 - Kimia Taghizadeh Ansari, Calvin Plett:
A low power ultra-wideband CMOS LNA for 3.1-10.6-GHz wireless receivers. 209-212 - Yonghui Ji, Ming Liu, Qin Wang, Shibing Long, Zhaoan Yu, Manhong Zhang:
A low power single ended input differential output low noise amplifier for L1/L2 band. 213-216 - Nihit Bajaj, Bert Vermeire, Bertan Bakkaloglu:
A 10MHz to 100MHz bandwidth scalable, fully differential current feedback amplifier. 217-220 - Juan Antonio Gómez Galán, Manuel Pedro, Carlos Rubia-Marcos, Ramón González Carvajal, Clara Isabel Luján-Martínez, Antonio J. López-Martín:
A low-voltage, high linear programmable triode transconductor. 221-224 - José María Algueta-Miguel, Antonio J. López-Martín, Jaime Ramírez-Angulo, Ramón González Carvajal:
Tunable rail-to-rail FGMOS transconductor. 225-228 - Robert Bogdan Staszewski:
State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS. 229-232 - Paul-Peter Sotiriadis:
All-digital frequency and clock synthesis architectures from a signals and systems perspective, current state and future directions. 233-236 - Liming Xiu, Chen-Wei Huang, Ping Gui:
A comparative study between Fractional-N PLL and Flying-Adder PLL. 237-240 - Francesco Brandonisio, Franco Maloberti:
An all-digital PLL with a first order noise shaping Time-to-Digital Converter. 241-244 - Brian Fitzgibbon, Michael Peter Kennedy:
Calculation of the cycle length in a HK-MASH DDSM with multilevel quantizers. 245-248 - Luis A. Camuñas-Mesa, José Antonio Pérez-Carrasco, Carlos Zamarreño-Ramos, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
On scalable spiking convnet hardware for cortex-like visual sensory processing systems. 249-252 - Yann LeCun, Koray Kavukcuoglu, Clément Farabet:
Convolutional networks and applications in vision. 253-256 - Clément Farabet, Berin Martini, Polina Akselrod, Selçuk Talay, Yann LeCun, Eugenio Culurciello:
Hardware accelerated convolutional neural networks for synthetic vision systems. 257-260 - Franck Mamalet, Sébastien Roux, Christophe Garcia:
Embedded facial image processing with Convolutional Neural Networks. 261-264 - Simon J. Thorpe, Adrien Brilhault, José Antonio Pérez-Carrasco:
Suggestions for a biologically inspired spiking retina using order-based coding. 265-268 - Benton H. Calhoun, Sudhanshu Khanna, Yanqing Zhang, Joseph F. Ryan, Brian P. Otis:
System design principles combining sub-threshold circuit and architectures with energy scavenging mechanisms. 269-272 - Chao Lu, Vijay Raghunathan, Kaushik Roy:
Maximum power point considerations in micro-scale solar energy harvesting systems. 273-276 - Ki Chul Chun, Pulkit Jain, Chris H. Kim:
Logic-compatible embedded DRAM design for memory intensive low power systems. 277-280 - Dongwon Kwon, Gabriel A. Rincón-Mora, Erick O. Torres:
Harvesting kinetic energy with switched-inductor DC-DC converters. 281-284 - Mingoo Seok, Scott Hanson, Michael Wieckowski, Gregory K. Chen, Yu-Shiang Lin, David T. Blaauw, Dennis Sylvester:
Circuit design advances to enable ubiquitous sensing environments. 285-288 - Luis Hernández, Jorge Fernández, Enrique Prefasi, Susana Patón:
A time encoded decimation filter for noise shaped power DACs. 289-292 - Hossein Pakniat, Mohammad Yavari, Reza Lotfi:
A digital background correction technique combined with DWA for DAC mismatch errors in multibit ΣΔ ADCs. 293-296 - Nima Maghari, Un-Ku Moon:
Precise area-controlled return-to-zero current steering DAC with reduced sensitivity to clock jitter. 297-300 - Nagendra Krishnapura:
Efficient determination of feedback DAC errors for digital correction in ΔΣ A/D converters. 301-304 - Chien-Hung Kuo, Hung-Jing Lai, Deng-Yao Shi:
A sixth-order 4-2 SMASH CIFF complex bandpass ΔΣ modulator with delaying digital input feedforward. 305-308 - Koji Sakui, Tetsuo Endoh:
A compact and low power logic design for multi-pillar vertical MOSFETs. 309-312 - Johannes Uhlig, Sebastian Höppner, Georg Ellguth, René Schüffny:
A low-power cell-based-design multi-port register file in 65nm CMOS technology. 313-316 - Fabio Frustaci, Stefania Perri, Marco Lanuzza, Pasquale Corsonello:
A new low-power high-speed single-clock-cycle binary comparator. 317-320 - Massimo Alioto, Elio Consoli, Gaetano Palumbo:
Clock distribution in clock domains with Dual-Edge-Triggered Flip-Flops to improve energy-efficiency. 321-324 - Rajeev K. Dokania, Xiao Y. Wang, Siddharth G. Tallur, Alyssa B. Apsel:
A 19μW, 100kbps Impulse Radio transceiver for body-area-networks. 325-328 - Yunfeng Chen, Jinhan Fan, Wei Li, Ning Li, Junyan Ren:
A current-mode 6-9GHz UWB transmitter with output power flattening technique. 329-332 - Silvia Soldà, Michele Caruso, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani:
Low-power UWB transmitter using a combined mixer and power amplifier. 333-336 - Géza Kolumbán, Tamás Krébesz, Chi Kong Tse, Francis Chung-Ming Lau:
Derivation of circuit specification for the UWB impulse radio transceivers. 337-340 - Kamel Elkhenissi, Maxim Cournoyer, Dominic Deslandes, Frederic Nabki:
A transmitted-reference low-power reconfigurable ultra-wideband transmitter. 341-344 - Konstantin Nikolic, Chris Toumazou:
A bio-inspired ultrasensitive imaging chip - Phase one: Design paradigm. 345-348 - Raphael Berner, Tobi Delbrück:
Event-based color change pixel in standard CMOS. 349-352 - Sylvain Léomant, Xiajun Wu, Amine Bermak:
A single bit memory per pixel time domain DPS using multi-reset integration scheme. 353-356 - Danial Chitnis, Steve Collins:
Compact readout circuits for SPAD arrays. 357-360 - Daniel Matolin, Rainer Wohlgenannt, Martin Litzenberger, Christoph Posch:
A load-balancing readout method for large event-based PWM imaging arrays. 361-364 - Katherine L. Cameron, Thomas F. Clayton, Bruce Rae, Alan F. Murray, Robert K. Henderson, Edoardo Charbon:
Poisson distributed noise generation for spiking neural applications. 365-368 - Shubha Ramakrishnan, Paul E. Hasler, Christal Gordon:
Floating gate synapses with spike time dependent plasticity. 369-372 - Xinxin Wang, Bertram E. Shi:
GPU implemention of fast Gabor filters. 373-376 - Bilel Belhadj, Jean Tomas, Olivia Malot, Yannick Bornat, Gilles N'Kaoua, Sylvie Renaud:
Guaranteeing spike arrival time in multiboard & multichip spiking neural networks. 377-380 - Yiping Dong, Zhen Lin, Yan Li, Takahiro Watanabe:
High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels. 381-384 - Jun Zhang, Xiang Li, Nam Ling, Jianhua Zheng, Philipp Zhang:
Prediction-based macroblock mode mapping for video coding. 385-388 - Bingqiang Zhu, Da An, Yaocheng Rong, Yun He:
A VLSI architecture of cost calculation and all-zero block detection for fractional motion estimation. 389-392 - Yi-Hsin Huang, Tao-Sheng Ou, Homer H. Chen:
Perceptual-based coding mode decision. 393-396 - Wenpeng Ding, You Zhou, Feng Wu:
Fast mode decision for KTA software. 397-400 - Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto, Peilin Liu:
An adaptive bandwidth reduction scheme for video coding. 401-404 - Zhihai Rong, Han-Xin Yang, Wen-Xu Wang:
Effect of clustering coefficient on cooperation in scale-free public goods game. 405-408 - Yang Yang, Xiang Li, Zhihai Rong:
The roles of small-world and degree heterogeneity on evolutionary behavior networks. 409-412 - Daniel Trpevski, Wallace Kit-Sang Tang, Ljupco Kocarev:
An opinion disseminating model for market penetration in social networks. 413-416 - Housheng Su, Zhihai Rong, Xiaofan Wang, Guanrong Chen:
On decentralized adaptive pinning synchronization of complex dynamical networks. 417-420 - Juan Chen, Junan Lu, Xiaoqun Wu, Wei Xing Zheng:
Impulsive synchronization on complex networks of nonlinear dynamical systems. 421-424 - Ülkühan Güler, Salih Ergün:
A high speed IC Random Number Generator based on phase noise in ring oscillators. 425-428 - Nathan Schemm, Sina Balkir, Sharad C. Seth:
Hardware implementation of the double-tree scan architecture. 429-432 - Satendra Kumar Maurya, Lawrence T. Clark:
Fast and scalable priority encoding using static CMOS. 433-436 - Gong-Han Chen, Chu-Chuan Lin, Po-Han Wu, Jiann-Chyi Rau:
Multi-cycle compress technique for high-speed IP in low-cost environment. 437-440 - Jianwei Chen, Hongchin Lin, Yun-Ching Tang:
Efficient high-throughput architectures for high-speed parallel scramblers. 441-444 - Tian-Bo Deng:
Wide-band length-6 cubic interpolator. 445-448 - Yuval Bistritz, Yaron Segalov:
Fraction-free inversion of a Toeplitz matrix. 449-452 - Junyoung Park, Seungjin Lee, Hoi-Jun Yoo:
A 30fps stereo matching processor based on belief propagation with disparity-parallel PE array architecture. 453-456 - Mathias Faust, Chip-Hong Chang:
Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication. 457-460 - Mei Leng, Yik-Chung Wu:
On joint synchronization of clock offset and skew for Wireless Sensor Networks under exponential delay. 461-464 - Jiangli Zhu, Xinmiao Zhang:
High-speed re-encoder design for algebraic soft-decision Reed-Solomon decoding. 465-468 - Jinjin He, Zhongfeng Wang, Huaping Liu:
Memory-reduced MAP decoding for double-binary convolutional Turbo code. 469-472