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ORCIDStefan Frehse
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2010 – 2019
- 2019
[j6]Sebastian Huhn
, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 875-887 (2019)- 2017
- [j5]Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017) - [c13]Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. ASP-DAC 2017: 182-187 - 2013
- [b1]Stefan Frehse:
Quality and quantity in robustness checking using formal techniques. University of Bremen, 2013, pp. 1-182 - [c12]Heinz Riener, Stefan Frehse, Görschwin Fey:
Improving fault tolerance utilizing hardware-software-co-synthesis. DATE 2013: 939-942 - 2012
- [j4]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler:
RevKit: A Toolkit for Reversible Circuit Design. J. Multiple Valued Log. Soft Comput. 18(1): 55-65 (2012) - [c11]Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler:
Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90 - 2011
- [j3]Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler:
Debugging reversible circuits. Integr. 44(1): 51-61 (2011) - [j2]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1239-1252 (2011) - [c10]Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining minimal testsets for reversible circuits using Boolean satisfiability. AFRICON 2011: 1-6 - [c9]Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler:
metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD 2011 - [c8]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler:
RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC 2011: 64-76 - 2010
- [j1]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. 52(4): 216-223 (2010) - [c7]Stefan Frehse, Görschwin Fey, Rolf Drechsler:
A better-than-worst-case robustness measure. DDECS 2010: 78-83 - [c6]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231 - [c5]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC 2010: 37-38 - [c4]Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler:
Enhancing debugging of multiple missing control errors in reversible logic. ACM Great Lakes Symposium on VLSI 2010: 465-470 - [c3]Stefan Frehse, Robert Wille, Rolf Drechsler:
Efficient Simulation-Based Debugging of Reversible Logic. ISMVL 2010: 156-161
2000 – 2009
- 2009
- [c2]Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler:
Debugging of Toffoli networks. DATE 2009: 1284-1289 - [c1]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90
Coauthor Index
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