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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 22
Volume 22, Number 1, January 2003
- Jong-Yeol Lee, In-Cheol Park
:
Timed compiled-code functional simulation of embedded software for performance analysis of SOC design. 1-14 - David J. Walkey, Dritan Celo, Tom J. Smy:
A simplified model for the effect of interfinger metal on maximum temperature rise in a multifinger bipolar transistor. 15-25 - Nikolay Rubanov:
SubIslands: the probabilistic match assignment algorithm for subcircuit recognition. 26-38 - David T. Blaauw, Chanhee Oh, Vladimir Zolotov, Aurobindo Dasgupta:
Static electromigration analysis for on-chip signal interconnects. 39-48 - Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar:
Fast on-chip inductance simulation using a precorrected-FFT method. 49-66 - Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Chip-level charged-device modeling and simulation in CMOS integrated circuits. 67-81 - Irith Pomeranz, Sudhakar M. Reddy:
Test enrichment for path delay faults using multiple sets of target faults. 82-90 - Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao:
Maze routing with buffer insertion under transition time constraints. 91-95 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Timing constraints for domino logic gates with timing-dependent keepers. 96-103 - Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou:
Automatic interconnection rectification for SoC design verification based on the port order fault model. 104-114
Volume 22, Number 2, February 2003
- H. Alan Mantooth, Georges G. E. Gielen:
Guest editorial. 121-123 - Manuel Innocent, Piet Wambacq, Stéphane Donnay, Harrie A. C. Tilmans, Willy M. C. Sansen, Hugo De Man:
An analytic Volterra-series-based model for a MEMS variable capacitor. 124-131 - Patrick Reynaert, Koen L. R. Mertens, Michiel Steyaert:
A state-space behavioral model for CMOS class E power amplifiers. 132-138 - Steven P. Levitan, Jose A. Martinez, Timothy P. Kurzweg, Abhijit Davare, Mark Kahrs, Michael Bails, Donald M. Chiarulli:
System simulation of mixed-signal multi-domain microsystems with piecewise linear models. 139-154 - Michal Rewienski, Jacob K. White:
A trajectory piecewise-linear approach to model order reduction and fast simulation of nonlinear circuits and micromachined devices. 155-170 - Joel R. Phillips:
Projection-based approaches for model reduction of weakly nonlinear, time-varying systems. 171-187 - Alper Demir, Jaijeet S. Roychowdhury:
A reliable and efficient procedure for oscillator PPV computation, with phase noise macromodeling applications. 188-197 - Glenn Wolfe, Ranga Vemuri:
Extraction and use of neural network models in automated synthesis of operational amplifiers. 198-212 - Bart De Smedt, Georges G. E. Gielen:
WATSON: design space boundary exploration and model generation for analog and RFIC design. 213-224 - David M. Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty:
A CAD methodology for optimizing transistor current and sizing in analog CMOS design. 225-237
Volume 22, Number 3, Mar 2003
- Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
Minimum buffered routing with bounded capacitive load for slew rate and reliability control. 241-253 - Mary Y. L. Wisniewski, Emmanuel Yashchin, Robert L. Franch, David P. Conrady, Daniel N. Maynard, Giovanni Fiorenza, I. Cevdet Noyan:
The physical design of on-chip interconnections. 254-276 - Sheldon X.-D. Tan, Chuanjin Richard Shi:
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. 277-284 - Clemens Heitzinger, Wolfgang Pyka, Naoki Tamaoki, Toshiro Takase, Toshimitsu Ohmine, Siegfried Selberherr:
Simulation of arsenic in situ doping with polysilicon CVD and its application to high aspect ratio trenches. 285-292 - Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
Reverse-order-restoration-based static test compaction for synchronous sequential circuits. 293-304 - Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas:
Exact path delay fault coverage with fundamental ZBDD operations. 305-316 - Kianosh Rahimi, Mani Soma:
Layout driven synthesis of multiple scan chains. 317-326 - Yuejian Wu, Paul N. MacDonald:
Testing ASICs with multiple identical cores. 327-336 - Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj:
Early probabilistic noise estimation for capacitively coupled interconnects. 337-345 - Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria:
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. 346-351 - Anshuman Chandra, Krishnendu Chakrabarty:
A unified approach to reduce SOC test data volume, scan power and testing time. 352-363 - Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee:
Test pattern generation and clock disabling for simultaneous test time and power reduction. 363-370 - James F. Plusquellic, Abhishek Singh, Chintan Patel, Anne E. Gattiker:
Power supply transient signal analysis for defect-oriented test. 370-374 - Qiushuang Zhang, Ian G. Harris:
Partial BIST insertion to eliminate data correlation. 374-379
Volume 22, Number 4, April 2003
- Charles J. Alpert, Sachin S. Sapatnekar:
Guest editorial. 385-386 - Ulrich Brenner, André Rohe:
An effective congestion-driven placement framework. 387-394 - Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan:
Multilevel global placement with congestion control. 395-409 - Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh:
Routability-driven white space allocation for fixed-die standard-cell placement. 410-419 - Yongseok Cheon, Martin D. F. Wong:
Design hierarchy-guided multilevel circuit partitioning. 420-427 - Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif:
Optimal decoupling capacitor sizing and placement for standard-cell layout designs. 428-436 - Prashant Saxena, Satyanarayan Gupta:
On integrating power and signal routing for shield count minimization in congested regions. 437-445 - Shuo Zhang, Wayne Wei-Ming Dai:
TEG: a new post-layout optimization method. 446-456 - Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen:
Twin binary sequences: a nonredundant representation for general nonslicing floorplan. 457-469 - Chiu-Wing Sham, Evangeline F. Y. Young:
Routability-driven floorplanner with buffer block planning. 470-480 - Milos Hrkic, John Lillis:
Buffer tree synthesis with consideration of temporal locality, sink polarity requirements, solution cost, congestion, and blockages. 481-491 - Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham:
Buffer insertion with adaptive blockage avoidance. 492-498 - Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas:
Global and local congestion optimization in technology mapping. 498-505 - Seokjin Lee, Martin D. F. Wong:
Timing-driven routing for FPGAs based on Lagrangian relaxation. 506-510
Volume 22, Number 5, May 2003
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. 517-534 - Jovanka Ciric, Carl Sechen:
Efficient canonical form for Boolean matching of complex functions in large libraries. 535-544 - Srini Krishnamoorthy, Russell Tessier:
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. 545-559 - Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu:
Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. 560-572 - Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia:
A practical methodology for early buffer and wire resource allocation. 573-583 - Jae-Gon Kim, Yeong-Dae Kim:
A linear programming-based algorithm for floorplanning in VLSI design. 584-592 - Chunsheng Liu, Krishnendu Chakrabarty:
Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment. 593-604 - Elaheh Bozorgzadeh, Ryan Kastner, Majid Sarrafzadeh:
Creating and exploiting flexibility in rectilinear Steiner trees. 605-615 - Robert P. Dick, Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha:
Analysis of power dissipation in embedded systems using real-time operating systems. 615-627 - Li Ding, David T. Blaauw, Pinaki Mazumder:
Accurate crosstalk noise modeling for early signal integrity analysis. 627-634 - Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen:
Efficient test access mechanism optimization for system-on-chip. 635-643 - Louis Scheffer:
Some conditions under which hierarchical verification is O(N). 643-646 - Cliff C. N. Sze, Ting-Chi Wang:
Optimal circuit clustering for delay minimization under a more general delay model. 646-651 - Wing Seung Yuen, Evangeline F. Y. Young:
Slicing floorplan with clustering constraint. 652-658
Volume 22, Number 6, June 2003
- Soha Hassoun, Steven M. Nowick, Leon Stok:
Guest Editorial. 662-664 - Prabhakar Kudva, Andrew Sullivan, William E. Dougherty:
Measurements for structural logic synthesis optimizations. 665-674 - Jordi Cortadella:
Timing-driven logic bi-decomposition. 675-685 - Jie-Hong Roland Jiang, Robert K. Brayton:
On the verification of sequential equivalence. 686-697 - Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A high-performance architecture and BDD-based synthesis methodology for packet classification. 698-709 - Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Synthesis of reversible logic circuits. 710-722 - Fan Mo, Robert K. Brayton:
PLA-based regular structures and their synthesis. 723-729 - Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani:
Integrated floorplanning with buffer/channel insertion for bus-based designs. 730-741 - H. C. Srinivasaiah, Navakanta Bhat:
Mixed-mode simulation approach to characterize the circuit delay sensitivity to implant dose variations. 742-747 - Tingdong Zhou, Steven L. Dvorak, John L. Prince:
Lossy transmission line simulation based on closed-form triangle impulse responses. 748-755 - Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng:
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. 756-769 - Yi Zhao, Sujit Dey:
Fault-coverage analysis techniques of crosstalk in chip interconnects. 770-782 - Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Variable-length input Huffman coding for system-on-a-chip test. 783-796 - Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba:
An efficient test vector compression scheme using selective Huffman coding. 797-806 - Arlindo L. Oliveira, Rajeev Murgai:
On the problem of gate assignment under different rise and fall delays. 807-814 - Hui Xu, Rob A. Rutenbar, Karem A. Sakallah:
sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. 814-820
Volume 22, Number 7, July 2003
- Ingmar Neumann, Wolfgang Kunz:
Layout driven retiming using the coupled edge timing model. 825-835 - Zhan Yu, Kei-Yong Khoo, Alan N. Willson Jr.:
Optimal joint module-selection and retiming with carry-save representation. 836-846 - Vishnu Swaminathan, Krishnendu Chakrabarty:
Energy-conscious, deterministic I/O device scheduling in hard real-time systems. 847-858 - Sarnath Ramnath:
New approximations for the rectilinear Steiner arborescence problem [VLSI layout]. 859-869 - Hua Xiang, Xiaoping Tang, Martin D. F. Wong:
Min-cost flow-based algorithm for simultaneous pin assignment and routing. 870-878 - Clemens Heitzinger, Andreas Hössinger, Siegfried Selberherr:
On smoothing three-dimensional Monte Carlo ion implantation simulation results. 879-883 - Tsung-Hao Chen, Clement Luk, Charlie Chung-Ping Chen:
INDUCTWISE: inductance-wise interconnect simulator and extractor. 884-894 - Xiaoling Huang, Chris S. Gathercole, H. Alan Mantooth:
Modeling nonlinear dynamics in analog circuits via root localization. 895-907 - Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas:
Data dependency size estimation for use in memory optimization. 908-921 - M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques. 922-936 - Christoph Albrecht, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky:
On the skew-bounded minimum-buffer routing tree problem. 937-945 - Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska:
A new reasoning scheme for efficient redundancy addition and removal. 945-951 - Wai-Kei Mak, Evangeline F. Y. Young:
Temporal logic replication for dynamically reconfigurable FPGA partitioning. 952-959
Volume 22, Number 8, August 2003
- David T. Blaauw, Luciano Lavagno:
Guest Editorial. 962-963 - Armita Peymandoust, Tajana Simunic, Giovanni De Micheli:
Complex instruction and software library mapping for embedded software using symbolic algebra. 964-975 - Yoonseo Choi, Taewhan Kim:
Address assignment in DSP code generation - an integrated approach. 976-984 - Michael J. Wirthlin, Brian McMurtrey:
Web-based IP evaluation and distribution using applets. 985-994 - Fadi A. Aloul, Brian D. Sierawski, Karem A. Sakallah:
Satometer: how much have we searched? 995-1004 - Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Three-level logic minimization based on function regularities. 1005-1016 - Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen:
Behavioral modeling of (coupled) harmonic oscillators. 1017-1026 - Joel R. Phillips, Luca Daniel, Luís Miguel Silveira:
Guaranteed passive balancing transformations for model order reduction. 1027-1041 - Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna:
Design automation with mixtures of proof strategies for propositional logic. 1042-1048 - Kenneth Francken, Georges G. E. Gielen:
A high-level simulation and synthesis environment for ΔΣ modulators. 1049-1061 - Gang Quan, Xiaobo Sharon Hu:
Minimal energy fixed-priority scheduling for variable voltage processors. 1062-1071 - Paolo Pavan, Luca Larcher, Massimiliano Cuozzo, Paola Zuliani, Antonino Conte:
A complete model of E2PROM memory cells for circuit simulations. 1072-1079 - Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
PROPTEST: a property-based test generator for synchronous sequential circuits. 1080-1091 - Irith Pomeranz, Sudhakar M. Reddy:
Theorems for identifying undetectable faults in partial-scan circuits. 1092-1097 - Joon-Jea Sung, Guen-Soon Kang, Suki Kim:
A transient noise model for frequency-dependent noise sources. 1097-1104 - Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul:
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. 1104-1113
Volume 22, Number 9, September 2003
- Fadi A. Aloul, Arathi Ramani, Igor L. Markov, Karem A. Sakallah:
Solving difficult instances of Boolean satisfiability in the presence of symmetry. 1117-1137 - Hao Zheng, Eric Mercer, Chris J. Myers:
Modular verification of timed circuits using automatic abstraction. 1138-1153 - Armita Peymandoust, Giovanni De Micheli:
Application of symbolic computer algebra in high-level data-flow synthesis. 1154-1165 - Debatosh Debnath, Zvonko G. Vranesic:
A fast algorithm for OR-AND-OR synthesis. 1166-1176 - Adnan Kabbani, Dhamin Al-Khalili, Asim J. Al-Khalili:
Technology-portable analytical model for DSM CMOS inverter transition-time estimation. 1177-1187 - Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul:
Probabilistic analysis of interconnect coupling noise. 1188-1203 - Thomas Binder, Andreas Hössinger, Siegfried Selberherr:
Rigorous integration of semiconductor process and device simulators. 1204-1214 - Petr Dobrovolný, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay:
Analysis and compact behavioral modeling of nonlinear distortion in analog communication circuits. 1215-1227 - Gang Li, Narayan R. Aluru:
Efficient mixed-domain analysis of electrostatic MEMS. 1228-1242 - Aseem Agarwal, Vladimir Zolotov, David T. Blaauw:
Statistical timing analysis using bounds and selective enumeration. 1243-1260 - Hai Zhou:
Timing analysis with crosstalk is a fixpoint on a complete lattice. 1261-1269 - Soha Hassoun, Christopher Cromer, Eduardo H. Calvillo Gámez:
Static timing analysis for level-clocked circuits in the presence of crosstalk. 1270-1277 - Darko Kirovski, Miodrag Potkonjak:
Local watermarks: methodology and application to behavioral synthesis. 1277-1283 - Tat Kee Tan, Anand Raghunathan, Niraj K. Jha:
A simulation framework for energy-consumption analysis of OS-driven embedded applications. 1284-1294
Volume 22, Number 10, October 2003
- Peng Li, Lawrence T. Pileggi:
Efficient per-nonlinearity distortion analysis for analog and RF circuits. 1297-1309 - Valentina Ciriani:
Synthesis of SPP three-level logic networks using affine spaces. 1310-1323 - Mohab Anis, Shawki Areibi, Mohamed I. Elmasry:
Design and optimization of multithreshold CMOS (MTCMOS) circuits. 1324-1342 - Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia:
Effective free space management for cut-based placement via analytical constraint generation. 1343-1353 - Zion Cien Shen, Chris C. N. Chu:
Bounds on the number of slicing, mosaic, and general floorplans. 1354-1361 - Rouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen, Albert Z. Wang:
ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction. 1362-1370 - Zaid Al-Ars, Ad J. van de Goor:
Test generation and optimization for DRAM cell defects using electrical simulation. 1371-1384 - Junwei Hou, Abhijit Chatterjee:
Concurrent transient fault simulation for analog circuits. 1385-1398 - Saravanan Padmanaban, Spyros Tragoudas:
An implicit path-delay fault diagnosis methodology. 1399-1408 - Jeongjin Roh, Jacob A. Abraham:
A comprehensive signature analysis scheme for oscillation-test. 1409-1423 - Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. 1424-1431 - George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Wordlength optimization for linear digital signal processing. 1432-1442 - Michael G. Dimopoulos, Panagiotis Linardis:
Accelerating the compaction of test sequences in sequential circuits through problem size reduction. 1443-1449 - Irith Pomeranz, Sudhakar M. Reddy:
Test data compression based on input-output dependence. 1450-1455
Volume 22, Number 11, November 2003
- Cesare Alippi, Andrea Galbusera, Marco Stellini:
An application-level synthesis methodology for multidimensional embedded processing systems. 1457-1470 - Peter M. Maurer:
Efficient event-driven simulation by exploiting the output observability of gate clusters. 1471-1486 - Junhyung Um, Taewhan Kim:
Synthesis of arithmetic circuits considering layout effects. 1487-1503 - Alex Doboli, Ranga Vemuri:
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS. 1504-1520 - Guoan Zhong, Cheng-Kok Koh, Kaushik Roy:
On-chip interconnect modeling by wire duplication. 1521-1532 - Haihua Su, Kaushik Gala, Sachin S. Sapatnekar:
Analysis and optimization of structured power/ground networks. 1533-1544 - Yu-Min Lee, Charlie Chung-Ping Chen:
The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. 1545-1550 - Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov:
Hierarchical whitespace allocation in top-down placement. 1550-1556 - Alex Doboli, Ranga Vemuri:
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies. 1556-1568 - Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Addressing useless test data in core-based system-on-a-chip test. 1568-1580 - Soha Hassoun, Charles J. Alpert:
Optimal path routing in single- and multiple-clock domain systems. 1580-1588 - Alan Mishchenko:
Fast computation of symmetries in Boolean functions. 1588-1593
Volume 22, Number 12, December 2003
- Frederic Doucet, Sandeep K. Shukla, Masato Otsuka, Rajesh K. Gupta:
BALBOA: a component-based design environment for system models. 1597-1612 - Pasquale Cocchini:
A methodology for optimal repeater insertion in pipelined interconnects. 1613-1624 - Giorgio Casinovi, Chad Young:
Estimation of power dissipation in switched-capacitor circuits. 1625-1636 - Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung:
On optimal hyperuniversal and rearrangeable switch box designs. 1637-1649 - Hendrik Rogier, Daniel De Zutter:
A fast technique based on perfectly matched layers for the full-wave solution of 2-D dispersive microstrip lines. 1650-1656 - Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
An improved branch and bound algorithm for exact BDD minimization. 1657-1663 - Irith Pomeranz, Sudhakar M. Reddy:
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. 1663-1670 - Peyman Rezvani, Massoud Pedram:
A fanout optimization algorithm based on the effort delay model. 1671-1678 - Sheldon X.-D. Tan, Chuanjin Richard Shi, Jyh-Chwen Lee:
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings. 1678-1684 - Teng-Sheng Moh, Tsu-Shuan Chang:
Comments on "Handling soft modules in general nonslicing floorplan using Lagrangian relaxation". 1684-1686
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