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ORCID39th ISMVL 2009: Naha, Okinawaw, Japan
- ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan. IEEE Computer Society 2009, ISBN 978-0-7695-3607-1
Invited Talk 1
- Andrei A. Bulatov:
Counting Problems and Clones of Functions. 1-6
Medical/Health Care Systems Based on Soft Computing
- Reiko Sakashita, Atsuko Uchinuno, Kazuko Kamiizumi, Keiko Tei, Noriko Awaya:
Web-Based Nursing Care Quality Improvement System with Fuzzy Recommendation System. 7-11 - Naoki Tsuchiya, Hiroshi Nakajima:
A Study of Practical Causality Acquisition among Vital Signals. 12-17 - Hong Ye, Syoji Kobashi, Yutaka Hata, Kazuhiko Taniguchi, Kazunari Asari:
Biometric System by Foot Pressure Change Based on Neural Network. 18-23 - Syoji Kobashi, Yuko Fujimoto, Masayo Ogawa, Kumiko Ando, Reiichi Ishikura, Seturo Imawaki, Shozo Hirota, Yutaka Hata:
Fuzzy Logic Assisted Quantification of Gyral Deformation Index Using Magnetic Resonance Images for the Infantile Brain. 24-29 - Manabu Nii, Takafumi Yamaguchi, Yutaka Takahashi, Atsuko Uchinuno, Reiko Sakashita:
Fuzzy Rule Extraction from Nursing-Care Texts. 30-35
Current-Mode Logic
- Naoya Onizawa, Takahiro Hanyu:
Robust Multiple-Valued Current-Mode Circuit Components Based on Adaptive Reference-Voltage Control. 36-41 - Motoi Inaba, Koichi Tanno, Ryota Sawada, Hisashi Tanaka, Hiroki Tamura:
Optimization of Current-Mode MVD-ORNS Arithmetic Circuits. 42-47 - Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi:
16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin. 48-53 - Nobuaki Okada, Michitaka Kameyama:
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals. 54-59 - Takashi Matsuura, Hirokatsu Shirahama, Masanori Natsui
, Takahiro Hanyu:
Timing-Variation-Aware Multiple-Valued Current-Mode Circuit for a Low-Power Pipelined System. 60-65
Algebra
- Dan A. Simovici, Selim Mimaroglu:
Mining Approximative Descriptions of Sets Using Rough Sets. 66-71 - Boris A. Romov:
Positive Primitive Structures. 72-76 - Patrik Eklund, Maria A. Galán, Jari Kortelainen, Lawrence Neff Stout:
Paradigms for Non-classical Substitutions. 77-79 - Ramón Béjar, Cèsar Fernández, Carles Mateu, Nuria Pascual:
Bounding the Phase Transition on Edge Matching Puzzles. 80-85
Quantum Logic
- David J. Rosenbaum, Marek A. Perkowski:
Efficient Implementation of Controlled Operations for Multivalued Quantum Logic. 86-91 - Martin Lukac, Marek A. Perkowski:
Quantum Finite State Machines as Sequential Quantum Circuits. 92-97 - Md. Mahmud Muntakim Khan, Ayan Kumar Biswas, Shuvro Chowdhury, Masud Hasan, Asif Islam Khan:
Synthesis of GF(3) Based Reversible/Quantum Logic Circuits without Garbage Output. 98-102 - Mozammel H. A. Khan:
Quantum Realization of Multiple-Valued Feynman and Toffoli Gates without Ancilla Input. 103-108
Invited Talk 2
- Koki Nishizawa:
Multi-valued Modal Fixed Point Logics for Model Checking. 109-113
Clone Theory 1
- Karsten Schölzel:
Minimal Coverings of Maximal Partial Clones. 114-119 - Gustav Nordh, Bruno Zanuttini:
Frozen Boolean Partial Co-clones. 120-125 - Karsten Schölzel:
The Minimal Covering of Maximal Partial Clones in 4-valued Logic. 126-131
Logic Design and its Application
- David Y. Feinstein, Mitchell A. Thornton:
On the Guidance of Reversible Logic Synthesis by Dynamic Variable Reordering. 132-138 - Ali Razib, Scott Dick, Vincent C. Gaudet:
Design of a High-Speed Fuzzy Logic Controller Based on Log-Domain Arithmetic. 139-144 - Bambang A. B. Sarif, Mostafa I. H. Abd-El-Barr:
The Use of Multiple Connected Pseudo Minterms in the Synthesis of MVL Functions. 145-150 - Naotake Kamiura, Ayumu Saitoh, Teijiro Isokawa, Nobuyuki Matsui:
A Two-Pronged Approach of Power-Aware Voltage Scheduling for Real-Time Task Graphs in Multi-processor Systems. 151-156
Invited Talk 3
- Mitsuo Kawato:
Computational Neuroscience and Multiple-Valued Logic. 157-160
Clone Theory 2
- Hajime Machida, Jovanka Pantovic:
Hyperclones Determined by Total-Parts of Hyper-relations. 161-166 - Hajime Machida, Ivo G. Rosenberg:
On Endoprimal Monoids in Clone Theory. 167-172 - Lucien Haddad:
Partial Clones Containing All Selfdual Monotonic Boolean Partial Functions. 173-178
Spectrum Logic
- Claudio Moraga, Radomir S. Stankovic, Jaakko Astola:
On Periodic Patterns and their Spectra. 179-184 - Claudio Moraga:
Generalized Discrete Hartley Transforms. 185-190 - Ramón Béjar, Alba Cabiscol, Felip Manyà, Jordi Planes:
Generating Hard Instances for MaxSAT. 191-195 - Josep Argelich, Alba Cabiscol, Inês Lynce, Felip Manyà:
Regular Encodings from Max-CSP into Partial Max-SAT. 196-202
Invited Talk 4
- Ali Sheikholeslami:
Multi-level Signaling for Chip-to-Chip and Backplane Communication (A Tutorial). 203-207
Fuzzy and Rough Sets Theory, and their Application 1
- Hiroshi Sakai, Hiroshi Kimura, Michinori Nakata:
An Overview of a Software Tool in Rough Non-deterministic Information Analysis. 208-213 - Van-Nam Huynh, Yoshiteru Nakamori, Chenyi Hu, Vladik Kreinovich:
On Decision Making under Interval Uncertainty: A New Justification of Hurwicz Optimism-Pessimism Approach and its Use in Group Decision Making. 214-220 - Claudio Moraga, Michio Sugeno, Enric Trillas:
Optimization of Fuzzy If-Then Rule Bases by Evolutionary Tuning of the Operations. 221-226 - Noboru Takagi:
Non-convex Fuzzy Truth Values and De Morgan Bisemilattices. 227-232 - Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama:
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. 233-238
Multiple-Valued VLSI
- Yuichi Baba, Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki:
Multiple-Valued Constant-Power Adder for Cryptographic Processors. 239-244 - Masaki Murozuka, Kazumasa Ikeura, Fumiyuki Adachi, Kazuya Machida, Takao Waho:
Time-Interleaved Polyphase Decimation Filter Using Signed-Digit Adders. 245-249 - Yasushi Yuminaka, Yasunori Takahashi, Kenichi Henmi:
Multiple-Valued Data Transmission Based on Time-Domain Pre-emphasis Techniques in Consideration of Higher-Order Channel Effects. 250-255 - Satyendra R. Datla, Mitchell A. Thornton, Luther Hendrix, Dave Henderson:
Quaternary Addition Circuits Based on SUSLOC Voltage-Mode Cells and Modeling with SystemVerilog©. 256-261 - Milton E. R. Romero, Evandro Mazina Martins, Ricardo Ribeiro dos Santos:
Multiple Valued Logic Algebra for the Synthesis of Digital Circuits. 262-267
Invited Talk 5
- Zeljko Zilic:
Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age. 268-273
Fuzzy and Rough Sets Theory, and their Application 2
- Yasuo Kudo, Tetsuya Murai:
Attribute Reduction as Calculation of Focus in Granular Reasoning. 274-279 - Tomoko Ninomiya, Masao Mukaidono:
Clarifying the Systems of Axioms Based on the Method of Indeterminate Coefficients. 280-285 - Michinori Nakata, Hiroshi Sakai:
Applying Rough Sets to Information Tables Containing Missing Values. 286-291 - Mayuka F. Kawaguchi, Masaaki Miyakoshi:
Generalized Extended t-Norms as t-Norms of Type 2. 292-297
Logic Design
- André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler:
Evaluation of Cardinality Constraints on SMT-Based Debugging. 298-303 - Jaakko Astola, Radomir S. Stankovic:
Application of Covering Codes for Reduced Representations of Logic Functions. 304-311 - Takako Soma, Takashi Soma:
Ternary Logic by 3rd Subharmonics and its Application to Multiway Switches. 312-317 - Cicilia C. Lozano, Bogdan J. Falkowski, Tadeusz Luba:
Fixed Polarity Quaternary Transforms Derived from Linearly Independent Transform over GF(2) Structure. 318-323
Emerging Device
- Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. 324-330 - Seiya Kasai, Yuta Shiratori, Kensuke Miura, Nan-Jian Wu:
Multi-path Switching Device Utilizing a Multi-terminal Nanowire Junction for MDD-Based Logic Circuit. 331-336 - Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, Seiya Kasai:
Multiple-Valued Logic Gates Using Asymmetric Single-Electron Transistors. 337-342 - Mozammel H. A. Khan:
Scalable Architectures for Design of Reversible Quaternary Multiplexer and Demultiplexer Circuits. 343-348
Decision Diagrams and Reed-Muller Expansion
- Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler:
Floating-Point Numerical Function Generators Using EVMDDs for Monotone Elementary Functions. 349-355 - Hosam A. Aleem, David H. Green, Ferda Mavituna:
Representing the Genetic Code as a Function on a Galois Field Using the Reed-Muller Expansion. 356-361 - Tsutomu Sasao, Hiroki Nakahara, Munehiro Matsuura, Yoshifumi Kawamura, Jon T. Butler:
A Quaternary Decision Diagram Machine and the Optimization of its Code. 362-369 - Ashur Rafiev, Julian P. Murphy, Alexandre Yakovlev:
Quaternary Reed-Muller Expansions of Mixed Radix Arguments in Cryptographic Circuits. 370-376
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