default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI-SoC 2007: Atlanta, GA, USA - Selected Papers
- VLSI-SoC: Advanced Topics on Systems on a Chip - A Selection of Extended Versions of the Best Papers of the Fourteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2007), October 15-17, 2007, Atlanta, USA. IFIP 291, Springer 2009, ISBN 978-0-387-93845-5
- Gustavo Neuberger, Gilson I. Wirth
, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis:
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies. 1-16 - Osnat Keren, Ilya Levin, Radomir S. Stankovic:
Use of Gray Decoding for Implementation of Symmetric Functions. 1-16 - Sheng-Yu Peng, Paul E. Hasler, David V. Anderson:
A Programmable Multi-Dimensional Analog Radial-Basis- Function-Based Classifier. 1-20 - Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre:
Compression-based SoC Test Infrastructures. 1-15 - Jorge Fernandez Villena, Wil H. A. Schilders, L. Miguel Silveira:
Parametric Structure-Preserving Model Order Reduction. 1-20 - Marco Paolieri, Ivano Bonesana, Marco D. Santambrogio:
ReCPU: a Parallel and Pipelined Architecture for Regular Expression Matching. 1-20 - Aline Mello, Ney Calazans, Fernando Moraes:
QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques. 1-22 - Almitra Pradhan, Ranga Vemuri:
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis. 1-20 - Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Reis:
Statistical and Numerical Approach for a Computer efficient circuit yield analysis. 1-24 - Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like Prover Using Word Level Information. 1-17 - Julien Goulier, Eric André, Marc Renaudin:
A new analytical approach of the impact of jitter on continuous time delta sigma converters. 1-16 - Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto:
An adaptive genetic algorithm for dynamically reconfigurable modules allocation. 1-18 - Bassam Jamil Mohd, Earl E. Swartzlander Jr., Adnan Aziz:
The Hazard-Free Superscalar Pipeline Fast Fourier Transform Architecture and Algorithm. 1-22 - Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau:
System and Procesor Design Effort Estimation. 1-21 - Antonio Carlos Schneider Beck, Luigi Carro:
Reconfigurable Acceleration with Binary Compatibility for General Purpose Processors. 1-16 - Sameer Sharma, L. G. Johnson:
First Order, Quasi-Static, SOI Charge Conserving Power Dissipation Model. 1-23
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-16 22:54 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
