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Yao-Wen Chang
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- affiliation: National Taiwan University, Taipei, Taiwan
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2020 – today
- 2024
- [j117]Ziran Zhu
, Yangjie Mei, Kangkang Deng, Huan He
, Jianli Chen
, Jun Yang
, Yao-Wen Chang:
High-Performance Placement Engine for Modern Large-Scale FPGAs With Heterogeneity and Clock Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(3): 956-969 (2024) - [j116]Ziran Zhu, Yilin Li, Miaodi Su, Shu Zhang, Haiyuan Su, Yifeng Xiao, Huan He, Jianli Chen, Yao-Wen Chang:
Subgraph matching-based reference placement for printed circuit board designs. J. Supercomput. 80(16): 24324-24357 (2024) - [j115]Wei-Hsiang Tseng
, Yao-Wen Chang
:
A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits. ACM Trans. Design Autom. Electr. Syst. 29(6): 1-22 (2024) - [c259]Yan-Jen Chen
, Cheng-Hsiu Hsieh
, Po-Han Su
, Shao-Hsiang Chen
, Yao-Wen Chang
:
Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes. DAC 2024: 139:1-139:6 - [c258]Je-Wei Chuang
, Zong-Han Wu
, Bo-Ying Huang
, Yao-Wen Chang
:
Redistribution Layer Routing with Dynamic Via Insertion Under Irregular Via Structures. DAC 2024: 141:1-141:6 - [c257]Wei-Che Tseng
, Zong-Ying Cai
, Yi-Ping Huang
, Yu-Hsiang Lo
, Yao-Wen Chang
:
Late Breaking Results: Power Rail Routing for Advanced Multi-Layered Printed Circuit Boards. DAC 2024: 345:1-345:2 - [c256]Chien-Hao Tsou
, Sheng-Yah Lin
, Wei-Chen Hung
, Yao-Wen Chang
:
Late Breaking Results: Modern Automatic PCB Placement with Complex Constraints. DAC 2024: 346:1-346:2 - [c255]Zhifeng Lin, Min Wei, Yilu Chen, Peng Zou, Jianli Chen, Yao-Wen Chang:
Electrostatics-Based Analytical Global Placement for Timing Optimization. DATE 2024: 1-6 - [c254]Yao-Wen Chang
:
Physical Design Challenges in Modern Heterogeneous Integration. ISPD 2024: 125-134 - [c253]Wei-Hsiang Tseng
, Yao-Wen Chang
, Jie-Hong Roland Jiang
:
Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems. ISPD 2024: 245-253 - 2023
- [j114]Yao-Wen Chang, Yi-Hsuan Lai:
What attracts young talent from Taiwan to start businesses in mainland China? A fuzzy analytic hierarchy process study. Technol. Anal. Strateg. Manag. 35(4): 394-408 (2023) - [j113]Ping-Wei Huang
, Yao-Wen Chang
:
Routability-driven Power/Ground Network Optimization Based on Machine Learning. ACM Trans. Design Autom. Electr. Syst. 28(4): 53:1-53:27 (2023) - [j112]Min Wei
, Xingyu Tong
, Yuan Wen
, Jianli Chen
, Jun Yu
, Wenxing Zhu
, Yao-Wen Chang
:
Analytical Placement with 3D Poisson's Equation and ADMM-based Optimization for Large-scale 2.5D Heterogeneous FPGAs. ACM Trans. Design Autom. Electr. Syst. 28(5): 70:1-70:24 (2023) - [c252]Zhijie Cai
, Peng Zou, Zhengtao Wu, Xingyu Tong
, Jun Yu, Jianli Chen, Yao-Wen Chang:
PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration. DAC 2023: 1-6 - [c251]Wei-Hsu Chen, Yao-Wen Chang:
Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology. DAC 2023: 1-6 - [c250]Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang:
Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs. DAC 2023: 1-6 - [c249]Yan-Jen Chen, Yan-Syuan Chen, Wei-Che Tseng, Cheng-Yu Chiang, Yu-Hsiang Lo, Yao-Wen Chang:
Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies. DAC 2023: 1-2 - [c248]Min-Hsuan Chung, Je-Wei Chuang, Yao-Wen Chang:
Any-Angle Routing for Redistribution Layers in 2.5D IC Packages. DAC 2023: 1-6 - [c247]Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, Jianli Chen, Yao-Wen Chang:
A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints. DAC 2023: 1-6 - [c246]Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, Ziran Zhu, Huan He, Jianli Chen, Yao-Wen Chang:
Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints. DAC 2023: 1-6 - [c245]Wei-Hsiang Tseng, Yao-Wen Chang:
Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits. DAC 2023: 1-2 - [c244]Yan-Lin Chen, Wei-Che Tseng, Wei-Yao Kao, Yao-Wen Chang:
A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Provably Good Customized and Fault-Tolerant Topology Designs. ICCAD 2023: 1-7 - [c243]Chung-Chia Lee, Yao-Wen Chang:
Floorplanning for Embedded Multi-Die Interconnect Bridge Packages. ICCAD 2023: 1-8 - [c242]Jhih-Wei Hsu
, Kuan-Cheng Chen
, Yan-Syuan Chen
, Yu-Hsiang Lo
, Yao-Wen Chang
:
Security-aware Physical Design against Trojan Insertion, Frontside Probing, and Fault Injection Attacks. ISPD 2023: 220-228 - [i2]Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang:
Analytical Solution of Poisson's Equation with Application to VLSI Global Placement. CoRR abs/2307.12041 (2023) - 2022
- [j111]Jianli Chen
, Ziran Zhu, Longkun Guo
, Yu-Wei Tseng, Yao-Wen Chang:
Mixed-Cell-Height Placement With Drain-to-Drain Abutment and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1103-1115 (2022) - [j110]Yu-Sheng Lu
, Yan-Lin Chen, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Co-Design for Wavelength-Routed Optical Networks-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2237-2249 (2022) - [j109]Xiqiong Bai, Ziran Zhu, Pingping Li, Jianli Chen
, Tingshen Lan, Xingquan Li
, Jun Yu, Wenxing Zhu
, Yao-Wen Chang:
Timing-Aware Fill Insertions With Design-Rule and Density Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3529-3542 (2022) - [j108]Jianli Chen
, Zhifeng Lin, Yanyue Xie
, Wenxing Zhu
, Yao-Wen Chang:
Mixed-Cell-Height Placement With Complex Minimum-Implant-Area Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4639-4652 (2022) - [j107]Yu-Sheng Lu
, Sheng-Jung Yu
, Yao-Wen Chang:
On-Chip Optical Routing With Provably Good Algorithms for Path Clustering and Assignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 4653-4666 (2022) - [j106]Jianli Chen
, Zhipeng Huang, Ziran Zhu, Zheng Peng, Wenxing Zhu
, Yao-Wen Chang:
Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5541-5553 (2022) - [j105]Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Via-Based Redistribution Layer Routing for InFO Packages With Irregular Pad Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5554-5567 (2022) - [j104]Wei-Hsiang Tseng
, Chen-Hao Hsu
, Wan-Hsuan Lin
, Yao-Wen Chang:
A Bridge-Based Compression Algorithm for Topological Quantum Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5582-5595 (2022) - [c241]Xiqiong Bai, Ziran Zhu, Peng Zou
, Jianli Chen, Jun Yu, Yao-Wen Chang:
Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification. ASP-DAC 2022: 172-177 - [c240]Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang:
High-Correlation 3D Routability Estimation for Congestion-guided Global Routing. ASP-DAC 2022: 580-585 - [c239]Wei-Hsiang Tseng, Yao-Wen Chang:
A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuits. DAC 2022: 535-540 - [c238]Huimin Wang, Xingyu Tong
, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang:
CNN-inspired analytical global placement for large-scale heterogeneous FPGAs. DAC 2022: 637-642 - [c237]Ziran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang:
High-performance placement for large-scale heterogeneous FPGAs with clock constraints. DAC 2022: 643-648 - [c236]Szu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang:
Y-architecture-based flip-chip routing with dynamic programming-based bend minimization. DAC 2022: 955-960 - [c235]Yu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang:
Thermal-aware optical-electrical routing codesign for on-chip signal communications. DAC 2022: 1279-1284 - [c234]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible chip placement via reinforcement learning: late breaking results. DAC 2022: 1392-1393 - [c233]Miaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang:
Subgraph matching based reference placement for PCB designs: late breaking results. DAC 2022: 1400-1401 - [c232]Yang Hsu, Min-Hsuan Chung, Yao-Wen Chang, Ci-Hong Lin:
Transitive Closure Graph-Based Warpage-Aware Floorplanning for Package Designs. ICCAD 2022: 16:1-16:7 - [c231]Yen-Ting Chen, Yao-Wen Chang:
Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures. ICCAD 2022: 65:1-65:6 - [c230]Cheng-Yuan Wang, Yao-Wen Chang, Yuan-Hao Chang:
SGIRR: Sparse Graph Index Remapping for ReRAM Crossbar Operation Unit and Power Optimization. ICCAD 2022: 165:1-165:7 - [c229]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Charlie Chung-Ping Chen:
Intelligent Design Automation for Heterogeneous Integration. ISPD 2022: 105-106 - [i1]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR abs/2204.06407 (2022) - 2021
- [j103]Chen-Hao Hsu
, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang:
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 533-546 (2021) - [j102]Jianli Chen, Yao-Wen Chang, Yu-Chen Huang:
Analytical Placement Considering the Electron-Beam Fogging Effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 560-573 (2021) - [j101]Jianli Chen, Yao-Wen Chang, Yen-Yi Wu:
Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2128-2141 (2021) - [j100]Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
A Robust Modulus-Based Matrix Splitting Iteration Method for Mixed-Cell-Height Circuit Legalization. ACM Trans. Design Autom. Electr. Syst. 26(2): 15:1-15:28 (2021) - [c228]Bingshu Wang, Lanfan Jiang, Wenxing Zhu, Longkun Guo, Jianli Chen, Yao-Wen Chang:
Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection. DAC 2021: 175-180 - [c227]Chen-Hao Hsu, Wan-Hsuan Lin
, Wei-Hsiang Tseng, Yao-Wen Chang:
A Bridge-based Compression Algorithm for Topological Quantum Circuits. DAC 2021: 457-462 - [c226]Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen:
VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. DAC 2021: 1117-1122 - [c225]Ming-Hung Chen
, Yao-Wen Chang, Jun-Jie Wang:
Performance-Driven Simultaneous Partitioning and Routing for Multi-FPGA Systems. DAC 2021: 1129-1134 - [c224]Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Simultaneous Pre- and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias. DAC 2021: 1147-1152 - [c223]Zhifeng Lin, Yanyue Xie, Gang Qian, Jianli Chen, Sifei Wang, Jun Yu, Yao-Wen Chang:
Timing-Driven Placement for FPGAs with Heterogeneous Architectures and Clock Constraints. DATE 2021: 1564-1569 - [c222]Fu-Yu Chuang, Yao-Wen Chang:
On-chip Optical Routing with Waveguide Matching Constraints. ICCAD 2021: 1-6 - [c221]Zih-Yao Lin, Yao-Wen Chang:
A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement. ICCAD 2021: 1-6 - [c220]Wei-Kai Liu
, Ming-Hung Chen
, Chia-Ming Chang, Chen-Chia Chang, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing. ICCAD 2021: 1-6 - [c219]Cheng-Ying Hsieh, Yao-Wen Chang, Chien Chen, Jyh-Cheng Chen:
Design and implementation of a generic 5G user plane function development framework. MobiCom 2021: 846-848 - [c218]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Opportunities for 2.5/3D Heterogeneous SoC Integration. VLSI-DAT 2021: 1 - 2020
- [j99]Jianli Chen, Zhifeng Lin, Yun-Chih Kuo, Chau-Chin Huang, Yao-Wen Chang, Shih-Chun Chen, Chun-Han Chiang, Sy-Yen Kuo
:
Clock-Aware Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5042-5055 (2020) - [j98]Ziran Zhu
, Jianli Chen, Wenxing Zhu
, Yao-Wen Chang:
Mixed-Cell-Height Legalization Considering Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5128-5141 (2020) - [c217]Chun-Han Chiang, Fu-Yu Chuang, Yao-Wen Chang:
Unified Redistribution Layer Routing for 2.5D IC Packages. ASP-DAC 2020: 331-337 - [c216]Jianli Chen, Zhipeng Huang, Ye Huang, Wenxing Zhu, Jun Yu, Yao-Wen Chang:
An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells *. DAC 2020: 1-6 - [c215]Jianli Chen, Ziran Zhu, Qinghai Liu, Yimin Zhang, Wenxing Zhu, Yao-Wen Chang:
Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation. DAC 2020: 1-6 - [c214]Chau-Chin Huang, Gustavo E. Téllez, Gi-Joon Nam, Yao-Wen Chang:
Latch Clustering for Timing-Power Co-Optimization. DAC 2020: 1-6 - [c213]Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. DAC 2020: 1-6 - [c212]Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang:
A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. DAC 2020: 1-6 - [c211]Hsiang-Ting Wen, Yu-Jie Cai, Yang Hsu, Yao-Wen Chang:
Via-based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures. DAC 2020: 1-6 - [c210]Peng Zou
, Zhifeng Lin, Xiao Shi, Yingjie Wu, Jianli Chen, Jun Yu, Yao-Wen Chang:
Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification. DAC 2020: 1-6 - [c209]Run-Yi Wang, Yao-Wen Chang:
Routability-Aware Pin Access Optimization for Monolithic 3D Designs. ICCAD 2020: 2:1-2:6 - [c208]Iris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen:
Intelligent Design Automation for 2.5/3D Heterogeneous SoC Integration. ICCAD 2020: 125:1-125:7 - [c207]Chieh Roger Lo, Teng-Hao Yeh, Wei-Chen Chen, Hang-Ting Lue
, Keh-Chung Wang, Chih-Yuan Lu, Yao-Wen Chang, Yung-Hsiang Chen, Chu-Yung Liu:
Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. IRPS 2020: 1-6
2010 – 2019
- 2019
- [j97]Dar-Ren Chen, Yao-Wen Chang, Hwa-Koon Wu, Wei-Chung Shia
, Yu-Len Huang
:
Multiview Contouring for Breast Tumor on Magnetic Resonance Imaging. J. Digit. Imaging 32(5): 713-727 (2019) - [j96]Yu-Hsuan Su, Yao-Wen Chang
:
DSA-Compliant Routing for 2-D Patterns Using Block Copolymer Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 267-280 (2019) - [j95]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg
, Chip-Hong Chang
, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti
, Shiro Dosho, Rolf Drechsler
, Ibrahim Abe M. Elfadel
, Ruonan Han, Masanori Hashimoto
, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho
, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun
, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra
, Baker Mohammad
, Mehran Mozaffari Kermani
, Makoto Nagata
, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont
, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan
, Mark M. Tehranipoor, Aida Todri-Sanial
, Marian Verhelst
, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang
, Jun Zhou, Mark Zwolinski
, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [c206]Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo
:
MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. ASP-DAC 2019: 557-562 - [c205]Fan-Keng Sun, Yao-Wen Chang:
BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement. DAC 2019: 118 - [c204]Chen-Hao Hsu, Shao-Chun Hung, Hao Chen, Fan-Keng Sun, Yao-Wen Chang:
A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. DAC 2019: 217 - [c203]Yu-Hsuan Chang, Hsiang-Ting Wen, Yao-Wen Chang:
Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs. ICCAD 2019: 1-8 - [c202]Jianli Chen, Wenxing Zhu, Jun Yu, Lei He, Yao-Wen Chang:
Analytical Placement with 3D Poisson's Equation and ADMM Based Optimization for Large-Scale 2.5D Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c201]Tingshen Lan, Xingquan Li
, Jianli Chen, Jun Yu, Lei He, Senhua Dong, Wenxing Zhu, Yao-Wen Chang:
Timing-Aware Fill Insertions with Design-Rule and Density Constraints. ICCAD 2019: 1-8 - [c200]Zhan-Ling Wang, Yao-Wen Chang:
Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly. ICCAD 2019: 1-7 - [c199]Xingquan Li
, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization. ISPD 2019: 27-34 - 2018
- [j94]Chau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang
, Tung-Chieh Chen, Ismail Bustany:
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 669-681 (2018) - [j93]Zhi-Wen Lin
, Shao-Yun Fang
, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan:
Provably Good Max-Min-m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. IEEE Trans. Very Large Scale Integr. Syst. 26(2): 378-391 (2018) - [c198]Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang:
WB-trees: a meshed tree representation for FinFET analog layout designs. DAC 2018: 9:1-9:6 - [c197]Run-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang:
Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree construction. DAC 2018: 45:1-45:6 - [c196]Hai-Juan Yu, Yao-Wen Chang:
DSA-friendly detailed routing considering double patterning and DSA template assignments. DAC 2018: 49:1-49:6 - [c195]Ziran Zhu, Jianli Chen, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Generalized augmented lagrangian and its applications to VLSI global placement. DAC 2018: 149:1-149:6 - [c194]Wenxing Zhu, Zhipeng Huang, Jianli Chen, Yao-Wen Chang:
Analytical solution of Poisson's equation and its application to VLSI global placement. ICCAD 2018: 2 - [c193]Jianli Chen, Li Yang
, Zheng Peng, Wenxing Zhu, Yao-Wen Chang:
Novel proximal group ADMM for placement considering fogging and proximity effects. ICCAD 2018: 3 - [c192]Shih-Chun Chen, Richard Sun, Yao-Wen Chang:
Simultaneous partitioning and signals grouping for time-division multiplexing in 2.5D FPGA-based systems. ICCAD 2018: 4 - [c191]Yu-Wei Tseng, Yao-Wen Chang:
Mixed-cell-height placement considering drain-to-drain abutment. ICCAD 2018: 64 - [c190]Ziran Zhu, Xingquan Li, Yuhang Chen, Jianli Chen, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height legalization considering technology and region constraints. ICCAD 2018: 65 - [c189]Jianli Chen, Peng Yang, Xingquan Li, Wenxing Zhu, Yao-Wen Chang:
Mixed-cell-height placement with complex minimum-implant-area constraints. ICCAD 2018: 66 - [c188]Fan-Keng Sun, Hao Chen, Ching-Yu Chen, Chen-Hao Hsu
, Yao-Wen Chang:
A multithreaded initial detailed routing algorithm considering global routing guides. ICCAD 2018: 82 - 2017
- [j92]Yao-Wen Chang:
An Interview With Professor Chenming Hu, Father of 3D Transistors. IEEE Des. Test 34(5): 90-96 (2017) - [j91]Yu-Hsuan Su, Yao-Wen Chang
:
Nanowire-Aware Routing Considering High Cut Mask Complexity. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(6): 964-977 (2017) - [j90]Zhi-Wen Lin, Yao-Wen Chang
:
Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2066-2079 (2017) - [j89]Krishnendu Chakrabarty
, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho
, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark M. Tehranipoor, Aida Todri-Sanial
, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson:
Editorial. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 1-20 (2017) - [c187]Chao-Hung Wang, Yen-Yi Wu, Jianli Chen, Yao-Wen Chang, Sy-Yen Kuo
, Wenxing Zhu, Genghua Fan:
An effective legalization algorithm for mixed-cell-height standard cells. ASP-DAC 2017: 450-455 - [c186]Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. DAC 2017: 52:1-52:6 - [c185]Yu-Chen Huang, Yao-Wen Chang:
Fogging Effect Aware Placement in Electron Beam Lithography. DAC 2017: 53:1-53:6 - [c184]Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang:
Graph-Based Logic Bit Slicing for Datapath