EURO-DAC 1996: Geneva, Switzerland

Analog and Mixed Mode Simulation

Low Power Synthesis

Design Experience

Timing Modeling

Design Flow and Design Management

Partitioning

Logic & FSM Synthesis

BDD Optimization Techniques

Codesign Methodology and Cospecification

System Level Design & Synthesis

New Aspects on Testing

Codesign Methodology & Cosimulation

Key Technologies and CAD of Microsystems

Asynchronous Synthesis and Storage Optimization

Modelling, Simulation of Microsystems and Multi Layer Routing in PCBs

Timing Issues in Synthesis

Physical Design for Deep Submicron

Architectural Synthesis Techniques

CAD for Analog Circuit

Analysis Tools

Beyond VHDL

Fault Modeling and Design for Testability

Modeling Methodologies

Synthesis

System Level Design

VHDL & Mixed Signal Design

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