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"Process variations aware robust on-chip bus architecture synthesis for MPSoCs."

Sujan Pandey et al. (2008)

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DOI: 10.1109/ISCAS.2008.4542086

access: closed

type: Conference or Workshop Paper

metadata version: 2019-06-02

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  dblp key:
  - conf/iscas/PandeyDMG08
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  - https://dblp.org/rec/conf/iscas/PandeyDMG08
Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992

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