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ORCID61st DAC 2024: San Francisco, CA, USA
- Vivek De:
Proceedings of the 61st ACM/IEEE Design Automation Conference, DAC 2024, San Francisco, CA, USA, June 23-27, 2024. ACM 2024, ISBN 979-8-4007-0601-1 - Junyao Wang
, Mohammad Abdullah Al Faruque:
SMORE: Similarity-Based Hyperdimensional Domain Adaptation for Multi-Sensor Time Series Classification. 1:1-1:6 - Yifan Zhu, Peinan Li, Yunkai Bai, Yubiao Huang, Shiwen Wang, Xingbin Wang, Dan Meng, Rui Hou:
EnTurbo: Accelerate Confidential Serverless Computing via Parallelizing Enclave Startup Procedure. 2:1-2:6 - Yunkai Bai, Peinan Li, Yubiao Huang, Shiwen Wang, Xingbin Wang, Dan Meng, Rui Hou:
SecPaging: Secure Enclave Paging with Hardware-Enforced Protection against Controlled-Channel Attacks. 3:1-3:6 - Runzhen Xue, Mingyu Yan, Dengke Han, Yihan Teng, Zhimin Tang, Xiaochun Ye, Dongrui Fan:
GDR-HGNN: A Heterogeneous Graph Neural Networks Accelerator Frontend with Graph Decoupling and Recoupling. 4:1-4:6 - Yan Wang, Xingbin Wang, Zechao Lin, Yulan Su, Sisi Zhang, Rui Hou, Dan Meng:
Garrison: A High-Performance GPU-Accelerated Inference System for Adversarial Ensemble Defense. 5:1-5:6 - Yunkun Liao, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
PHD: Parallel Huffman Decoder on FPGA for Extreme Performance and Energy Efficiency. 6:1-6:6 - Hanwei Fan, Ya Wang, Sicheng Li, Tingyuan Liang, Wei Zhang:
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration. 7:1-7:6 - Ali Hajiabadi, Archit Agarwal, Andreas Diavastos, Trevor E. Carlson:
Levioso: Efficient Compiler-Informed Secure Speculation. 8:1-8:6 - Ali Hajiabadi, Trevor E. Carlson:
Conjuring: Leaking Control Flow via Speculative Fetch Attacks. 9:1-9:6 - Fangxin Liu, Ning Yang, Zhiyan Song, Zongwu Wang, Haomin Li, Shiyuan Huang, Zhuoran Song, Songwen Pei, Li Jiang:
INSPIRE: Accelerating Deep Neural Networks via Hardware-friendly Index-Pair Encoding. 10:1-10:6 - Che Chang, Tsung-Wei Huang, Dian-Lun Lin, Guannan Guo, Shiju Lin:
Ink: Efficient Incremental k-Critical Path Generation. 11:1-11:6 - Chenyu Wang, Zhen Dong, Daquan Zhou, Zhenhua Zhu, Yu Wang, Jiashi Feng, Kurt Keutzer:
EPIM: Efficient Processing-In-Memory Accelerators based on Epitome. 12:1-12:6 - Tuo Dai, Bizhao Shi, Guojie Luo:
G2PM: Performance Modeling for ACAP Architecture with Dual-Tiered Graph Representation Learning. 13:1-13:6 - Bizhao Shi, Tuo Dai, Jiaxi Zhang, Xuechao Wei, Guojie Luo:
PT-Map: Efficient Program Transformation Optimization for CGRA Mapping. 14:1-14:6 - Sunghye Park, Dohun Kim, Seokhyeong Kang:
HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication. 15:1-15:6 - Zhuo Su, Zehong Yu, Dongyan Wang, Rui Wang, Yang Tao, Yu Jiang:
CFTCG: Test Case Generation for Simulink Model through Code Based Fuzzing. 16:1-16:6 - Jiarui Wang, Xun Jiang, Yibo Lin:
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing. 17:1-17:6 - Tian-Fu Chen, Jie-Hong Roland Jiang:
Boolean Matching Reversible Circuits: Algorithm and Complexity. 18:1-18:6 - Chia-Wei Lin, Jing-Yao Weng, I-Te Lin, Ho-Chieh Hsu, Chia-Ming Liu, Mark Po-Hung Lin:
Voronoi Diagram-based Multiple Power Plane Generation on Redistribution Layers in 3D ICs. 19:1-19:6 - Zehong Yu, Zhuo Su, Yu Jiang, Aiguo Cui, Rui Wang:
Efficient Code Generation for Data-Intensive Simulink Models via Redundancy Elimination. 20:1-20:6 - Yifan Cheng, Zehong Yu, Zhuo Su, Ting Chen, Xiaosong Zhang, Yu Jiang:
AccMoS: Accelerating Model Simulation for Simulink via Code Generation. 21:1-21:6 - Zhiheng Yue, Shaojun Wei, Yang Hu, Shouyi Yin:
CAP: A General Purpose Computation-in-memory with Content Addressable Processing Paradigm. 22:1-22:6 - Hiroshi Sawada, Kazuo Aoyama, Kohei Ikeda:
Zeroth-Order Optimization of Optical Neural Networks with Linear Combination Natural Gradient and Calibrated Model. 23:1-23:6 - Yansong Xu, Dongxu Lyu, Zhenyu Li, Yuzhou Chen, Zilong Wang, Gang Wang, Zhican Wang, Haomin Li, Guanghui He:
DEFA: Efficient Deformable Attention Acceleration via Pruning-Assisted Grid-Sampling and Multi-Scale Parallel Processing. 24:1-24:6 - Hashan Roshantha Mendis, Chih-Kai Kang, Chun-Han Lin, Ming-Syan Chen, Pi-Cheng Hsiu:
Deep Reorganization: Retaining Residuals in TinyML. 25:1-25:6 - Jianan Mu, Husheng Han, Shangyi Shi, Jing Ye, Zizhen Liu, Shengwen Liang, Meng Li, Mingzhe Zhang, Song Bian, Xing Hu, Huawei Li, Xiaowei Li:
Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption. 26:1-26:6 - Chengning Wang, Dan Feng, Yuchong Hu, Wei Tong, Jingning Liu:
STAGGER: Enabling All-in-One Subarray Sensing for Efficient Module-level Processing in Open-Bitline ReRAM. 27:1-27:6 - Xin Zhang, Zhi Zhang, Qingni Shen, Wenhao Wang, Yansong Gao, Zhuoxi Yang, Zhonghai Wu:
ThermalScope: A Practical Interrupt Side Channel Attack Based on Thermal Event Interrupts. 28:1-28:6 - Ruiyang Qin, Jun Xia, Zhenge Jia, Meng Jiang, Ahmed Abbasi, Peipei Zhou, Jingtong Hu, Yiyu Shi:
Enabling On-Device Large Language Model Personalization with Self-Supervised Data Selection and Synthesis. 29:1-29:6 - Sven Thijssen, Muhammad Rashedul Haq Rashed, Sumit Kumar Jha, Rickard Ewetz:
Synthesis of Compact Flow-based Computing Circuits from Boolean Expressions. 30:1-30:6 - Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun:
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. 31:1-31:6 - Wang Fang, Mingsheng Ying:
SymPhase: Phase Symbolization for Fast Simulation of Stabilizer Circuits. 32:1-32:6 - Muhammad Rashedul Haq Rashed, Sven Thijssen, Dominic Simon, Sumit Jha, Rickard Ewetz:
Execution Sequence Optimization for Processing In-Memory using Parallel Data Preparation. 33:1-33:6 - Weikai Xu, Jin Luo, Qianqian Huang, Ru Huang:
Compact and Efficient CAM Architecture through Combinatorial Encoding and Self-Terminating Searching for In-Memory-Searching Accelerator. 34:1-34:6 - Xujiang Xiang, Zhiheng Yue, Yuxuan Li, Liuxin Lv, Shaojun Wei, Yang Hu, Shouyi Yin:
Dyn-Bitpool: A Two-sided Sparse CIM Accelerator Featuring a Balanced Workload Scheme and High CIM Macro Utilization. 35:1-35:6 - Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. 36:1-36:6 - Xin Zhao, Zhicheng Hu, Zilong Guo, Haodong Fan, Xi Yang, Jing Zhou, Liang Chang:
A RRAM-based High Energy-efficient Accelerator Supporting Multimodal Tasks for Virtual Reality Wearable Devices. 37:1-37:6 - HoSun Choi, Chanho Park, Euijun Kim, William J. Song:
Nona: Accurate Power Prediction Model Using Neural Networks. 38:1-38:6 - Zihao Chen, Jiangli Huang, Yiting Liu, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng:
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model. 39:1-39:6 - Anastasis Vagenas, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George I. Stamoulis:
Advanced gate-level glitch modeling using ANNs. 40:1-40:6 - Sunan Zou, Guojie Luo:
PONO: Power Optimization with Near Optimal SMT-based Sub-circuit Generation. 41:1-41:6 - Xueyuan Liu, Zhuoran Song, Hao Chen, Xing Li, Xiaoyao Liang:
MoC: A Morton-Code-Based Fine-Grained Quantization for Accelerating Point Cloud Neural Networks. 42:1-42:6 - Haishuang Fan, Qichu Sun, Jingya Wu, Wenyan Lu, Xiaowei Li, Guihai Yan:
Co-Via: A Video Frame Interpolation Accelerator Exploiting Codec Information Reuse. 43:1-43:6 - Ranyang Zhou, Sabbir Ahmed, Adnan Siraj Rakin, Shaahin Angizi:
DNN-Defender: A Victim-Focused In-DRAM Defense Mechanism for Taming Adversarial Weight Attack on DNNs. 44:1-44:6 - Tianyu Guo, Xuanteng Huang, Kan Wu, Xianwei Zhang, Nong Xiao:
SMILE: LLC-based Shared Memory Expansion to Improve GPU Thread Level Parallelism. 45:1-45:6 - Junzhuo Zhou, Li Huang, Haoxuan Xia, Yihui Cai, Leilei Jin, Xiao Shi, Wei W. Xing, Ting-Jung Lin, Lei He:
LVF2: A Statistical Timing Model based on Gaussian Mixture for Yield Estimation and Speed Binning. 46:1-46:6 - Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang:
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. 47:1-47:6 - Ning Lin, Shaocong Wang, Yue Zhang, Yangu He, Kwunhang Wong, Arindam Basu, Dashan Shang, Xiaoming Chen, Zhongrui Wang:
Older and Wiser: The Marriage of Device Aging and Intellectual Property Protection of DNNs. 48:1-48:6 - Shuyao Cheng, Chongxiao Li, Zidong Du, Rui Zhang, Xing Hu, Xiaqing Li, Guanglin Xu, Yuanbo Wen, Qi Guo:
Revisiting Automatic Pipelining: Gate-level Forwarding and Speculation. 49:1-49:6 - Kevin Mato, Stefan Hillmich, Robert Wille:
Mixed-Dimensional Qudit State Preparation Using Edge-Weighted Decision Diagrams. 50:1-50:6 - Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler:
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. 51:1-51:6 - Nguyen-Dong Ho, Gyujun Jeong, Cheol-Min Kang, Seungkyu Choi, Ik-Joon Chang:
MERSIT: A Hardware-Efficient 8-bit Data Format with Enhanced Post-Training Quantization DNN Accuracy. 52:1-52:6 - Yunda Tsai, Mingjie Liu, Haoxing Ren:
RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Model. 53:1-53:6 - Cheng Chu, Zhenxiao Fu, Yilun Xu, Gang Huang, Hausi A. Müller, Fan Chen, Lei Jiang:
TITAN: A Fast and Distributed Large-Scale Trapped-Ion NISQ Computer. 54:1-54:6 - Vidushi Goyal, Valeria Bertacco, Reetuparna Das:
Duet: A Collaborative User Driven Recommendation System for Edge Devices. 55:1-55:6 - Tianqi Zhang, Neha Prakriya, Sumukh Pinge, Jason Cong, Tajana Rosing:
SpectraFlux: Harnessing the Flow of Multi-FPGA in Mass Spectrometry Clustering. 56:1-56:6 - Zeyu Guo, Jinshan Yue, Shengzhe Yan, Zhuoyu Dai, Xiangqu Fu, Zhaori Cong, Zening Niu, Ke Hu, Lihua Xu, Jiawei Wang, Lingfei Wang, Guanhua Yang, Di Geng, Ling Li:
IG-CRM: Area/Energy-Efficient IGZO-Based Circuits and Architecture Design for Reconfigurable CIM/CAM Applications. 57:1-57:6 - Ning Yang, Fangxin Liu, Zongwu Wang, Haomin Li, Zhuoran Song, Songwen Pei, Li Jiang:
EOS: An Energy-Oriented Attack Framework for Spiking Neural Networks. 58:1-58:6 - Jinhyo Jung, Hwisoo So, Woobin Ko, Sumedh Shridhar Joshi, Yebon Kim, Yohan Ko, Aviral Shrivastava, Kyoungwoo Lee:
Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs. 59:1-59:6 - Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, Yinhe Han, Huawei Li, Xiaowei Li:
Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework. 60:1-60:6 - Yi Wang, Huan Liu, Jianan Yuan, Jiaxian Chen, Tianyu Wang, Chenlin Ma, Rui Mao:
Leanor: A Learning-Based Accelerator for Efficient Approximate Nearest Neighbor Search via Reduced Memory Access. 61:1-61:6 - Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie:
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. 62:1-62:6 - Yucong Huang, Jingyu He, Kwang-Ting (Tim) Cheng, Chi-Ying Tsui, Terry Tao Ye:
RWriC: A Dynamic Writing Scheme for Variation Compensation for RRAM-based In-Memory Computing. 63:1-63:6 - Qingjie Zhang, Lijun Chi, Di Wang, Mounira Msahli, Gérard Memmi, Tianwei Zhang, Chao Zhang, Han Qiu:
Laser Shield: a Physical Defense with Polarizer against Laser Attacks on Autonomous Driving Systems. 65:1-65:6 - Pengcheng Qiu, Guiming Wu, Tingqiang Chu, Changzheng Wei, Runzhou Luo, Ying Yan, Wei Wang, Hui Zhang:
MSMAC: Accelerating Multi-Scalar Multiplication for Zero-Knowledge Proof. 66:1-66:6 - Yuxuan Qin, Chuxiong Lin, Mingche Lai, Zhang Luo, Shi Xu, Weifeng He:
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption. 67:1-67:6 - Zhuoran Song, Chunyu Qi, Yuanzheng Yao, Peng Zhou, Yanyi Zi, Nan Wang, Xiaoyao Liang:
TSAcc: An Efficient \underline{T}empo-\underline{S}patial Similarity Aware \underline{Acc}elerator for Attention Acceleration. 68:1-68:6 - Yinan Xu, Sa Wang, Dan Tang, Ninghui Sun, Yungang Bao:
PathFuzz: Broadening Fuzzing Horizons with Footprint Memory for CPUs. 69:1-69:6 - Hanrui Zhao, Niuniu Qi, Mengxin Ren, Xia Zeng, Zhenbing Zeng, Zhengfeng Yang:
Neural Barrier Certificates Synthesis of NN-Controlled Continuous Systems via Counterexample-Guided Learning. 70:1-70:6 - Shiju Lin, Guannan Guo, Tsung-Wei Huang, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
GCS-Timer: GPU-Accelerated Current Source Model Based Static Timing Analysis. 71:1-71:6 - Jaekyung Im, Seokhyeong Kang:
SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation. 72:1-72:6 - Nils Bosbach, Niko Zurstraßen, Rebecca Pelke, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers:
Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models. 73:1-73:6 - Weijie Fang, Longkun Guo, Jiawei Lin, Silu Xiong, Huan He, Jiacen Xu, Jianli Chen:
Obstacle-Aware Length-Matching Routing for Any-Direction Traces in Printed Circuit Board. 74:1-74:6 - Zhidan Zheng, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, Ulf Schlichtmann:
Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. 74:1-74:6 - Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. 75:1-75:6 - Boyang Zhang, Dian-Lun Lin, Che Chang, Cheng-Hsiang Chiu, Bojue Wang, Wan-Luan Lee, Chih-Chun Chang, Donghao Fang, Tsung-Wei Huang:
G-PASTA: GPU-Accelerated Partitioning Algorithm for Static Timing Analysis. 76:1-76:6 - Baharealsadat Parchamdar, Benjamin Carrión Schäfer:
Finding Bugs in RTL Descriptions: High-Level Synthesis to the Rescue. 77:1-77:6 - Anni Lu, Junmo Lee, Yuan-Chun Luo, Hai Li, Ian A. Young, Shimeng Yu:
Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. 78:1-78:6 - Eunji Kwon, Minxuan Zhou, Weihong Xu, Tajana Rosing, Seokhyeong Kang:
RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers. 79:1-79:6 - Prasanth Mangalagiri, Lynn Qian, Farrukh Zafar, Praveen Mosalikanti, Phoebe Chang, Arun Kurian, Vinay Saripalli:
CDLS: Constraint Driven Generative AI Framework for Analog Layout Synthesis. 80:1-80:6 - Md. Abdullah-Al Kaiser, Gourav Datta, Peter A. Beerel, Akhilesh R. Jaiswal:
Toward High-Accuracy, Programmable Extreme-Edge Intelligence for Neuromorphic Vision Sensors utilizing Magnetic Domain Wall Motion-based MTJ. 81:1-81:6 - Hsu-Yu Huang, Chu-Yun Hsiao, Tsung-Te Liu, James Chien-Mo Li:
Low-Complexity Algorithmic Test Generation for Neuromorphic Chips. 82:1-82:6 - Meng Liu, Shuai Li, Fei Xiao, Ruijie Wang, Chunxue Liu, Liang Wang:
SSRESF: Sensitivity-aware Single-particle Radiation Effects Simulation Framework in SoC Platforms based on SVM Algorithm. 83:1-83:6 - Chentao Jia, Ming Hu, Zekai Chen, Yanxin Yang, Xiaofei Xie, Yang Liu, Mingsong Chen:
AdaptiveFL: Adaptive Heterogeneous Federated Learning for Resource-Constrained AIoT Systems. 84:1-84:6 - Ying-Jie Jiang, Shao-Yun Fang:
Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization. 85:1-85:6 - Zhiyu An, Xianzhong Ding, Wan Du:
Go Beyond Black-box Policies: Rethinking the Design of Learning Agent for Interpretable and Verifiable HVAC Control. 86:1-86:6 - Zixiao Wang, Yunheng Shen, Xufeng Yao, Wenqian Zhao, Yang Bai, Farzan Farnia, Bei Yu:
ChatPattern: Layout Pattern Customization via Natural Language. 87:1-87:6 - Ruisi Zhang, Farinaz Koushanfar:
EmMark: Robust Watermarks for IP Protection of Embedded Quantized Large Language Models. 88:1-88:6 - Ruoyan Ma, Shengan Zheng, Guifeng Wang, Jin Pu, Yifan Hua, Wentao Wang, Linpeng Huang:
Accelerating Regular Path Queries over Graph Database with Processing-in-Memory. 89:1-89:6 - Kaihong Huang, Dian Shen, Zhaoyang Wang, Juntao Yang, Beilun Wang:
Hynify: A High-throughput and Unified Accelerator for Multi-Mode Nonparametric Statistics. 90:1-90:6 - Hanyu Zhang, Liqiang Lu, Siwei Tan, Size Zheng, Jia Yu, Jianwei Yin:
SpREM: Exploiting Hamming Sparsity for Fast Quantum Readout Error Mitigation. 91:1-91:6 - Shounak Chakraborty, Sangeet Saha, Magnus Själander, Klaus D. McDonald-Maier:
MAFin: Maximizing Accuracy in FinFET based Approximated Real-Time Computing. 92:1-92:6 - Zhenyu Bai, Pranav Dangi, Huize Li, Tulika Mitra:
SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs. 93:1-93:6 - Changxu Liu, Hao Zhou, Lan Yang, Jiamin Xu, Patrick Dai, Fan Yang:
Gypsophila: A Scalable and Bandwidth-Optimized Multi-Scalar Multiplication Architecture. 94:1-94:6 - Yuan Zhang, Kuncai Zhong, Jiliang Zhang:
DH-TRNG: A Dynamic Hybrid TRNG with Ultra-High Throughput and Area-Energy Efficiency. 95:1-95:6 - Hongyi Wang, Kai Zhong, Haoyu Zhang, Shulin Zeng, Zhenhua Zhu, Xinhao Yang, Shuang Wang, Guohao Dai, Huazhong Yang, Yu Wang:
DySpMM: From Fix to Dynamic for Sparse Matrix-Matrix Multiplication Accelerators. 96:1-96:6 - Hyungjoon Bae, Da Won Kim, Wanyeong Jung:
VVIP: Versatile Vertical Indexing Processor for Edge Computing. 97:1-97:6 - Haoyu Wang, Basel Halak, Jianjie Ren, Ahmad Atamli:
DL2Fence: Integrating Deep Learning and Frame Fusion for Enhanced Detection and Localization of Refined Denial-of-Service in Large-Scale NoCs. 98:1-98:6 - Xuhang Wang, Zhuoran Song, Xiaoyao Liang:
InterArch: Video Transformer Acceleration via Inter-Feature Deduplication with Cube-based Dataflow. 99:1-99:6 - Weiwen Jiang, Youzuo Lin:
QuGeo: An End-to-end Quantum Learning Framework for Geoscience - A Case Study on Full-Waveform Inversion. 100:1-100:6 - Omar Ragheb, Jason Helge Anderson:
CLUMAP: Clustered Mapper for CGRAs with Predication. 101:1-101:6 - Renze Chen, Zijian Ding, Size Zheng, Meng Li, Yun Liang:
MoteNN: Memory Optimization via Fine-grained Scheduling for Deep Neural Networks on Tiny Devices. 102:1-102:6 - Christopher Talbot, Deepali Garg, Lawrence T. Pileggi, Kenneth Mai:
An IP-Agnostic Foundational Cell Array Offering Supply Chain Security. 103:1-103:6