default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDISCAS 2021: Daegu, South Korea
- IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021. IEEE 2021, ISBN 978-1-7281-9201-7
- Samalika Lakmali Perera, Ying Xu, André van Schaik
, Runchun Wang:
Live Demonstration: An FPGA-Based Emulation of an Event-Based Vision Sensor Using Commercially Available Camera. 1 - Rashid Ali, You Wang, Haoyuan Ma, Zhengyi Hou, Deming Zhang, Erya Deng, Weisheng Zhao:
A Reconfigurable Arbiter PUF Based on STT-MRAM. 1-5 - Syed Muhammad Abubakar, Yue Yin, Songyao Tan, Hanjun Jiang, Zhihua Wang, Seng-Pan U, Wen Jia:
A 2.52 μΑ Wearable Single Lead Ternary Neural Network Based Cardiac Arrhythmia Detection Processor. 1-4 - Taehak Kim, Jaehoon Jeong, Seungmin Woo, Jeonggyu Yang, Hyunwoo Kim, Ahyeon Nam, Changdong Lee, Jinmin Seo, Minji Kim, Siwon Ryu, Yoonju Oh, Taigon Song:
NS3K: A 3nm Nanosheet FET Library for VLSI Prediction in Advanced Nodes. 1-5 - Wenbin He, Fan Ye, Junyan Ren:
An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer. 1-4 - Shiying Wang, Ziyang Kang, Lei Wang, Shiming Li, Lianhua Qu:
A Hardware Aware Liquid State Machine Generation Framework. 1-5 - Carlos Salazar-García, Ronny García-Ramírez, Renato Rimolo-Donadio, Christos Strydis, Alfonso Chacón-Rodríguez:
PlasticNet+: Extending Multi-FPGA Interconnect Architecture via Gigabit Transceivers. 1-5 - Woorham Bae:
State-of-the-Art Circuit Techniques for Low-Jitter Phase-Locked Loops: Advanced Performance Benchmark FOM Based on an Extensive Survey. 1-5 - Mahmood A. Mohammed, Gordon W. Roberts:
Conventional CMOS OTAs Driving nF-Range Capacitive Loads. 1-5 - Ziying Ni, Dur-e-Shahwar Kundi, Máire O'Neill, Weiqiang Liu:
High-Performance Systolic Array Montgomery Multiplier for SIKE. 1-5 - Danyang Zhu, Jing Tian, Zhongfeng Wang:
Low-Latency Architecture for the Parallel Extended GCD Algorithm of Large Numbers. 1-5 - Debjyoti Bhattacharjee, Nathan Laubeuf, Stefan Cosemans, Ioannis A. Papistas, Arindam Mallik, Peter Debacker, Myung Hee Na, Diederik Verkest:
Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. 1-5 - Bo Zhang, Lei Zhang, Mojun Wu, Yan Wang:
Dynamic Gesture Recognition Based on RF Sensor and AE-LSTM Neural Network. 1-5 - Gabriel Nobert, Abdul Hafiz Alameh, Nam Ly, Nicolas G. Constantin, Yves Blaquière:
Towards an LTCC SiP for Control System in Safety-Critical Applications. 1-5 - Yuchen Li, Siming Zuo, Jacob Thompson, Lisa Ranford-Cartwright, Nosrat Mirzai, Hadi Heidari:
Magnetoresistance Sensor with Analog Frontend for Lab-on-Chip Malaria Parasite Detection. 1-5 - Ilias Bournias, Roselyne Chotin, Lionel Lacassagne:
FPGA Acceleration of the Horn and Schunck Hierarchical Algorithm. 1-5 - Chen Xu, Xiaolei Su, Zhengkun Shen, Dong Wang, Yi Tan, Zexue Liu, Hailong Jiao, Junhua Liu, Huailin Liao:
A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications. 1-5 - Markus Stadelmayer, Tim Schumacher, Thomas Faseth, Harald Pretl:
A Low-Power Edge-Combining Transmitter Using Quadrature Signals for FSK Modulation. 1-5 - Xingwu Ji, Zheng Gong, Ruihang Miao, Wuyang Xue, Rendong Ying:
Monocular Semantic Mapping Based on 3D Cuboids Tracking. 1-5 - Thang Xuan Pham, Hanho Lee:
High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule. 1-4 - Katsuki Tokano, Wenqi Zhu, Tatsuki Osato, Kien Nguyen, Hiroo Sekiya:
Optimal Design of 6.78 MHz Wireless Power Transfer System for Robot Arm. 1-5 - Hyeji Kim, Jaehoon Chung, Kyoung-Seon Shin, Chun-Gi Lyuh, Hyun-Mi Kim, Chan Kim, Yong Cheol Peter Cho, Jeongmin Yang, Je-Seok Ham, Minseok Choi, Jinho Han, Youngsu Kwon:
Live Demonstration: A Neural Processor for AI Acceleration. 1 - Devon Janke, David V. Anderson:
Best Practices for Designing and Training Neural Networks Subjected to Random Variations. 1-5 - Chae-Hyun Kim, Hyung-Min Lee:
A 2.45-GHz RF Energy Harvester with On-Chip 8-VCR SC Booster for IoT Devices. 1-5 - Fupeng Chen, Xinzhe Liu, Heng Yu, Yajun Ha:
CLIF: Cross-Layer Information Fusion for Stereo Matching and its Hardware Implementation. 1-5 - Chien-Chih Huang, Jyun-Neng Ji, Ming-Der Shieh:
On Compare-and-Swap Optimization for Fully Homomorphic Encrypted Data. 1-4 - Jialin Liu, David J. Allstot:
Compressed Sensing Σ-Δ Modulators and Recovery Algorithm for Multi-Channel Bio-Signal Acquisition. 1-4 - Corey Lammie, Wei Xiang, Mostafa Rahimi Azghadi:
Towards Memristive Deep Learning Systems for Real-Time Mobile Epileptic Seizure Prediction. 1-5 - Xiaofan Li, Melpomeni Kalofonou:
Predicting Cancer Drug Response Using an Adapted Deep Neural Network Model. 1-5 - Jayol Lee, Youngseok Baek, Iksoo Eo, Bontae Koo:
A Ka-Band FMCW PLL Synthesizer with 8.5-GHz Bandwidth for High-Precision High-Resolution Sub-mmWave Radar Sensing. 1-5 - Taiyu Zhu, Lei Kuang, Kezhi Li, Junming Zeng, Pau Herrero, Pantelis Georgiou:
Blood Glucose Prediction in Type 1 Diabetes Using Deep Learning on the Edge. 1-5 - Yunlu Wang, Menghan Hu, Chaohua Yang, Na Li, Jian Zhang, Qingli Li, Guangtao Zhai, Simon X. Yang:
Low-Cost and Unobtrusive Respiratory Condition Monitoring Based on Raspberry Pi and Recurrent Neural Network. 1-5 - Sangwoo Hwang, Junghyup Lee, Jaeha Kung:
Adaptive Input-to-Neuron Interlink Development in Training of Spike-Based Liquid State Machines. 1-5 - Bibhudutta Satapathy, Amandeep Kaur:
A High Speed, Low Energy Comparator Based on Current Recycling Approach. 1-5 - Shiyi Jin, Jin-Gyun Chung, Yinan Xu:
Signature-Based Intrusion Detection System (IDS) for In-Vehicle CAN Bus Network. 1-5 - Saddam Husain, Ahmad Khusro, Mohammad S. Hashmi, Galymzhan Nauryzbayev, Muhammad Akmal Chaudhary:
Demonstration of CAD Deployability for GPR Based Small-Signal Modelling of GaN HEMT. 1-5 - Min Chen, Yutong Zhao, Nuo Xu, Fan Ye, Junyan Ren:
A Partially Binarized and Fixed Neural Network Based Calibrator for SAR-Pipelined ADCs Achieving 95.0-dB SFDR. 1-4 - Shanzhe Yu, Xueyou Shi, Yacong Zhang, Guangyi Chen, Siyuan Ye, Wengao Lu, Zhongjian Chen:
A Readout Circuit with Current-Compensation-Based Extended-Counting ADC for 1024×768 Diode Uncooled Infrared Imagers. 1-5 - Haixian Wen, Junyuan Fang, Jiajing Wu, Zibin Zheng:
Transaction-Based Hidden Strategies against General Phishing Detection Framework on Ethereum. 1-5 - Aurélien Alacchi, Edouard Giacomin, Xifan Tang, Pierre-Emmanuel Gaillardon:
Smart-Redundancy: An Alternative SEU/SET Mitigation Method for FPGAs. 1-5 - Ramith Hettiarachchi, Udith Haputhanthri, Kithmini Herath, Hasindu Kariyawasam, Shehan Munasinghe, Kithmin Wickramasinghe, Duminda Samarasinghe, Anjula C. De Silva, Chamira U. S. Edussooriya:
A Novel Transfer Learning-Based Approach for Screening Pre-Existing Heart Diseases Using Synchronized ECG Signals and Heart Sounds. 1-5 - Inho Park, Jinseok Oh, Chulwoo Kim:
A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique. 1-4 - Hongchang Qiao, Chenchang Zhan, Quan Pan, Yutian Chen, Ning Zhang:
An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response. 1-4 - Tun-Yen Liao, Hsin-Shu Chen, Wen-Jong Wu:
Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques. 1-4 - Qiao Cai, Yuxin Ji, Ce Ma, Xiaocui Li, Ting Zhou, Jian Zhao, Yongfu Li:
An Ultra-Low-Voltage Energy-Efficient Dynamic Fully-Regenerative Latch-Based Level-Shifter Circuit with Tunnel-FET & FinFET Devices. 1-5 - Ckristian Duran, Elkim Roa:
Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability. 1-5 - Chua-Chin Wang, Chien-Ping Kuo:
67.5-fJ Per Access 1-kb SRAM Using 40-nm Logic CMOS Process. 1-4 - Khoirom Johnson Singh, Anand Bulusu, Sudeb Dasgupta:
Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack. 1-5 - Daohuai Jiang, Hengrong Lan, Yifei Xu, Yujie Wang, Feng Gao, Fei Gao:
Size-Adjustable Photoacoustic Tomography System with Sectorial Ultrasonic Transducer Array. 1-5 - Masahiro Kawano, Tran Thi Thao Nguyen, Yuhei Nagao, Leonardo Lanante, Masayuki Kurosaki, Hiroshi Ochi:
Live Demonstration: Null Beamforming to Self in Cooperative MIMO for Full-Duplex System. 1 - Milad Zamani, Margherita Ronchini, Hai Au Huynh, Hooman Farkhani, Farshad Moradi:
Flexible Energy-Efficient Implementation of Adaptive Spiking Encoder for Neuromorphic Processors. 1-5 - Sunwha Koh, Younggwang Jung, Daijoon Hyun, Youngsoo Shin:
Routability Optimization for Extreme Aspect Ratio Design Using Convolutional Neural Network. 1-4 - Arshad Khan, Shawkat Ali, Saleem Khan, Amine Bermak:
Rapid Fabrication of Soft Strain Sensors by Multi-Nozzle Electrohydrodynamic Inkjet Printing for Wearable Electronics. 1-4 - Md Toufikul Islam, Semih Aslan:
Leak Detection and Location Pinpointing in Water Pipeline Systems Using a Wireless Sensor Network. 1-7 - Laysson Oliveira Luz, José Augusto Miranda Nacif, Ricardo S. Ferreira, Omar P. Vilela Neto:
NMLib: A Nanomagnetic Logic Standard Cell Library. 1-5 - Peta Guruprakashkumar, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Edoardo Bonizzoni:
A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. 1-5 - Jialiang Tang, Mingjin Liu, Ning Jiang, Huan Cai, Wenxin Yu, Jinjia Zhou:
Data-Free Network Pruning for Model Compression. 1-5 - B. Dinesh Kumar, Hitesh Shrimali, Nagarjuna Nallam:
A Low-Power Quadrature LC-Oscillator Using Core-and-Coupling Current-Reuse. 1-5 - Mohammad Usaid Abbasi:
A Wearable EEG Amplifier Using a Novel Teraohm Low-Distortion Tunable Hybrid Pseudo-Resistor. 1-5 - Jaewon Lee, Gain Kim, Jinho Park, Hyeon-Min Bae:
Link Bit-Error-Rate Requirement Analysis for Deep Neural Network Accelerators. 1-5 - Xiaobai Chen, Weibei Fan, Yong Xie, Fu Xiao:
A 2.44 Tops/W Heterogeneous DCNN Inference/Training Processor for Embedded System. 1-5 - Jongkil Hyun, Junghwan Kim, Cheol-Ho Choi, Byungin Moon:
Hardware Architecture of a Haar Classifier Based Face Detection System Using a Skip Scheme. 1-4 - Hanrui Zhang, Nannan Li, Zihao Jiao, Jie Zhang, Xiaofei Wang, Hong Zhang:
A 1st-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration. 1-5 - Rameesha Qaiser, Muhammad Rizwan Khan, Wala Saadeh:
An Impedance Measurement SoC with Highly Digital Magnitude and Phase-to-Digital Converter. 1-5 - Jie Chen, Xiang Li:
A Minimal Memory Game-Based Distributed Algorithm to Vertex Cover of Networks. 1-5 - Hing-Mo Lam, Silin Lu, Hezi Qiu, Hailong Jiao, Min Zhang, Shengdong Zhang:
Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder. 1-5 - Si Wang, Chip-Hong Chang:
Fingerprinting Deep Neural Networks - a DeepFool Approach. 1-5 - Zhanyuan Cai, Wei Gao:
Efficient Fast Algorithm and Parallel Hardware Architecture for Intra Prediction of AVS3. 1-5 - Richelle L. Smith, Thomas H. Lee:
Modeling of Injection Locking in Neurons for Neuromorphic and Biomedical Systems. 1-5 - Jiaqi Wang, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis:
Accounting for Memristor I-V Non-Linearity in Low Power Memristive Amplifiers. 1-5 - Ibrahim M. Elfadel:
Convergent Time-Stepping Schemes for Analog ReLU Networks. 1-5 - Ming Yang, Shayan Shahramian, Henry Wong, Peter Krotnev, Anthony Chan Carusone:
Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. 1-5 - Huiping Zhuang, Zhiping Lin, Kar-Ann Toh:
Training Multilayer Neural Networks Analytically Using Kernel Projection. 1-5 - Kohji Hosokawa, Pritish Narayanan, Stefano Ambrogio, Hsinyu Tsai, Charles Mackin, Andrea Fasoli, Alexander M. Friz, An Chen, Jose Luquin, Katherine Spoon, Geoffrey W. Burr, Scott C. Lewis:
Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited). 1-5 - Ahmad Reza Danesh, Payam Heydari:
A Comprehensive Analysis of Charge-Pump-Based Multi-Stage Multi-Output DC-DC Converters. 1-5 - Oscal Tzyh-Chiang Chen, Yu Cheng Zhang, Yu-Xuan Chang, Yu-Lung Chang:
Iterative Multiple-Path One-Shot NAS for the Optimized Performance. 1-5 - Balaji Vijayakumar, Janakiraman Viraraghavan:
An Area-Efficient Word-Line Pitch-Aligned 8T SRAM Compatible Digital-to-Analog Converter. 1-5 - N. Watanabe, M. Ikeda:
ToF Image Sensor with Pulse-Frequency-Modulation Pixel for In-Pixel Code Discrimination. 1-5 - Yubo Shi, Meiqi Wang, Siyi Chen, Jinghe Wei, Zhongfeng Wang:
Transform-Based Feature Map Compression for CNN Inference. 1-5 - Markus Robens, Christian Grewing, Michael Schiek, Stefan van Waasen:
Effective Low-Pass Filter Function Due to the Use of a Comb Filter and Virtual Oversampling. 1-5 - Yue Zheng, Chip-Hong Chang:
Secure Mutual Authentication and Key-Exchange Protocol between PUF-Embedded IoT Endpoints. 1-5 - Xuesong Chen, Hazem Elgabra, Chih-Hung Chen, Jonathan Baugh, Lan Wei:
Estimation of MOSFET Channel Noise and Noise Performance of CMOS LNAs at Cryogenic Temperatures. 1-5 - Mounika Akula, Ajinkya Kale, Johannes Sturm:
A Double-Balanced N-Phase Passive 3 × Sub-Harmonic Down-Conversion Mixer. 1-5 - Matthias Eberlein, Harald Pretl:
A Current-Mode Temperature Sensor with a ±1.56 °C Raw Error and Duty-Cycle Output in 16nm FinFET. 1-5 - Ria Rashid, Nandakumar Nambath:
Hybrid Particle Swarm Optimization Algorithm for Area Minimization in 65 nm Technology. 1-5 - Sayed Elgendy, Eslam Yahya Tawfik:
Impact of Physical Design on PUF Behavior: A Statistical Study. 1-5 - Ujjawal Chugh, Arnab Mitra, Ankur Deshwal, N. P. Swaroop, Aditi Saluja, Seungwon Lee, Joonho Song:
An Automated Approach to Accelerate DNNs on Edge Devices. 1-5 - Sachin Maheshwari, Alexander Serb, Christos Papavassiliou, Themistoklis Prodromakis:
An Adiabatic Regenerative Capacitive Artificial Neuron. 1-5 - Ayush Jain, Ziqi Zhou, Ujjwal Guin:
Survey of Recent Developments for Hardware Trojan Detection. 1-5 - Tianyuan Tang, Ping Luo, Chengda Deng, Bo Zhang:
A Novel Ladder Control Assisted Startup for Primary Side Regulated Flyback Converter. 1-4 - Chuhui Wang, Yanhang Chen, Shaochen Xi, Jianping Guo, Junrui Liang:
An Integrated Piezoelectric Energy Harvesting Interface Circuit with Adaptive S3BF Control. 1-4 - Van Ha Nguyen, Abdul Hafiz Alameh, Nam Ly, Yves Blaquière, Glenn E. R. Cowan:
A Novel Minimum-Phase Dual-Inductor Hybrid Boost Converter with PWM Voltage-Mode Controller. 1-5 - Yajun Mao, Qian Zhao, Rongxuan Song, Zhihai Rong, Jiasheng Hao:
Timescales Diversity Induces Influencers to Persist Cooperation on Scale-Free Networks. 1-5 - Mandana Ardeshir Tanha, Farnaz Fahimi Hanzaee, Richard H. Bayford, Andreas Demosthenous:
RF Wireless Power Transfer for EIT Neonate Lung Function Monitoring. 1-5 - Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini:
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. 1-5 - Chao Wang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao:
Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes. 1-5 - Michael Canesche, Lucas Bragança, Omar Paranaiba Vilela Neto, José Augusto Miranda Nacif, Ricardo S. Ferreira:
Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design. 1-5 - Jordi Bonet-Dalmau, Pere Palà-Schönwälder, F. Xavier Moncunill-Geniz:
SNR Measurement of Superregenerative Oscillators. 1-5 - Cesar G. Chaves, Johanna Sepúlveda, Thomas Hollstein:
Lightweight Monitoring Scheme for Flooding DoS Attack Detection in Multi-Tenant MPSoCs. 1-5 - Miguel de Prado, Manuele Rusci, Romain Donze, Alessandro Capotondi, Serge Monnerat, Luca Benini, Nuria Pazos:
Robustifying the Deployment of tinyML Models for Autonomous Mini-Vehicles. 1-5 - Zhuoran Song, Dongyue Li, Zhezhi He, Xiaoyao Liang, Li Jiang:
ReRAM-Sharing: Fine-Grained Weight Sharing for ReRAM-Based Deep Neural Network Accelerator. 1-5 - Khaled Humood, Baker Mohammad, Heba Abunahla:
DTRNG: Low Cost and Robust True Random Number Generator Using DRAM Weak Write Scheme. 1-5 - Kai Sheng, Linqi Shi, Weixin Gai, Qianting Hua, Peng Lin:
A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET. 1-5 - Cameron James Norris, Sunwoong Kim:
An Approximate and Iterative Posit Multiplier Architecture for FPGAs. 1-5 - C. Mohan, Luis A. Camuñas-Mesa, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
Implementation of Binary Stochastic STDP Learning Using Chalcogenide-Based Memristive Devices. 1-5 - Coen Arrow, Hancong Wu, Seungbum Baek, Herbert H. C. Iu, Kianoush Nazarpour, Jason Kamran Eshraghian:
Prosthesis Control Using Spike Rate Coding in the Retina Photoreceptor Cells. 1-5 - Satoshi Shioiri, Yoshiyuki Sato, Yuta Horaguchi, Hiroaki Muraoka, Mariko Nihei:
Quali-Informatics in the Society with Yotta Scale Data. 1-4 - Bojun Hu, Chao Liu, Sanfeng Zhang, Qiang Li:
A Ku-Band SiGe Phased-Array Transceiver with 6-Bit Phase and Attenuation Control. 1-5 - Chao Zhang, Jingtong Mo, Zihan Lian, Weifeng He:
High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory. 1-4 - Zhenghui Zhao, Chuanmin Jia, Shanshe Wang, Siwei Ma, Jiansheng Yang:
Learned Image Compression Using Adaptive Block-Wise Encoding and Reconstruction Network. 1-5 - Binghui Wang, Haigang Yang, Yiping Jia:
A 3-6GHz 5-to-512 Multiplier Adaptive Fast-Locking Self-Biased PLL in 28nm CMOS. 1-5 - Tolulope A. Odetola, Syed Rafay Hasan:
SoWaF: Shuffling of Weights and Feature Maps: A Novel Hardware Intrinsic Attack (HIA) on Convolutional Neural Network (CNN). 1-5 - Yadong Yin, Kamal El-Sankary, Zhizhang Chen, Ximing Fu:
A Type-II Analog PLL with Time-Domain Processing. 1-5 - Maria D. Vieira, Michael Canesche, Lucas Bragança, Josué Campos, Mateus Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays. 1-5 - Farzin Ghorban, Nesreen Hasan, Jörg Velten, Anton Kummert:
Improving FM-GAN through Mixup Manifold Regularization. 1-5 - Cong Zhang, Dongsheng Liu, Xingjie Liu, Xuecheng Zou, Guangda Niu, Bo Liu, Quming Jiang:
Towards Efficient Hardware Implementation of NTT for Kyber on FPGAs. 1-5 - Jieyu Li, Zihan Lian, Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process. 1-5 - Zhechong Lan, Li Dong, Xixin Jing, Li Geng:
A 12-Bit 100MS/s SAR ADC with Digital Error Correction and High-Speed LMS-Based Background Calibration. 1-5 - Malik Summair Asghar, Saad Arslan, HyungWon Kim:
Current Multiplier Based Synapse and Neuron Circuits for Compact SNN Chip. 1-4 - Yonghwi Kwon, Giyoon Jung, Daijoon Hyun, Youngsoo Shin:
Dynamic IR Drop Prediction Using Image-to-Image Translation Neural Network. 1-5 - Wenqing Song, Yifei Shen, Yuxiang Fu, Chuan Zhang, Li Li:
Adaptive Successive Cancellation Priority Decoder for 5G Polar Codes. 1-5 - Carmine Paolino, Alessio Antolini, Fabio Pareschi, Mauro Mangia, Riccardo Rovatti, Eleonora Franchi Scarselli, Antonio Gnudi, Gianluca Setti, Roberto Canegallo, Marcella Carissimi, Marco Pasotti:
Compressed Sensing by Phase Change Memories: Coping with Encoder non-Linearities. 1-5 - Yifeng Song, Xiao Hu, Wenhao Wang, Jing Tian, Zhongfeng Wang:
High-Speed and Scalable FPGA Implementation of the Key Generation for the Leighton-Micali Signature Protocol. 1-5 - Yixuan Zeng, Heming Sun, Jiro Katto, Yibo Fan:
Approximated Reconfigurable Transform Architecture for VVC. 1-5 - Hongyu Wang, Shengyu Gao, Teng Wang, Yang Wang, Xin Lou:
Multi-Scale Slanted O(1) Stereo Matching Algorithm. 1-5 - Dimple Kochar, Animesh Kumar:
Estimation of Time to Failure Distribution in SRAM Due to Trapped Oxide Charges. 1-5 - Hong-Han Lien, Chung-Wei Hsu, Tian-Sheuan Chang:
VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator. 1-5 - Kai Cui, Ahmet Burakhan Koyuncu, Atanas Boev, Elena Alshina, Eckehard G. Steinbach:
Quality-Blind Compressed Color Image Enhancement with Convolutional Neural Networks. 1-5 - Erya Deng, Wang Kang, Weisheng Zhao, Shaoqian Wei, You Wang, Deming Zhang:
Spin-Orbit Torque Nonvolatile Flip-Flop Designs. 1-5 - Yanshu Guo, Yaoyu Li, Hanjun Jiang, Xiaofeng Yang, Zhihua Wang:
A 110pJ/Bit Star- 16QAM 915MHz Band Ultra-Low Power Receiver Based on Polar Architecture. 1-4 - Maoshen Zhang, Qiang Liu:
A Digital and Lightweight Delay-Based Detector against Fault Injection Attacks. 1-5 - Cheolyong Bae, Oscar Gustafsson:
Overlap-Save Commutators for High-Speed Streaming Data Filtering. 1-5 - Zhao Yang, Qingshuang Sun:
Efficient Resource-Aware Neural Architecture Search with Dynamic Adaptive Network Sampling. 1-5 - Antik Mallick, Mohammad Khairul Bashar, Daniel S. Truesdell, Benton H. Calhoun, Siddharth Joshi, Nikhil Shukla:
Graph Coloring Using Coupled Oscillator-Based Dynamical Systems. 1-5 - Useok Lee, Jae Hong Roh, Chan Hwangbo, Myung Hoon Sunwoo:
A Uniformly Segmented SC-Flip Decoder for Polar Codes with Memory Reduction Methods. 1-5 - Kaiquan Chen, Ce Ma, Qing Zhang, Yongfu Li, Jian Zhao, Mingyi Chen:
FreePDK15TFET: An Open-Source Process Design Kit for 15nm CMOS and TFET devices. 1-5 - Junjie Gu, Guixiang Jin, Hongtao Xu, Hao Min, Na Yan:
A Two-Way Power-Combining 60GHz CMOS Power Amplifier with 22.0% PAE and 19.4dBm Psat in 65nm Bulk CMOS. 1-4 - Yi Sheng Chong, Wang Ling Goh, Yew Soon Ong, Vishnu P. Nambiar, Anh Tuan Do:
An Energy-Efficient Convolution Unit for Depthwise Separable Convolutional Neural Networks. 1-5 - Yuanfei Huang, Akshay Athalye, Samir R. Das, Petar M. Djuric, Milutin Stanacevic:
RF Energy Harvesting and Management for Near-Zero Power Passive Devices. 1-5 - Yi Zhong, Xiaoxin Cui, Yisong Kuang, Kefei Liu, Yuan Wang, Ru Huang:
A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. 1-5 - Yisong Kuang, Xiaoxin Cui, Yi Zhong, Kefei Liu, Chenglong Zou, Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang:
A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. 1-5 - Satyabrata Sarangi, Bevan M. Baas:
DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era. 1-5 - Hachem Bensalem, Yves Blaquière, Yvon Savaria:
Acceleration of the Secure Hash Algorithm-256 (SHA-256) on an FPGA-CPU Cluster Using OpenCL. 1-5 - Che-Wei Hsu, Soon-Jyh Chang:
A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration. 1-5 - Marcio Monteiro, Pedro Aquino Silva, Ismael Seidel, Mateus Grellert, Leonardo Bandeira Soares, José Luís Güntzel, Cristina Meinhardt:
Design of Energy-Efficient Gaussian Filters by Combining Refactoring and Approximate Adders. 1-5 - Lulin Cai, Yiduan Qian, Yajuan He, Wen Feng:
Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing. 1-4 - Felipe Barboza da Silva, Ediz Cetin, Wallace Alves Martins:
ADS-B Signal Detection via Time-Frequency Analysis for Radio Astronomy Applications. 1-4 - Dan Cracan, Mihai Sanduleanu, Mizan Abraha Gebremicheal:
A 0.7-1.5GHz Tunable Papoulis All-Pole Low-Pass Filter in 22nm CMOS FDSOI. 1-5 - Mamoru Fukuchi, Shun Suzuki, Kyosuke Maeda, Chihiro Matsui, Ken Takeuchi:
BER Evaluation System Considering Device Characteristics of TLC and QLC NAND Flash Memories in Hybrid SSDs with Real Storage Workloads. 1-4 - Pranshu Kalra, Devraj Rajagopal, Sumantra Seth, Anshul Sirohi:
Multi Voltage High Performance Bidirectional Buffer in a Low Voltage CMOS process. 1-5 - Jiangli Huang, Shuhan Zhang, Cong Tao, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process. 1-5 - Zhiyong Li, Dongseok Im, Jinsu Lee, Hoi-Jun Yoo:
A 3.6 TOPS/W Hybrid FP-FXP Deep Learning Processor with Outlier Compensation for Image-to-Image Application. 1-5 - Daniel Junehee Lee, Fei Yuan, Yushi Zhou:
All-Digital Successive Approximation TDC in Time-Mode Signal Processing. 1-4 - Zixiang Wan, Woogeun Rhee, Zhihua Wang:
Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops. 1-4 - Zijian Tang, Chao Zhang, Yahao Song, Milin Zhang:
Design of a Seizure Detector Using Single Channel EEG Signal. 1-4 - Wenwen Liu, Gang Wang, Qinghao Lin, Haibo Liu, Jingwei Shi, Min Lin:
An RS (255, 239) Decoder with e-PIBM Algorithm, 25.6Gb/s Throughput and 623 TSNT FoM Value Using Fractional Folding Technique in 40nm Technology. 1-5 - Philipp Thomas, Markus Grözing, Manfred Berroth:
64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology. 1-4 - Parikha Mehrotra, Baibhab Chatterjee, Shovan Maity, Shreyas Sen:
Design Considerations for a Sub-25μW PLL with Multi-Phase Output and 1-450MHz Tuning Range. 1-5 - Hao Zhang, Seok-Bum Ko:
Efficient Multiple-Precision Posit Multiplier. 1-5 - Renzo Andri, Geethan Karunaratne, Lukas Cavigelli, Luca Benini:
ChewBaccaNN: A Flexible 223 TOPS/W BNN Accelerator. 1-5 - Dinda Pramanta, Hakaru Tamukoh:
FPGA Implementation of Pulse-Coupled Phase Oscillators working as a Reservoir at the Edge of Chaos. 1-5 - Matteo Baire, Andrea Melis, Matteo Bruno Lodi, Luca Lodi, Alessandro Fanti, Giuseppe Mazzarella:
Empowering Traditional Carasau Bread Production Using Wireless Sensor Network. 1-4 - Yiyang Chen, Daryl Ma, Pantelis Georgiou:
A Wireless Power Management Unit with a Novel Self-Tuned LDO for System-On-Chip Sensors. 1-5 - Jinkai Zheng, Xinchen Liu, Chenggang Yan, Jiyong Zhang, Wu Liu, Xiaoping Zhang, Tao Mei:
TraND: Transferable Neighborhood Discovery for Unsupervised Cross-Domain Gait Recognition. 1-5 - Dong Yanchi, Weixin Gai, Xiao Xiang, Haowei Niu:
A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer. 1-5 - Dai Jiang, Yu Wu, Noora Almarri, Maryam Habibollahi, Fangqi Liu, J. Barney Bryson, Linda Greensmith, Andreas Demosthenous:
An Integrated Bidirectional Multi-Channel Opto-Electro Arbitrary Waveform Stimulator for Treating Motor Neurone Disease. 1-4 - Yiying Zhang, Baoxian Zhou, Xi Chen, Jing Shang:
An Intelligent Recommendation Method for Power Big Data Based on Knowledge Graph. 1-5 - Nan-Hsiung Tseng, Bo-Kuan Wu, Tzu-Ping Huang, Cheng-Yen Lee, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A Series Stacked FinFET Structure for Digital Low Dropout Regulators with Minimum Energy Point Technique for 37.5% Energy Reduction in Cortex M0 Processor. 1-4 - Al-Hussein A. El-Shafie, Mohamed H. Zaki, Serag El-Din Habib:
Towards an Efficient Hardware Implementation of CNN-Based Object Trackers. 1-5 - Robson Domanski, William Kolodziejski, Guilherme Corrêa, Marcelo Schiavon Porto, Bruno Zatt, Luciano Agostini:
Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation. 1-5 - Yu-Chen Cheng, Hsiao-Chin Chen:
CMOS LNA for DTV-Band Cognitive Radio Applications. 1-5 - Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui:
Low-Power Memristor-Based Computing for Edge-AI Applications. 1-5 - Markus Haberler, Christoph Steffan, Inge Siegl, Norbert Sailer, Mario Auer:
A 92-dB-DR 126-μν Sensitivity Potentiometrie Sensor Interface with High Interference Robustness. 1-5 - Xin Zhang, Chunqi Shi, Runxi Zhang, Hao Deng, Jinghong Chen:
A 64-84 GHz CMOS LNA with Excellent Gain Flatness for Wideband mmW Applications. 1-5 - Valentina Baruzzi, Matteo Lodi, Alberto Oliveri, Marco Storace:
Analysis and Improvement of an Algorithm for the Online Inertia Estimation in Power Grids with RES. 1-5 - Seiji Uenohara, Kazuyuki Aihara:
CMOS Mixed-Signal Spiking Neural Network Circuit Using a Time-Domain Digital-To-Analog Converter. 1-5 - Tsung-Han Tsai, Shih-An Huang:
Live Demonstration: Real-Time Multi-Hand Segmentation on Exhibition. 1 - Xinsheng Wang, Tian Tian, Jihua Zhu, Odette Scharenborg:
Learning Fine-Grained Semantics in Spoken Language Using Visual Grounding. 1-5 - Zhaohong Wang, Sen-Ching S. Cheung:
Privacy-Protected Denoising for Signals on Graphs from Distributed Systems. 1-5 - Peng Cao, Zhiliang Hong:
A Bipolar-Input Bipolar-Output DC-DC Converter for Thermoelectric Energy Harvesting. 1-4 - Ching-Hwa Cheng, Ching-Kun Chao, Kai-Chun Yeh, Don-Gey Liu, Sheng-Di Lin:
The Performance-Complexity Efficient Time-to-Digit and Data-Processing Chips Design and Validation for a LiDAR System. 1-4 - Yuquan Dai, Kemeng Li, Jin Chai, Zhuoling Xiao, Bo Yan, Yi He, Wenyu Peng:
Radar Update (RUPT): A Pedestrian Navigation System with Enhanced Trajectory Performance. 1-5 - Matías R. Miguez, Jessica Flebbe, Helen Vogel, Alfredo Arnaud, Ignacio Benavente:
A Prototype of a Pulsed Electric Fields Treatment for Solid Foods in Batches. 1-4 - Hood Khizer, Wahaj Ahmad, Tayyba Naz, Hasan Sajid:
Vol-Net and V3C-Net: Towards End to End Traffic Volume Estimation. 1-5 - Narasinga Rao Miniskar, Frank Liu, Jeffrey S. Vetter:
A Memory Efficient Lock-Free Circular Queue. 1-5 - Xin Li, Christian Vogel, Jianhui Wu:
Two-Stage Difference-Based Estimation Method for Timing Skew in TI-ADCs. 1-4 - Netanel Shavit, Inbal Stanger, Ramiro Taco, Marco Lanuzza, Alexander Fish:
Live Demonstration: A 0.8V, 1.54 pJ / 940 MHz Dual Mode Logic-Based 16x16-Bit Booth Multiplier in 16-nm FinFET. 1 - Umberto Garlando, Lee Bar-On, Paolo Motto Ros, Alessandro Sanginario, Stefano Calvo, Maurizio Martina, Adi Avni, Yosi Shacham-Diamand, Danilo Demarchi:
Analysis of in Vivo Plant Stem Impedance Variations in Relation with External Conditions Daily Cycle. 1-5 - Jiachen Shen, Yi Zhang, Liu Yang, Lin He, Yufeng Guo, Hao Gao:
Wideband Digitally Controlled True Time Delay for Beamforming in a 40 nm CMOS Technology. 1-4 - Jinzhao Han, Miguel Cacho-Soblechero, Matthew Douthwaite, Pantelis Georgiou:
A Digital ISFET Sensor with In-Pixel ADC. 1-5 - Vita Pi-Ho Hu, Cheng-Wei Su, Chun-Chi Yu, Chang-Ju Liu, Cheng-Yang Weng:
Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node. 1-5 - Jonah P. Sengupta, Martin Villemur, Daniel R. Mendat, Gaspar Tognetti, Andreas G. Andreou:
Architecture and Algorithm Co-Design Framework for Embedded Processors in Event-Based Cameras. 1-5 - Youze Xin, Bing Zhang, Congzhen Hu, Li Dong, Dan Li, Yunsong Wang, Lijun Zhang, Shuyu Lei, Li Geng:
A 320×240 I-ToF CMOS Image Sensor with 2-Tap 5.6µm Pixel and Mismatch-Nonlinearity Suppression. 1-4 - Nan Ren, Zaiming Fu, Dandan Zhou, Dexuan Kong, Shulin Tian:
PointNet-Based Jitter Decomposition on Point Cloud of Jitter Histogram. 1-5 - András Fülöp, András Horváth:
Application of Cellular Neural Networks in Semantic Segmentation. 1-5 - Siriporn Dokthurian, Wirat Rattanapitak, Somkiat Wangsiripitak:
Human Height Estimation Using Visual Geometry and Feature Learning. 1-5 - Daiki Kojima, Ken Takeuchi:
Error Suppression of Last-Programmed Word-Line for Real Usage of 3D-NAND Flash Memory. 1-4 - Jiang Jiang, Hui-Liang Shen, Yongxiang Xia, Herbert H. C. Iu:
Optimal Coupling Pattern of Cyber-Physical Systems. 1-5 - Kan Yao, Dur-e-Shahwar Kundi, Chenghua Wang, Máire O'Neill, Weiqiang Liu:
Towards CRYSTALS-Kyber: A M-LWE Cryptoprocessor with Area-Time Trade-Off. 1-5 - Abhijitt Dhavlle, Rakibul Hassan, Manideep Mittapalli, Sai Manoj Pudukotai Dinakarrao:
Design of Hardware Trojans and its Impact on CPS Systems: A Comprehensive Survey. 1-5 - Winnie Thomas, Suryakant Toraskar, Virendra Singh:
Dynamic Optimizations in GPU Using Roofline Model. 1-5 - Zhijian Liang, Jie Yuan:
An Event-Driven Multi-Input Multi-Output BuckBoost Converter with Adaptive MPPT for Wide Power Range RF Energy Harvesting. 1-5 - Sangmin Shin, Minsung Kim, Junyoung Park, Hyunjoong Lee, Suhwan Kim:
Energy-Efficient Read-Out IC for High-Precision DC Measurement System with Instrumentation Amplifier Power Reduction Technique. 1-5 - Xueyou Shi, Shanzhe Yu, Guangyi Chen, Yacong Zhang, Zhongjian Chen, Wengao Lu:
A Low Noise 384×288 Uncooled Infrared Imager Based on Phase Difference Modulation. 1-5 - Youngchang Choi, Sunmean Kim, Kyongsu Lee, Seokhyeong Kang:
Design and Analysis of a Low-Power Ternary SRAM. 1-4 - Teo Boon Chiat Terence, Venkadasamy Navaneethan, Lim Xian Yang, Nardi Utomo, Ziming Liu, Tan Chong Boon, Seah Yun Da Bryan, Ji-Jon Sit, Liter Siek:
A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application. 1-5 - Seyed Ahmad Mirsalari, Najmeh Nazari, Seyed Ali Ansarmohammadi, Sima Sinaei, Mostafa E. Salehi, Masoud Daneshtalab:
ELC-ECG: Efficient LSTM Cell for ECG Classification Based on Quantized Architecture. 1-5 - Fatima Tuz Zohora, Vedant Karia, Anurag Reddy Daram, Abdullah M. Zyarah, Dhireesha Kudithipudi:
MetaplasticNet: Architecture with Probabilistic Metaplastic Synapses for Continual Learning. 1-5 - Yigi Kwon, Byounghan Min, Jinhwan Lee, Wooyol Lee, Sunghyun Yang:
An 8.1 ENOB 10bit 400MS/s Pipelined ADC Using SAR and Sub-Ranging Flash. 1-5 - Zhengqi Xu, Ke Wu, Xiaoming Liu, Chengyuan Liu, Jing Jin, Jianjun Zhou:
A Ka-Band Quadrature-Hybrid LNA-PS with Gm- Boosting Technique in 40-nm CMOS. 1-5 - Rajeev Kumar Pandey, Paul C.-P. Chao:
An Adaptive Analog Front End for a Flexible PPG Sensor Patch with Self-Determined Motion Related DC Drift Removal. 1-5 - Divy Pandey, Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Dip Sankar Banerjee:
SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications. 1-5 - Tun Li, Hongji Zou, Dan Luo, WanXia Qu:
Symbolic Simulation Enhanced Coverage-Directed Fuzz Testing of RTL Design. 1-5 - Ryan Billmeyer, Minghui Lu, Brian B. Johnson, Sairaj V. Dhople:
Modeling and Simulation of Power-Electronic Inverters in Analog Electronic Circuit Simulators. 1-5 - Jooyoon Kim, Yunho Jang, Taehwan Kim, Jongsun Park:
Low Energy Domain Wall Memory Based Convolution Neural Network Design with Optimizing MAC Architecture. 1-4 - Leandro Passetti, Benjamín T. Reyes, Damián A. Morero, Mario R. Hueda:
Reduced Complexity Backpropagation-Based Adaptive Compensation of Frequency Interleaved ADC for Digital Communication Receivers. 1-5 - Fariborz Lohrabi Pour, Dong Sam Ha:
A Temperature Compensated Variable Gain Phase Shifter Based on GaN HEMTs. 1-5 - Reza Hashemian:
Application of Nullors in Symbolic Single Port Transfer Functions Using Admittance Method. 1-5 - Frowin Buballa, Sebastian Linnhoff, Michael Reinhold, Friedel Gerfers:
A 12 Bit 500 MS/s Sub-2 Radix SAR ADC for a Time-Interleaved 8 GS/s ADC in 28 nm CMOS. 1-5 - Lin Li, Yici Cai, Qiang Zhou:
An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. 1-5 - Anil Korkmaz, Chaoyi He, Linda P. B. Katehi, R. Stanley Williams, Samuel Palermo:
Design of Tunable Analog Filters Using Memristive Crossbars. 1-5 - Shaofeng Zou, Jiawei Lin, Xuyang Wang, Guolin Li, Zhihua Wang, Xiang Xie:
An Object Enhancement Method for Forward-Looking Sonar Images Based on Multi-Frame Fusion. 1-5 - Zongyu Guo, Jun Fu, Runsen Feng, Zhibo Chen:
Accelerate Neural Image Compression with Channel-Adaptive Arithmetic Coding. 1-5 - Naoya Onizawa, Takahiro Hanyu:
High Convergence Rates of CMOS Invertible Logic Circuits Based on Many-Body Hamiltonians. 1-5 - Lei Zhang, David Borggreve, Frank Vanselow, Ralf Brederlow:
Impact of Parasitic Wire Resistance on Accuracy and Size of Resistive Crossbars. 1-5 - Ahmet Samil Demirkol, Alon Ascoli, Ioannis Messaris, Ronald Tetzlaff:
Analytical Investigation of Pattern Formation in an M-CNN with Locally Active NbOx Memristors. 1-5 - Yuan Liang, Chirn Chye Boon, Qian Chen, Yangtao Dong:
Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer. 1-5 - Matteo Risso, Alessio Burrello, Daniele Jahier Pagliari, Simone Benatti, Enrico Macii, Luca Benini, Massimo Poncino:
Robust and Energy-Efficient PPG-Based Heart-Rate Monitoring. 1-5 - Ryohei Nakayama, Makoto Ikeda:
BN-254 Based Multi-Core, Multi-Pairing Crypto-Processor for Functional Encryption. 1-5 - Mert Koç, Salar Chamanian, Halil Andaç Yigit, Hasan Ulusan, Haluk Külah:
An Adaptive Converter for Current Neural Stimulators Achieving up to 79% Power Dissipation Reduction. 1-4 - Wei Zhou, Zhibo Chen:
Deep Multi-Scale Features Learning for Distorted Image Quality Assessment. 1-5 - Yuqi Zhu, Shengze Li, Jieyuan Zhang, Xinhai Xu:
Combined Reinforcement Learning via Artificial Potential Field: A Case Study in Pommerman. 1-5 - Yixuan Zeng, Heming Sun, Jiro Katto, Yibo Fan:
Accelerating Convolutional Neural Network Inference Based on a Reconfigurable Sliced Systolic Array. 1-5 - Rupam Das, Eve McGlynn, Mengyao Yuan, Hadi Heidari:
Serpentine-Shaped Metamaterial Energy Harvester for Wearable and Implantable Medical Systems. 1-5 - Xiaoguang Zhu, Siran Huang, Wenjing Fan, Yuhao Cheng, Huaqing Shao, Peilin Liu:
SDAN: Stacked Diverse Attention Network for Video Action Recognition. 1-5 - Abdolreza Sabzi Shahrebabaki, Sabato Marco Siniscalchi, Giampiero Salvi, Torbjørn Svendsen:
A DNN Based Speech Enhancement Approach to Noise Robust Acoustic-to-Articulatory Inversion. 1-5 - Kurea Murakami, Minoru Watanabe:
Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs. 1-5 - Yunzhou Cheng, Xinyi Li, Guoqiang Xiao, Wenzhuo Ma, Xinye Gou:
Dual-Path Deep Supervision Network with Self-Attention for Visible-Infrared Person Re-Identification. 1-5 - Bradley McDanel, Sai Qian Zhang, H. T. Kung:
Saturation RRAM Leveraging Bit-Level Sparsity Resulting from Term Quantization. 1-5 - Deming Zhang, Xian Wang, Kaili Zhang, Lang Zeng, You Wang, Bi Wang, Erya Deng, Chuanjie Wang, Peng Wu, Youguang Zhang, Weisheng Zhao:
Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory. 1-5 - Clemens J. S. Schaefer, Mark Horeni, Pooria Taheri, Siddharth Joshi:
LSTMs for Keyword Spotting with ReRAM-Based Compute-In-Memory Architectures. 1-5 - Yihan Pan, Patrick Foster, Alexander Serb, Themis Prodromakis:
A RRAM-Based Associative Memory Cell. 1-5 - M. Meraj Ahmed, Abhijitt Dhavlle, Naseef Mansoor, Sai Manoj Pudukotai Dinakarrao, Kanad Basu, Amlan Ganguly:
What Can a Remote Access Hardware Trojan do to a Network-on-Chip? 1-5 - Chih-Wei Wu, Jian-Jiun Ding:
Multi-Viewpoint Patterns and Occlusions Handling Using Hybrid Features for Vehicle Tracking. 1-5 - Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen:
A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. 1-4 - Arlene John, Barry Cardiff, Deepu John:
A 1D-CNN Based Deep Learning Technique for Sleep Apnea Detection in IoT Sensors. 1-5 - Federico Bizzarri, Laura Gardini, Paolo Nora, Angelo Brambilla:
A Stability Condition for Constant-On Time Buck Converters Suitable for Automotive Applications. 1-5 - Keisuke Kawahara, Yohtaro Umeda, Kyoya Takano:
Design of an Area-Efficient Differential Distributed Amplifier Based on the Theory of Differential Transmission Lines. 1-5 - Qiang Fu, Min Tan, Dezhi Xing, Sizhu Shao, Zhipeng Hu, Junbo Feng:
A 57.2-Gb/s PAM4 Driver for a Segmented Silicon-Photonics Mach-Zehnder Modulator with Extinction Ratio >9-dB in 45-nm RF-SOI CMOS Technology. 1-5 - Yuekang Guo, Jing Jin, Xiaoming Liu, Jianjun Zhou:
A Phase Domain Excess Loop Delay Compensation Technique with Latency Optimized Phase Selector for VCO-Based Continuous-Time ΔΣ ADC. 1-4 - Dongming Wang, Chuan Zhang, Zhenhao Ji, Yongqiang Du, Jianing Zhao, Ming Jiang, Xiaohu You:
Live Demonstration: A Cloud-Based Cell-Free Distributed Massive MIMO System. 1 - Muchan Li, Zhongzheng Tian, Xuemin Yu, Dacheng Yu, Zhongyang Ren, Liming Ren, Yunyi Fu:
Single-Electron Transistor Based on Cobalt Oxide. 1-5 - Qiwen Wang, Yongmo Park, Wei D. Lu:
Device Non-Ideality Effects and Architecture-Aware Training in RRAM In-Memory Computing Modules. 1-5 - Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang:
Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. 1-5 - Qian Gao, Wenqing Song, Zhonghai Lu, Li Li, Yuxiang Fu:
Dynamic and Traffic-Aware Medium Access Control Mechanisms for Wireless NoC Architectures. 1-5 - Yansen Huang, Rui Zhong, Wenjin Yao, Rui Wang:
Unsupervised Learning of Visual and Semantic Features for Video Summarization. 1-5 - Sivasai Guddanti, Qadeer A. Khan:
A High Efficiency Fast Transient Zero Output Ripple Buck Converter Using Split PWM Controller with Inductor Mismatch Compensation. 1-5 - Daryl Ma, Yiyang Chen, Sara S. Ghoreishizadeh, Pantelis Georgiou:
SPACEMan: Wireless SoC for Concurrent Potentiometry and Amperometry. 1-5 - Dennis E. Robey, Wesley Thio, Herbert H. C. Iu, Jason Kamran Eshraghian:
Naturalizing Neuromorphic Vision Event Streams Using Generative Adversarial Networks. 1-5 - Xinlin Xia, Xu Cheng, Yingjiang Guo, Xianhu Luo, Xianjin Deng:
A 1.6GHz Ultra-Low Phase Noise GaAs HBT PLL for Anti-Radiation Applications. 1-3 - Kavitha T. Madhu, Saptarsi Das, Abhishek Tyagi, Ankur Deshwal, Joonho Song, Seungwon Lee:
Transport Triggered near Memory Accelerator for Deep Learning. 1-5 - Chamira U. S. Edussooriya, Dileepa Marasinghe, Chamith Wijenayake, Len T. Bruton, Panajotis Agathoklis:
Improving the Attenuation of Moving Interfering Objects in Videos Using Shifted-Velocity Filtering. 1-5 - Vasilis Sakellariou, Vassilis Paliouras:
An FPGA Accelerator for Spiking Neural Network Simulation and Training. 1-5 - Maryam Habibollahi, Farnaz Fahimi Hanzaee, Dai Jiang, Henry Lancashire, Andreas Demosthenous:
An Active Microchannel Neural Interface with Artifact Reduction. 1-4 - Vishal Saxena:
A Mixed-Signal Convolutional Neural Network Using Hybrid CMOS-RRAM Circuits. 1-5 - Walter D. Leon-Salas, Jegan Rajendran, Miguel A. Vizcardo, Mauricio Postigo-Málaga:
Measuring Photosynthetically Active Radiation with a Multi-Channel Integrated Spectral Sensor. 1-5 - Luisa Fernanda Dovale, Elkim Roa:
Channel Operating Margin as Transceiver Architecture Design Tool. 1-5 - Ximing Fu, Kamal El-Sankary, Yadong Yin:
A High-Performance OTA with Hybrid of Inverter-Based OTA and Nauta OTA for High Speed Applications. 1-5 - Ning Pu, Kang Zhao, Syed Muhammad Abubakar, Yue Yin, Hanjun Jiang, Xiaofeng Yang, Zhihua Wang:
An Energy-Efficient Binarized Neural Network Using Analog-Intensive Feature Extraction for Keyword and Speaker Verification Wakeup. 1-5 - Zu-Jia Lo, Bipasha Nath, Yuan-Chuan Wang, Yun-Jie Huang, Hui-Chun Huang, Sheng-Yu Peng:
A Floating-Gate-Based Four-Channel Reconfigurable Analog Front-End Integrated Circuit. 1-4 - Cerin Ninan Kunnatharayil, Shahbaz Abbasi, Omer Ceylan, Yasar Gurbuz:
A Low-Noise 320×240 Digital ROIC for SiGe Microbolometers with a Fast Converging Offset Calibration Technique. 1-5 - Yujie Huang, Yi Ling, Ming-e Jing, Xiaoyong Xue, Xiaoyang Zeng, Yibo Fan:
Fast Style Transfer with High Shape Retention. 1-5 - Chia-Chen Chang, Yu-Tung Chin, Hossameldin A. Ibrahim, Kang-Yu Chang, Shyh-Jye Jou:
A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO. 1-5 - Chieh-Yu Lin, Li-Wei Liu, Yen-Chin Liao, Hsie-Chia Chang:
A 33.2 Gbps/Iter. Reconfigurable LDPC Decoder Fully Compliant with 5G NR Applications. 1-5 - Xinling Yue, Sijun Du:
Voltage Flip Efficiency Optimization of SSHC Rectifiers for Piezoelectric Energy Harvesting. 1-5 - Naci Pekcokguler, Dominique Morche, Adrian Frischknecht, Christoph Gerum, Andreas Burg, Catherine Dehollain:
Dynamic Range and Complexity Optimization of Mixed-Signal Machine Learning Systems. 1-5 - Hamidreza Sadreazami, Marzieh Amini, M. Omair Ahmad, M. N. S. Swamy:
EEGCAPS: Brain Activity Recognition Using Modified Common Spatial Patterns and Capsule Network. 1-5 - Maryam Saeed, Qingyuan Wang, Olev Märtens, Benoit Larras, Antoine Frappé, Barry Cardiff, Deepu John:
Event-Driven ECG Classification Using an Open-Source, LC-ADC Based Non-Uniformly Sampled Dataset. 1-5 - Angela Slavova, Ronald Tetzlaff:
Edge of Chaos in Memristor CNN with Hysteresis and Applications in Pattern Formation. 1-4 - Taeyeon Kim, Jongsun Kim:
A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC. 1-4 - R. S. Ashwin Kumar:
A Discrete-Time Delta-Sigma Modulator with Relaxed Driving Requirements And Improved Anti-Aliasing. 1-5 - Shivam Kundan, Iraklis Anagnostopoulos:
Priority-Aware Scheduling under Shared-Resource Contention on Chip Multicore Processors. 1-5 - Ziwei Li, Han Xu, Li Luo, Qi Wei, Fei Qiao:
A 5.9μW Ultra-Low-Power Dual-Resolution CIS Chip of Sensing-with-Computing for Always-on Intelligent Visual Devices. 1-5 - Shen-Fu Hsiao, Yu-Chang Chen, Yu-Che Yen:
Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning. 1-4 - Jie Sun, Jun Huang, Jianhui Wu, Weiqiang Liu:
A 2-Then-1 Bit/Cycle Asynchronous SAR ADC with Background Offset Calibration. 1-5 - Chandan Kumar Jha, Sumit Walia, Gagan Kanojia, Joycee Mekie:
FPCAM: Floating Point Configurable Approximate Multiplier for Error Resilient Applications. 1-5 - Jim Bartels, Korkut Kaan Tokgoz, Masamoto Fukawa, Shohei Otsubo, Chao Li, Ikumi Rachi, Kenichi Takeda, Hiroyuki Ito:
A 216 μW, 87% Accurate Cow Behavior Classifying Decision Tree on FPGA with Interpolated Arctan2. 1-5 - Abdelkrim Bessaad, Amine Rhouni, Dimitri Galayko:
Maximum Power Point Tracking MPPT Algorithm for Kinetic Energy Harvesters. 1-5 - Kanglin Xiao, Bo Wang, Changpei Qiu, Xin'an Wang:
Design and Implementation of a Temperature Self-Compensation Balanced Hybrid Ring Oscillator BHRO. 1-5 - Takashi Sato, Yuki Tanaka, Song Bian:
Clonable PUF: on the Design of PUFs That Share Equivalent Responses. 1-5 - Nourhan Elsayed, Hani H. Saleh, Ademola Mustapha, Baker Mohammad, Mihai Sanduleanu:
A 1: 4 Active Power Divider for 5G Phased-Array Transmitters in 22nm CMOS FDSOI. 1-5 - Ahmed M. Abdelhameed, Magdy A. Bayoumi:
An Efficient Deep Learning System for Epileptic Seizure Prediction. 1-5 - Tayeb H. C. Bouazza, Smail Bachir, Claude Duvanaud:
A New Block-Oriented Model for Reduced Complexity Digital Predistortion in Wideband Applications. 1-5 - Yanzhao Ma, Zhengjie Ye, Fei Li, Zhitong Chen, Kai Cui, Xiaoya Fan:
A Fully-Integrated Reference-Free Relaxation Oscillator with No Comparators. 1-5 - Hu Zhang, Chenghua Wang, Chenggang Yan, Yijun Cui, Chongyan Gu, Máire O'Neill, Weiqiang Liu:
A Dynamic Highly Reliable SRAM-Based PUF Retaining Memory Function. 1-5 - Mauro Di Marco, Mauro Forti, Giacomo Innocenti, Alberto Tesi:
Transient Control in Targeting Multistable Dynamics of a Memristor Circuit. 1-5 - Jungmin Kwon, Chaeyeon Cha, Hyunggon Park:
Multilayered LSTM with Parameter Transfer for Vehicle Speed Data Imputation. 1-5 - Shenghan Wang, Yangyang Jiang, Hengling Zhao, Xue Yang, Zhonghao Zhang, Ce Zhu, Ying Li, Yipeng Liu:
Smart Dysphagia Detection System with Adaptive Boosting Analysis of Throat Signals. 1-5 - Jisu Kwon, Sejong Oh, Daejin Park:
Metamorphic Edge Processor Simulation Framework Using Flexible Runtime Partial Replacement of Software-Embedded Verilog RTL Models. 1-5 - Halil Ibrahim Kaysici, Salih Ergün:
Duty Cycle Correction Circuit and Its Application for High Speed Random Number Generation. 1-5 - Yan Huang, Erya Deng, Jinyu Bai, Qing Yang, Wang Kang, Biao Pan:
HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy. 1-5 - Yao Qin, Xin Ming, Zhiyi Lin, Yuanyuan Liu, Yongyu Zhang, Zhaoji Li, Bo Zhang:
An Anti-Overcharged High-dV/dt-Immunity Capacitive Level Shifter with Dynamic Discharge Control for Half-Bridge GaN Driver. 1-5 - Shahriar Shahabuddin, Zaheer Khan, Markku J. Juntti:
Concept Drift Detection Methods for Deep Learning Cognitive Radios: A Hardware Perspective. 1-5 - Haoyuan Ma, You Wang, Rashid Ali, Zhengyi Hou, Deming Zhang, Erya Deng, Gefei Wang, Weisheng Zhao:
SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework. 1-5 - Julio Torres-Tello, Seok-Bum Ko:
Identifying Useful Features in Multispectral Images with Deep Learning for Optimizing Wheat Yield Prediction. 1-5 - Michele Caselli, Marco Ronchi, Andrea Boni:
An Integrated Low Power Temperature Sensor for Food Monitoring Applications. 1-4 - Tommaso Polonelli, Lukas Schulthess, Philipp Mayer, Michele Magno, Luca Benini:
H-Watch: An Open, Connected Platform for AI-Enhanced COVID19 Infection Symptoms Monitoring and Contact Tracing. 1-5 - Srisubha Kalanadhabhatta, Rashi Dutt, S. Saqib Khursheed, Amit Acharyya:
IC Age Estimation Methodology Using IO Pad Protection Diodes for Prevention of Recycled ICs. 1-5 - Junghoon Cho, Junhyun Song, Jongsun Park:
Low Cost Heterogeneous ARIA S-Box Implementation for CPA-Resistance. 1-5 - Hao Su, Jie Yang, Lei Sun, Zhiping Lin:
A Solver of Fukunaga Koontz Transformation without Matrix Decomposition. 1-4 - Nour El Hoda Djidi, Matthieu Gautier, Antoine Courtay, Olivier Berder:
Enhancing Wake-Up Receivers Reliability through Preamble Filtering and Minimum Energy Coding. 1-5 - Christopher Bengel, Anne Siemon, Vikas Rana, Stephan Menzel:
Implementation of Multinary Łukasiewicz Logic Using Memristive Devices. 1-5 - Jiaqi Liu, Min Xiao, Xiaorui Lin, Ran Zhu, Zhuoling Xiao, Bo Yan, Shuisheng Lin, Liang Zhou:
Adaptive Real-Time Loop Closure Detection Based on Image Feature Concatenation. 1-5 - Corentin Pochet, Haowei Jiang, Drew A. Hall:
Ultra-Low Leakage ESD Protection Achieving 10.5 fA Leakage. 1-5 - Gonçalo Rodrigues, Diogo Brito, Hanna Iva Busse, Jorge R. Fernandes, João Silva, Taimur Gibran Rabuske:
A Temperature-Compensated 57 PPM/°C 10MHz, 2.4μW Stacked Ring Oscillator. 1-5 - Asif Wahid, Rajath Bindiganavile, Armin Tajalli:
Optimal PAM Order for Wireline Communication. 1-5 - Chiang-Jen Peng, Yun-Ju Chan, Cheng Yu, Syu-Siang Wang, Yu Tsao, Tai-Shih Chi:
Attention-Based Multi-Task Learning for Speech-Enhancement and Speaker-Identification in Multi-Speaker Dialogue Scenario. 1-5 - Taegun Yim, Choong Keun Lee, Hongil Yoon:
A High Speed Modified Dickson Charge Pump. 1-5 - Song-I Cheon, Soon-Jae Kweon, Youngin Kim, Sohmyung Ha, Minkyu Je:
A Power-Efficient, Wide-Frequency-Range Impedance Measurement IC Using Frequency-Shift Technique. 1-5 - Seung-Hwan Bae, Hyuk-Jae Lee, Hyun Kim:
DC-AC: Deep Correlation-Based Adaptive Compression of Feature Map Planes in Convolutional Neural Networks. 1-5 - Michele Mastella, Elisabetta Chicca:
A Hardware-Friendly Neuromorphic Spiking Neural Network for Frequency Detection and Fine Texture Decoding. 1-5 - Nicolas Fahier, Cheng-Jie Yang, Wai-Chi Fang:
Wearable Cardiovascular Monitoring System Design Using Human Body Communication. 1-5 - Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang:
A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop. 1-4 - Dong-Hwi Choi, Dong-Woo Jee:
1V 4.49nW/Pixel Retinal Prosthesis Chip with Light-to-Stimulus Duration Converter. 1-5 - Jialiang Tang, Mingjin Liu, Ning Jiang, Wenxin Yu, Changzheng Yang:
Spatial and Channel Dimensions Attention Feature Transfer for Better Convolutional Neural Networks. 1-5 - Ning Jiang, Jialiang Tang, Wenxin Yu, Jinjia Zhou, Liuwei Mai:
Gradient Local Binary Pattern Layer to Initialize the Convolutional Neural Networks. 1-5 - Heon Hwa Cheong, Suhwan Kim:
A Power-Efficient and Fast-Locking Digital Quadrature Clock Generator with Ping-Pong Phase Detection. 1-4 - Vinay Joshi, Wangxin He, Jae-sun Seo, Bipin Rajendran:
Hybrid In-Memory Computing Architecture for the Training of Deep Neural Networks. 1-5 - Mojtaba Hasannezhad, Wei-Ping Zhu, Benoît Champagne:
A Novel Low-Complexity Attention-Driven Composite Model for Speech Enhancement. 1-5 - Ying-Hao Zhang, Xiao Fan Liu:
Traffic Redundancy in Blockchain Systems: The Impact of Logical and Physical Network Structures. 1-5 - Rakesh Rena, Suraj Kumar Verma, Vijaya Sankara Rao Pasupureddi:
A Process Scalable Architecture for Low Noise Figure Sub-Sampling Mixer-First RF Front-End. 1-5 - Maxwell Ballot, Tinus Stander:
A RF Amplifier with Oscillation-Based BIST Based on Differential Power Detection. 1-4 - Matthew Ward, Kevin Malmsten, Hassan A. Salamy, Cheol-Hong Min:
Data Balanced Bagging Ensemble of Convolutional- LSTM Neural Networks for Time Series Data Classification with an Imbalanced Dataset. 1-5 - Lu Lu, Yuzong Chen, Tony Tae-Hyoung Kim:
A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme. 1-5 - Qian Zhao, Yajun Mao:
The Evolution of Submissive Strategies on the Clustered Scale-Free Networks. 1-5 - Yara Yaacoub, Fabienne Nouvel, Sylvain Haese, Jean-Yves Baudais:
VLC Modelization for VLC-PLC System: Evaluation of Optical, Electrical, and Frequency Behavior. 1-5 - Stanislas Dubois, Julien Choveton-Caillat, Wedji Kane, Terii Gilbert, Mohcine Nfaoui, Mohamed El Boudali, Marwane Rezzouki, Guillaume Ferré:
Bee Detection for Fruit Cultivation. 1-5 - Nian Zhang, Chenchang Zhan, Guanghua Ye, Chuqi Chen, Xuening Li, Jun Yi:
Analysis of Multi-Phase Trans-Inductor Voltage Regulator with Fast Transient Response for Large Load Current Applications. 1-5 - Kasem Khalil, Bappaditya Dey, Ashok Kumar, Magdy A. Bayoumi:
A Reversible-Logic Based Architecture for Long Short-Term Memory (LSTM) Network. 1-5 - Alexi Bonament, Morgan Madec, Christophe Lallement:
Compact Modeling of Reaction-Diffusion-Advection Mechanisms for the Virtual Prototyping of Lab-on-Chip. 1-5 - Hsin-Wen Ku, Wei-Hao Fang, Huan-Lun Tso, Pei-Yun Tsai, Yuan-Hao Huang:
Low-Complexity Wideband Hybrid Precoding for mmWave MIMO-OFDM. 1-5 - Leyu Zhang, Yutai Sun, Yifei Shen, Wenqing Song, Xiaohu You, Chuan Zhang:
Efficient Fast-SCAN Flip Decoder for Polar Codes. 1-5 - Tero Partanen, Ari Lemmetti, Panu Sjövall, Jarno Vanne:
High-Level Synthesis Implementation of Transform-Exempted SATD Architectures for Low-Power Video Coding. 1-5 - Nicola Femia, Giulia Di Capua:
Optimum Design of Differential-Mode Input Filters for DC-DC Switching Regulators. 1-5 - Lindong Wu, Zongwei Wang, Ming Zhao, Wei Hu, Yimao Cai, Ru Huang:
A High Accuracy Multiple-Command Speech Recognition ASIC Based on Configurable One-Dimension Convolutional Neural Network. 1-4 - Nicoletta Risi, Enrico Calabrese, Giacomo Indiveri:
Instantaneous Stereo Depth Estimation of Real-World Stimuli with a Neuromorphic Stereo-Vision Setup. 1-5 - Md Faizul Bari, Baibhab Chatterjee, Shreyas Sen:
DIRAC: Dynamic-IRregulAr Clustering Algorithm with Incremental Learning for RF-Based Trust Augmentation in IoT Device Authentication. 1-5 - Yoo-Seung Won, Shivam Bhasin:
A Systematic Side-Channel Evaluation of Black Box AES in Secure MCU: Architecture Recovery and Retrieval of PUF Based Secret Key. 1-5 - Tze Hin Cheung, Jussi Ryynänen, Aarno Pärssinen, Kari Stadius:
A 5.4-GHz 2/3/4-Modulus Fractional Frequency Divider Circuit in 28-nm CMOS. 1-5 - Yichao Liu, Junrui Liang:
Equivalent Impedance Analysis and Compensation of Full-Wave Bridge Rectifier under High-Frequency Operation with Extended Impedance Method. 1-5 - Imran M. Saied, Tughrul Arslan, Rahmat Ullah, Changjiang Liu, Fengzhou Wang:
Hardware Accelerator for Wearable and Portable Radar-Based Microwave Breast Imaging Systems. 1-5 - Marios Neofytou, Pavlos Athanasiadis, Marcello Ganzerli, Maarten Lont, Georgi I. Radulov, Kostas Doris:
A Novel 2-Dimensional Correction Method for mm-Wave Cartesian I/Q Modulators. 1-5 - Kai Chen, Yimin Huang, Yuan Du, Zhuang Shao, Xingyu Gu, Li Du, Zhongfeng Wang:
A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference. 1-5 - Hehe Li, Xin Li, Lianfeng Li, Junbin Pan, Shujia Zhu, Jinwei Du, Peng Wang:
BAFPN: An Optimization for YOLO. 1-5 - Shree Thirumalaikumar, Matthew Douthwaite, Pantelis Georgiou:
Design of a Calorimetric Flow Rate Sensor for On-Body Sweat Monitoring. 1-5 - Xiaoyu Huang, Edward George Jones, Siru Zhang, Shouyu Xie, Steve B. Furber, Yannis Goulermas, Edward Marsden, Ian Baistow, Srinjoy Mitra, Alister Hamilton:
An FPGA Implementation of Convolutional Spiking Neural Networks for Radioisotope Identification. 1-5 - Sujin Kim, Hoyong Sung, Sohyeon Kim, Minkyu Je, Ji-Hoon Kim:
ML-Based Humidity and Temperature Calibration System for Heterogeneous MOx Sensor Array in ppm-Level BTEX Monitoring. 1-5 - Alzemiro Henrique Lucas da Silva, Iaçanã I. Weber, André Luís Del Mestre Martins, Fernando Gehm Moraes:
Dynamic Thermal Management in Many-Core Systems Leveraged by Abstract Modeling. 1-5 - Dong-Wan Ko, Won-Young Lee:
A Low EMI Transmitter for DRAM Interface with Quadrature Clock Corrector. 1-5 - Einat Levy, Aharon Sfez, Roman Golman, Odem Harel, Adam Teman:
4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality. 1-4 - Mohamed B. Elamien, Brent J. Maundy, Leonid Belostotski, Ahmed S. Elwakil:
A Wideband 24-29 GHz Differential All-Pass Filter in 65-nm CMOS. 1-5 - Kun-Chih Chen, Chi-Hsun Wu:
High-Accurate Stochastic Computing for Artificial Neural Network by Using Extended Stochastic Logic. 1-4 - George Mekhael, Nathaniel Morgan, Mounica Patnala, Trond Ytterdal, Maher E. Rizkalla:
GNRFET-Based DC-DC Converters for Low Power Data Management in ULSI System, a Feasibility Study. 1-5 - Vivek Nautiyal, Gaurav Singla, Bikas Maiti, Martin Kinkade:
Self-Timed Write Aid Circuit for Tall Memories in Advanced CMOS Technologies. 1-4 - Yu-Sheng Lin, Wei-Chao Chen, Chia-Lin Yang, Shao-Yi Chien:
A Dense Tensor Accelerator with Data Exchange Mesh for DNN and Vision Workloads. 1-5 - Hao Chen, Shanxin Zhang, Hui Yuan, Xinghai Yang, Huaxiang Zhang, Jiande Sun:
Monocular 3D Pedestrian Localization Fusing with Bird's Eye View. 1-5 - Muhammad Furqan Ayub, Muhammad Awais Bin Altaf:
A 77.8-dB DR, 114.2 fJ/Step Amplifier-Less Current-to-Digital Converter. 1-5 - Shan Cao, Limin Jiang, Ting Lin, Shunqing Zhang, Shugong Xu:
A Semi-Folded Decoding Architecture for Flexible Codeword Length Configuration of Polar Codes. 1-5 - Inbal Stanger, Netanel Shavit, Ramiro Taco, Marco Lanuzza, Alexander Fish:
Live Demo: Silicon Evaluation of Multimode Dual Mode Logic for PVT-Aware Datapaths. 1 - Zuo-Wei Yeh, Chia-Hua Hsu, Chen-Fu Yeh, Wen-Chieh Wu, Cheng-Te Wang, Chung-Chuan Lo, Kea-Tiong Tang:
POPPINS: A Population-Based Digital Spiking Neuromorphic Processor with Integer Quadratic Integrate-and-Fire Neurons. 1-5 - David Liang Tai Wong, Yongfu Li, Deepu John, Weng Khuen Ho, Chun-Huat Heng:
Resource and Energy Efficient Implementation of ECG Classifier Using Binarized CNN for Edge AI Devices. 1-5 - Chithra:
A Technique for Measuring Picosecond Delays Using Phase Modulation. 1-5 - Moustafa Saleh, Ali Ibrahim, Francesco Menichelli, Yasser Mohanna, Maurizio Valle:
Efficient Machine Learning Algorithm for Embedded Tactile Data Processing. 1-5 - Carmine Paolino, Fabio Pareschi, Riccardo Rovatti, Gianluca Setti:
Stability and Mismatch Robustness of a Leakage Current Cancellation Technique. 1-5 - Zhenhong Liu, Linfeng Zhou, Cheng Chen, Zhouchen Ma, Guangpeng Shen, Yongfu Li, Jian Zhao:
An Energy Efficient Functional near Infrared Spectroscopy System Employing Spatial Adaptive Sampling Technique. 1-5 - Jing Wang, Yici Cai, Qiang Zhou:
A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. 1-5 - Federico D'Aniello, Andreas Ott, Andrea Baschirotto:
Supply Line Embedded Communication in Automotive Sensor/Actuator Networks. 1-5 - Yu-Sheng Ting, Yu-Fan Teng, Tzi-Dar Chiueh:
Batch Normalization Processor Design for Convolution Neural Network Training and Inference. 1-4 - David Ariando, Yiqiao Tang, Shin Utsuzawa, Yi-Qiao Song, Soumyajit Mandal:
A Compact GaNFET-Based Power Amplifier for ASIC-Based Miniature NMR Spectrometers. 1-5 - Zubaer Ibna Mannan, Hyongsuk Kim:
Neuro-Memristive Circuit for Bio-Synaptic Plasticity. 1-5 - Jung-Hee Kim, Jeong-Hwan Choi, Jinyoung Son, Gyeong-Su Kim, Jihwan Park, Joon-Hyuk Chang:
MIMO Noise Suppression Preserving Spatial Cues for Sound Source Localization in Mobile Robot. 1-5 - Jialiang Tang, Mingjin Liu, Ning Jiang, Wenxin Yu, Changzheng Yang, Jinjia Zhou:
Knowledge Distillation Based on Positive-Unlabeled Classification and Attention Mechanism. 1-5 - Chao Chen, Jie Sun, Chenghua Wang, Weiqiang Liu:
A 10-b 500MS/s Partially Loop-Unrolled SAR ADC with a Comparator Offset Calibration Technique. 1-5 - Nishat Tarannum Tasneem, Dipon K. Biswas, Ifana Mahbub, Pashupati R. Adhikari, Russell C. Reid:
Self-Powered Motion Tracking Sensor Integrated with Low-Power CMOS Circuitry. 1-5 - Shaowei Zhen, Rui Yang, Dongming Wu, Yufan Cheng, Ping Luo, Bo Zhang:
Design of Hybrid Dual-Path DC-DC Converter with Wide Input Voltage Efficiency Improvement. 1-5 - Jiliang Zhang, Gaofeng Tan, Yue Hu, Jian Zhao, Mingyi Chen, Yongfu Li, Liang Qi:
A Multi-Rate Hybrid DT/CT Mash ΔΣ Modulator with High Tolerance to Noise Leakage. 1-5 - Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo:
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML. 1-5 - Yigit Demirag, Filippo Moro, Thomas Dalgaty, Gabriele Navarro, Charlotte Frenkel, Giacomo Indiveri, Elisa Vianello, Melika Payvand:
PCM-Trace: Scalable Synaptic Eligibility Traces with Resistivity Drift of Phase-Change Materials. 1-5 - Zhongyuan Tian, Lin Chen, Xiao Li, Jun Feng, Jiang Xu:
Multi-Core Power Management through Deep Reinforcement Learning. 1-5 - Hengrui Zhao, Dong Liu, Houqiang Li:
Efficient Integer-Arithmetic-Only Convolutional Networks with Bounded ReLU. 1-5 - Liang Chang, Zixuan Zhu, Zhen Zhu, Siqi Yang, Weihang Li, Jun Zhou:
Energy-Efficient Spin-Orbit Torque MRAM Operations for Neural Network Processor. 1-5 - Yifei Pei, Ying Liu, Nam Ling, Lingzhi Liu, Yongxiong Ren:
Class-Specific Neural Network for Video Compressed Sensing. 1-5 - Yifan Qian, Chang Meng, Yawen Zhang, Weikang Qian, Runsheng Wang, Ru Huang:
Approximate Logic Synthesis in the Loop for Designing Low-Power Neural Network Accelerator. 1-5 - Shintaro Arai, Wataru Tamura, Takaya Yamazato, Hiroyuki Hatano, Masato Saito, Hiroya Tanaka, Yukihiro Tadokoro:
Circuit Experiment of Photodiode-Type Visible Light Communication Using the Stochastic Resonance Generated by Interfering Light Noise. 1-5 - Aibin Yan, Liang Ding, Chuanbo Shan, Haoran Cai, Xiaofeng Chen, Zhanjun Wei, Zhengfeng Huang, Xiaoqing Wen:
TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation. 1-5 - Yang Liu, Yushen Fu, Chengyu Huang, Huazhong Yang, Xueqing Li:
Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs. 1-5 - Bo Qiao, Ajmal Vadakkan Kayyil, Jeffrey S. Walling, David J. Allstot:
I/Q-Sharing Switched-Capacitor Power Amplifier with Baseband Harmonic-Rejection and Wilkinson Combiner. 1-4 - Wei Xing Zheng, Da-Zheng Feng, Zhu Pan, Jin Li:
An Improved Constant Modulus Algorithm and Its Generalized Form for Blind Equalization. 1-5 - Weifu Chen, Mingyi Chen, Yuzhi Hao, Liang Qi, Jian Zhao:
A 1-μA-Quiescent-Current Capacitor-Less LDO Regulator with Adaptive Embedded Slew-Rate Enhancement Circuit. 1-5 - Subhajit Dutta Chowdhury, Gengyu Zhang, Yinghua Hu, Pierluigi Nuzzo:
Enhancing SAT-Attack Resiliency and Cost-Effectiveness of Reconfigurable-Logic-Based Circuit Obfuscation. 1-5 - Harshit Rathore, Imon Mondal:
Breaking the Trade-Off between Bandwidth and Close-in Blocker Attenuation in an N-Path Filter. 1-5 - Michael Pietzko, Johannes Wagner, Ahmed Abdelaal, John G. Kauffman, Maurits Ortmanns:
Influence of Excess Loop Delay on the STF of Continuous-Time Delta-Sigma Modulators. 1-5 - Zahra Ebrahimi, Akash Kumar:
BioCare: An Energy-Efficient CGRA for Bio-Signal Processing at the Edge. 1-5 - Yoko Uwate, Thomas Ott, Yoshifumi Nishio:
Effect of Stochastically Coupling on Frustrated Triangular Oscillatory Network. 1-5 - Daniel Iparraguirre, José G. Delgado-Frias, Howard Heck:
A Crosstalk-Harnessed Signaling Enhancement that Eliminates Common-Mode Encoding. 1-5 - Hao Wang, Sen-Ching S. Cheung:
Augmented Reality Circuit Learning. 1-5 - Jifu Liang, Hasantha Malavipathirana, S. I. Hariharan, Arjuna Madanayake, Soumyajit Mandal:
Analog Switched-Capacitor Circuits for Solving the Schrödinger Equation. 1-5 - Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Yun Da Bryan Seah, Ying Hung Yvonne Lam, Liter Siek:
Low Voltage Low Power Output Programmable OCL-LDO with Embedded Voltage Reference. 1-5 - Agung W. Setiawan, Arga Aridarma, Reza T. Setiabekti:
Comparison of Instructor and Professionals Assessment in Project-Based Learning. 1-4 - Yu-Sheng Wu, Sih-Sian Wu, Tan Huang, Liang-Gee Chen:
Online Training Refinement Network and Architecture Design for Stereo Matching. 1-5 - Ruihang Miao, Peilin Liu, Zheng Gong, Wuyang Xue, Xingwu Ji, Rendong Ying:
Adaptive Stereo Direct Visual Odometry with Real-Time Loop Closure Detection and Relocalization. 1-5 - Xiaozhe Fan, James Hidalgo, Walter D. Leon-Salas:
A Single-Aperture, Single-Pixel Reader for Optical Frequency Identification. 1-5 - Christopher E. Arcadia, Kangping Hu, Slava Epstein, Meni Wanunu, Aaron Adler, Jacob K. Rosenstein:
CMOS Electrochemical Imaging Arrays for the Detection and Classification of Microorganisms. 1-5 - Umanath Kamath, Lorenzo Rota, Aldo Pena-Perez, Bojan Markovic, Aseem Gupta, Camillo Tamma, Angelo Dragone:
Reference Voltage Buffer for Hybrid RC-DAC SAR ADCs in 130 nm CMOS Process. 1-4 - Jingci Yang, Yanhan Zeng, Weijian Chen, Yihan Lin, Haochang Zhi, Hongzhou Tan:
A 77-nA and Three-Output CMOS Voltage Reference with -73dB PSRR for Energy Harvesting Systems. 1-5 - Nipun Kaushik, John Hu:
A Switched-Capacitor Power Side-Channel Attack Detection Circuit in 65-nm CMOS. 1-5 - Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, Yi Hsu:
Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. 1-4 - Souris Sahu, Rashi Dutt, Amit Acharyya:
Control Strategy for Efficient Utilisation of Regenerative Power through Optimal Load Distribution in Hybrid Energy Storage System. 1-5 - Md. Munir Hasan, Jeremy Holleman:
Hardware Model Based Simulation of Spiking Neuron Using Phase Plane. 1-5 - Amir Antonir, Chamith Wijenayake, Aleksandar Ignjatovic:
Acquisition of High Bandwidth Signals by Sampling an Analog Chromatic Derivatives Filterbank. 1-5 - Chance Tarver, Alexios Balatsoukas-Stimming, Christoph Studer, Joseph R. Cavallaro:
OFDM-Based Beam-Oriented Digital Predistortion for Massive MIMO. 1-5 - Ce Ma, Yuxin Ji, Cai Qiao, Ting Zhou, Liang Qi, Yongfu Li:
An Energy-Efficient Level Shifter Using Time Borrowing Technique for Ultra Wide Voltage Conversion from Sub-200mV to 3.0V. 1-5 - Tiago D. Perez, Malik Imran, Pablo Vaz, Samuel Pagliarini:
Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO. 1-5 - Heng You, Jia Yuan, Zenghui Yu, Shushan Qiao:
A 0.5V 36nW 10-Transistor Power-on-Reset Circuit with High Accuracy. 1-5 - Hua Fan, Bochuan Li, Jianming Liu, Qian Shen, Haizhu Wang, Qi Wei, Quanyuan Feng, Hadi Heidari:
Project-Based Course in Electronic Engineering Education. 1-5 - Wei-Chih Li, Cheng-Jie Yang, Bo-Ting Liu, Wai-Chi Fang:
Live Demonstration: An AI-Edge Platform with Multimodal Wearable Physiological Signals Monitoring Sensors for Affective Computing Applications. 1 - Yu-Wen Chen, Kuo-Hsuan Hung, Shang-Yi Chuang, Jonathan Sherman, Wen-Chin Huang, Xugang Lu, Yu Tsao:
EMA2S: An End-to-End Multimodal Articulatory-to-Speech System. 1-5 - Bo Li, Ediz Cetin:
Waveform Domain Deep Learning Approach for RF Fingerprinting. 1-5 - Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee:
Normalized Differential Power Analysis - for Ghost Peaks Mitigation. 1-5 - Chai Wah Wu, Ann Chen Wu, James Strom:
DeepTune: Robust Global Optimization of Electronic Circuit Design Via Neuro-Symbolic Optimization. 1-5 - Younghoon Byun, Youngjoo Lee:
Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques. 1-5 - Masahiro Kawano, Tran Thi Thao Nguyen, Yuhei Nagao, Leonardo Lanante, Hiroshi Ochi, Masayuki Kurosaki:
Null Beamforming to Self in Cooperative MIMO for Full-Duplex Systems. 1-4 - Jiachen Xu, Ethan Chen, Vanessa Chen:
Live Demonstration: Energy-Efficient Data Symbol Detection Via Boosted Learning for Multi-Actuator Data Storage Systems. 1 - Shahzad Muzaffar, Ibrahim M. Elfadel:
Beyond Arduino: A Guide for the Perplexed. 1-5 - Zong Jie Shen, Chun Zhao, Ka Lok Man, Yina Liu, Cezhou Zhao:
Long-Term Memory Performance with Learning Behavior of Artificial Synaptic Memristor Based on Stacked Solution-Processed Switching Layers. 1-4 - Ajmal Vadakkan Kayyil, Bo Qiao, David J. Allstot:
Linearity Improvement Techniques for CMOS Switched-Capacitor Power Amplifiers. 1-5 - Xiangyu Meng, Weihao Kong, Haifeng Yang, Yecong Li, Xuan Li:
A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS. 1-4 - Hema Sai Kalluru, Prasenjit Saha, Andleeb Zahra, Zia Abbas:
Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations. 1-5 - Karan Sohal, Danilo Manstretta, Rinaldo Castello:
A 2nd Order Current-Mode Filter with 14dB Variable Gain and 650MHz to 1GHz Tuning-Range in 28nm CMOS. 1-5 - Anjana Dissanayake, Steven M. Bowers, Benton H. Calhoun:
Stacked Transconductance Boosting for Ultra-Low Power 2.4GHz RF Front-End Design. 1-4 - Lukas Straczek, Carsten Heinicke, Dominik Veit, Jürgen Oehm:
An Offset and 1/f-Noise Compensated Current-to-Digital Conversion for Active Pixels in MEA Applications. 1-5 - Holger Mandry, Sven Müelich, Joachim Becker, Robert F. H. Fischer, Maurits Ortmanns:
Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs. 1-5 - Meng Zhao, Qiancheng Zhao, Zhongjian Chen, Wengao Lu, Yacong Zhang, Guizhen Yan:
A 0.084% Nonlinearity Open-Loop Capacitive Micro-Accelerometer with On-Chip Digital Nonlinearity Calibration and Embedded EEPROM. 1-5 - Mingyao Zheng, Yun Tie, Fang Zhu, Lin Qi, Yuning Gao:
Research on Panoramic Stereo Live Streaming Based on the Virtual Reality. 1-5 - Udita Mukherjee, Tanmay Halder, Anand Kannan, Sovan Ghosh, Shanthi Pavan:
A 28.5µW All-Analog Voice-Activity Detector. 1-5 - Arijit Karmakar, Valentijn De Smedt, Paul Leroux:
A 0.18 pJ/Step Time-Domain 1st Order ΔΣ Capacitance-to-Digital Converter in 65-nm CMOS. 1-5 - Jiajie Huang, Lulu Wang, Yewangqing Lu, Ting Zhou, Zhiwen Gu, Mingyi Chen, Yongfu Li:
A Highly Configurable and Extensible Spiral Capacitor Design for High Density or High Precision Applications. 1-5 - Sanjeev Tannirkulam Chandrasekaran, Akshay Jayaraj, Naveen Ramesh, Arindam Sanyal:
33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator. 1-4 - Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. 1-5 - Ahmed Abdelaal, Michael Pietzko, Mohamed A. Mokhtar, John G. Kauffman, Maurits Ortmanns:
FIR Filter with Symmetric Non-Equal Coefficients for CT Delta-Sigma Modulators. 1-5 - Camilo Rojas, Hanssel Morales, Elkim Roa:
A Low-Cost Bug Hunting Verification Methodology for RISC-V-Based Processors. 1-5 - Tomoaki Koizumi, Takao Waho, Hitoshi Hayashi:
A Delta-Sigma-Modulation Multi-Channel Network with Improved Noise-Shaping Characteristics. 1-5 - Darukeesan Pakiyarajah, Sakila S. Jayaweera, Chamira U. S. Edussooriya, Chamith Wijenayake, Arjuna Madanayake:
WLS Design of M-D Complex-Coefficient FIR Filters with Low Group Delay Using Second-Order Cone Programming. 1-5 - Jinhua Wang, Dong Sam Ha:
A Wide Input Power Line Energy Harvesting Circuit for Wireless Sensor Nodes. 1-5 - Alon Amid, Albert J. Ou, Krste Asanovic, Yakun Sophia Shao, Borivoje Nikolic:
Vertically Integrated Computing Labs Using Open-Source Hardware Generators and Cloud-Hosted FPGAs. 1-5 - Ahmed Abdelaziz, Tawfiq Musah:
The Effect of Equalization on Nonlinearity in Time-Based Decision Feedback Equalizers. 1-5 - Cecilia De la Parra, Ahmed El-Yamany, Taha Soliman, Akash Kumar, Norbert Wehn, Andre Guntoro:
Exploiting Resiliency for Kernel-Wise CNN Approximation Enabled by Adaptive Hardware Design. 1-5 - Wei Song, Xuecheng Wang, Xin Li, Yu Pan, Milin Zhang:
Design of a Wireless Multiple-Mode Human Behavior Evaluation System. 1-5 - Liao Wu, Wenjie Kang, Minghua Xie, Peidong Zhu:
A Self-Powered Multi-Input Bridgeless Series-SSHI Circuit for Piezoelectric Energy Harvesting. 1-4 - Kuihe Yang, Ziying Song, Yingchao Zhang, Yufan Zhou, Xiaohan Sun, Jianxuan Wang:
Model Optimization Method Based on Vertical Federated Learning. 1-5 - Alireza Esmaeilzehi, M. Omair Ahmad, M. N. S. Swamy:
MorphoNet: A Deep Image Super Resolution Network Using Hierarchical and Morphological Feature Generating Residual Blocks. 1-5 - Weihong Yan, Yuxin Ji, Lining Hu, Ting Zhou, Yang Zhao, Yan Liu, Yongfu Li:
A Resource-Efficient, Robust QRS Detector Using Data Compression and Time-Sharing Architecture. 1-5 - Abdulqader Nael Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui:
Spin Wave Based Full Adder. 1-5 - Wei Wang, Yimeng Chai, Ziwen Wu, Litong Ge, Xuechun Han, Baohua Zhang, Chuang Wang, Yue Li:
Generating Adversarial Patches Using Data-Driven MultiD-WGAN. 1-5 - Kuan-Ting Lin, Ching-Te Chiu, Jheng-Yi Chang, Shan-Chien Hsiao:
High Utilization Energy-Aware Real-Time Inference Deep Convolutional Neural Network Accelerator. 1-5 - Andrea Donisi, Luigi Di Benedetto, Gian Domenico Licciardo, Alfredo Rubino, Eduardo Piccirilli, Emilio Lanzotti:
Design of Digital Controller for SVPWM Algorithm with Real-Time Control of the Output Amplitude and Switching Frequency. 1-5 - Mohammad Attari, Jesús Rodríguez Sánchez, Liang Liu, Steffen Malkowsky:
An Application Specific Vector Processor for CNN-Based Massive MIMO Positioning. 1-5 - Kaisa Ryynänen, Kari Stadius, Andreas Hammer, Mikko Varonen, Henrik Forsten, Tero Kiuru, Ville Viikari, Jussi Ryynänen:
A Compact Low-Power 140-GHz Low-Noise Amplifier with 19-dB Gain and 7-dB NF. 1-5 - Janak Sharda, Ritvik Sharma, Debanjan Bhowmik:
A Crossbar Array of Analog-Digital-Hybrid Volatile Memory Synapse Cells for Energy-Efficient On-Chip Learning. 1-5 - Guillaume Guérin, Gabriel A. Rincón-Mora:
Power-Conversion Efficiency: Loss Dominance, Optimization, & Design Insight. 1-5 - Tsung-Han Tsai, Po-Hsien Wu, Xin-Hui Lin, Po-Ting Chi:
Live Demonstration: Intelligent Voice Wake-up Human-Following Robot. 1 - Bishenghui Tao, Ivan Wang Hei Ho, Hong-Ning Dai:
Complex Network Analysis of the Bitcoin Blockchain Network. 1-5 - Jiyuan Hu, Jun Wang, Guangyu Zhong, Jian Cao, Ren Mao, Fan Liang:
A Lossless Intra Reference Block Recompression Scheme for Bandwidth Reduction in HEVC-IBC. 1-5 - Zhongyuan Fang, Liheng Lou, Kai Tang, Wensong Wang, Bo Chen, Yisheng Wang, Yuanjin Zheng:
A CMOS-Integrated Radar-Assisted Cognitive Sensing Platform for Seamless Human-Robot Interactions. 1-4 - Jinwoo Jeon, Junyoung Maeng, Inho Park, Hyunjin Kim, Chulwoo Kim:
A Hybrid DC-DC Converter Capable of Supplying Heavy Load in Step-Up and Step-Down Mode. 1-5 - Xin Li, Hong Tang, Guobiao Hu, Junrui Liang:
Live Demo of a Transient-Motion-Powered Human Motion Detector. 1 - Jingxi Yang, Chi K. Tse:
Homoclinic Bifurcation of a Voltage Source Converter with Second-Order Grid-Forming Control. 1-4 - Ckristian Duran, Héctor Gómez, Elkim Roa:
AES Sbox Acceleration Schemes for Low-Cost SoCs. 1-5 - Mariam Rakka, Rouwaida Kanj:
Importance Splitting Sample Point Reuse for Efficient Memory Yield Estimation. 1-5 - Tsung-Wen Sun, Tsung-Heng Tsai:
A Battery Management System with Charge Balancing and Aging Detection Based on ANN. 1-4 - Rowshon Munny, John Hu:
Power Side-Channel Attack Detection through Battery Impedance Monitoring. 1-5 - Patrick Kurth, Kai Misselwitz, Urs Hecht, Friedel Gerfers:
A 56 GHz 19 fs RMS-Jitter Sub-Sampling Phase-Locked Loop for 112 Gbit/s Transceivers. 1-5 - Weijun Ma, Junyuan Fang, Jiajing Wu:
Sequential Node Attack of Complex Networks Based on Q-Learning Method. 1-5 - Atia B. Amin, Georges Octave Dubois, Séphora Thurel, Jean Danyluk, Mounir Boukadoum, Abdoulaye Baniré Diallo:
Wireless Sensor Network and Irrigation System to Monitor Wheat Growth under Drought Stress. 1-4 - Surendra Hemaram, Jai Narayan Tripathi:
Optimal Design of a Decoupling Network Using Variants of Particle Swarm Optimization Algorithm. 1-5 - Hector A. Gonzalez, Florian Kelber, Marco Stolba, Chen Liu, Bernhard Vogginger, Stefan Hänzsche, Stefan Scholze, Sebastian Höppner, Christian Mayr:
Ultra-High Compression of Twiddle Factor ROMs in Multi-Core DSP for FMCW Radars. 1-5 - Zhengyu Wang, Lewis Keeble, Nicolas Moser, Tor Sverre Lande, Pantelis Georgiou:
A Dual-Sensing CMOS Array for Combined Impedance-pH Detection of DNA with Integrated Electric Field Manipulation. 1-5 - Qingliang Liu, Jiabao Gao, Jinmei Lai:
TCP-Net: Minimizing Operation Counts of Binarized Neural Network Inference. 1-5 - Mineo Kaneko:
Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization. 1-5 - Kalpeshkumar Ranipa, Wei-Ping Zhu, M. N. S. Swamy:
Multimodal CNN Fusion Architecture with Multi-Features for Heart Sound Classification. 1-5 - Mohammadhossein Bahari, Seyedramin Rasoulinezhad, Mahdi Amiri, Farzam Gilani, Saeed Saadatnejad, Seyed Alireza Nezamalhosseini, Mahdi Shabany:
Modified Joint Channel-and-Data Estimation for One-Bit Massive MIMO. 1-5 - Yi Wang, Marc Stöttinger, Yajun Ha:
A Fault Resistant AES via Input-Output Differential Tables with DPA Awareness. 1-5 - Faheem Ullah Khan, Shahid Mehmood, Xiaojin Zhao, Yatao Yang, Xiaofang Pan:
Ultra-Sensitive Bimetallic Alloy Loaded with Porous Architecture MOF for Ammonia Detection at Room Temperature. 1-5 - Christian Hoyer, Dimitrios A. Prousalis, Lucas Wetzel, Rabia Fatima Riaz, Jens Wagner, Frank Jülicher, Frank Ellinger:
Mutual Synchronization with 24 GHz Oscillators. 1-5 - TaiYu Cheng, Masanori Hashimoto:
Minimizing Energy of DNN Training with Adaptive Bit-Width and Voltage Scaling. 1-5 - Yunbo Huang, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation, Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset. 1-4 - Michele Martemucci, Benedikt Kersting, Riduan Khaddam-Aljameh, Irem Boybat, S. R. Nandakumar, Urs Egger, Matthew BrightSky, Robert L. Bruce, Manuel Le Gallo, Abu Sebastian:
Accurate Weight Mapping in a Multi-Memristive Synaptic Unit. 1-5 - Daler N. Rakhmatov:
Stratified-Medium Plane-Wave Ultrasound Image Reconstruction via Frequency-Domain Migration. 1-5 - Fengshi Tian, Jie Yang, Shiqi Zhao, Mohamad Sawan:
A New Neuromorphic Computing Approach for Epileptic Seizure Prediction. 1-5 - Chua-Chin Wang, Chia-Yi Huang, Chia-Hung Yeh:
SRAM-Based Computation in Memory Architecture to Realize Single Command of Add-Multiply Operation and Multifunction. 1-4 - Mehrnaz Ahmadi, Lihong Zhang:
Analog Layout Placement for FinFET Technology Using Reinforcement Learning. 1-5 - Najmehossadat Nourieh, Yichuang Sun, Oluyomi Simpson:
A Step-Down ZVS Power Converter with Self-Driven Synchronous Rectifier. 1-5 - Xiaying Wang, Tibor Schneider, Michael Hersche, Lukas Cavigelli, Luca Benini:
Mixed-Precision Quantization and Parallel Implementation of Multispectral Riemannian Classification for Brain-Machine Interfaces. 1-5 - Tan Huang, Sih-Sian Wu, Jan Klopp, Po-Hsiang Yu, Liang-Gee Chen:
A Computational Efficient Architecture for Extremely Sparse Stereo Network. 1-5 - Taciano A. Rodolfo, Marcos L. L. Sartori, Matheus T. Moreira, Ney Laert Vilar Calazans:
Quasi Delay Insensitive FIFOs: Design Choices Exploration and Comparison. 1-5 - Ting Zou, Qian Zhao, Zhihai Rong, Jiasheng Hao:
Strategies Memorizing More Rounds May Promote the Emergence of Cooperation in Stochastic Games. 1-5 - Mohamed O. Abouzeid, Tawfiq Musah:
Hysteretic Error Extraction in Multi-Level Wireline Receivers. 1-5 - Dong-Jick Min, Jae Hoon Shim:
A Zero-Crossing-Based Integrator with Bidirectional Two-Phase Charging and Selective-Reset Operations for ΔΣ ADCs. 1-5 - Rohit B. Chaurasiya, Rahul Shrestha:
Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network. 1-5 - Shuguo Li, Wenbo Guo:
Area-Efficient Modular Reduction Structure and Memory Access Scheme for NTT. 1-5 - Jou Won Song, Ye In Park, Jong-Ju Hong, Seonggyun Kim, Suk-Ju Kang:
Attention-Based Bidirectional LSTM-CNN Model for Remaining Useful Life Estimation. 1-5 - Hyunkyu Park, Jihwan Park, Jae-Whan Lee, Yong-Un Jeong, Shin-Hyun Jeong, Suhwan Kim, Joo-Hyung Chae:
A High-Accuracy and Fast-Correction Quadrature Signal Corrector Using an Adaptive Delay Gain Controller for Memory Interfaces. 1-5 - Pham Minh Dung, Ching-Hwa Cheng, Don-Gey Liu:
An Intelligent Image-Based Force Sensing System Development to Assist Robot-Arm Surgery. 1-5 - Tatsuki Ono, Song Bian, Takashi Sato:
Automatic Parallelism Tuning for Module Learning with Errors Based Post-Quantum Key Exchanges on GPUs. 1-5 - Fredy Solis, Damián A. Morero, Mario R. Hueda, Benjamín T. Reyes:
Experimental Evaluation of Backpropagation-Based Background Compensation of TI-ADC with Application to Digital Communication Receivers. 1-5 - Jinming Zhang, Lifu Cheng, Cen Li, Yongfu Li, Guanghui He, Ningyi Xu, Yong Lian:
A Low-Latency FPGA Implementation for Real-Time Object Detection. 1-5 - Solomon Michael Serunjogi, Mahmoud Rasras, Mihai Sanduleanu:
64Gb/s NRZ/PAM4 Burst-Mode Optical Receiver Frontend with Gain Control, Offset Correction and Gain Decoupled from Bandwidth. 1-4 - Sebastian Linnhoff, Erik Sippel, Frowin Buballa, Michael Reinhold, Martin Vossiek, Friedel Gerfers:
A 12 Bit 8 GS/s Randomly-Time-Interleaved SAR ADC with Adaptive Mismatch Correction. 1-4 - Dong-Hyun Seo, Mayukh Nath, Debayan Das, Baibhab Chatterjee, Santosh Ghosh, Shreyas Sen:
PG-CAS: Patterned-Ground Co-Planar Capacitive Asymmetry Sensing for mm-Range EM Side-Channel Attack Probe Detection. 1-5 - Iosif-Angelos Fyrigos, Theodoros Panagiotis Chatzinikolaou, Vasileios G. Ntinas, Nikolaos Vasileiadis, Panagiotis Dimitrakis, Ioannis Karafyllidis, Georgios Ch. Sirakoulis:
Memristor Crossbar Design Framework for Quantum Computing. 1-5 - Miguel A. Prada-Delgado, Gero Dittmann, Ilie Circiumaru, Jens Jelitto:
A Blockchain-Based Crypto-Anchor Platform for Interoperable Product Authentication. 1-5 - Amad Ul Hassen, Fahad Ahmed Khan:
An Adaptive Metric for Node Substitution-Based BDD Minimization. 1-5 - Wonjoo Kim, Dirk J. Wouters, Rainer Waser, Vikas Rana:
Tuning the Memory Window of TaOx ReRAM Using the RF Sputtering Power. 1-5 - Woojune Park, Jung Hee Kim, Suk-Ju Kang, Joonsoo Kim, Kugjin Yun, Won-Sik Cheong:
Structured Camera Pose Estimation for Mosaic-Based Omnidirectional Imaging. 1-5 - Nikolaos Vasileiadis, Vasileios G. Ntinas, Iosif-Angelos Fyrigos, Rafailia-Eleni Karamani, Vassilios Ioannou-Sougleridis, Pascal Normand, Ioannis Karafyllidis, Georgios Ch. Sirakoulis, Panagiotis Dimitrakis:
A New 1P1R Image Sensor with In-Memory Computing Properties Based on Silicon Nitride Devices. 1-5 - Alvaro Velasquez, Sumit Kumar Jha, Rickard Ewetz, Susmit Jha:
Automated Synthesis of Quantum Circuits Using Symbolic Abstractions and Decision Procedures. 1-5 - Cheng-Jie Yang, Wei-Chih Li, Meng-Teen Wan, Wai-Chi Fang:
Real-Time EEG-Based Affective Computing Using On-Chip Learning Long-Term Recurrent Convolutional Network. 1-5 - Chuang Bi, Hong Ou, Qingzhou Kang, Rongdong Li, Lin Cheng:
A Novel Driver Circuit on Crosstalk Suppression in SiC MOSFETs. 1-5 - Son H. Nguyen, Heather Richardson, Rajeevan Amirtharajah:
A Bias-Flip Interface and Dual-Input DC-DC Converter for Piezoelectric and RF Energy Harvesting. 1-5 - Huang Ju, Xiaofeng Huang, Guoqing Xiang, Yuan Li, Huizhu Jia, Xiaodong Xie:
Hardware-Friendly Coding Unit Decision Scheme for HEVC. 1-5 - Ziwang Luo, David B. H. Tay, Xiaoping Lai, Zhiping Lin:
Design of Orthogonal Wavelet Filters with Minimum RMS Bandwidth Using A Symbolic Approach. 1-5 - Xuechen Liu, Md. Sahidullah, Tomi Kinnunen:
Learnable MFCCs for Speaker Verification. 1-5 - Peilong Feng, Timothy G. Constandinou:
Autonomous Wireless System for Robust and Efficient Inductive Power Transmission to Multi-Node Implants. 1-5 - Payam Heydari:
Noise Analysis of Passive Sampling Mixers Using Auto- and Cross-Correlation Functions. 1-5 - Zhonghao Zhang, Yangyang Jiang, Xingyu Cao, Xue Yang, Ce Zhu, Ying Li, Yipeng Liu:
Deep Learning Based Gait Analysis for Contactless Dementia Detection System from Video Camera. 1-5 - Gordon W. Roberts:
Single-Loop Feedback Parameter Extraction Method for Stability Analysis of Electronic Circuits. 1-4 - Nicolas Fahier, Cheng-Jie Yang, Wai-Chi Fang:
Live Demonstration: ECG-PPG Wearable Cardiovascular Monitoring System Design Using Human Body Communication. 1 - Peng Chen, Stefan Andersson, Sten E. Gunnarsson, Henrik Sjöland:
Analysis and Design of an 1-20 GHz Track and Hold Circuit. 1-5 - Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si, Meng-Fan Chang, Qiang Li:
A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. 1-5 - Joonhyuk Cho, Wanyeong Jung:
RectBoost: Start-Up Boosting for Rectenna Using an Adaptive Matching Network. 1-5 - Xichuan Zhou, Zhenghua Zhou, Zhengqing Zhong, Jianyi Yu, Tengxiao Wang, Min Tian, Ying Jiang, Cong Shi:
A Heterogeneous Spiking Neural Network for Computationally Efficient Face Recognition. 1-5 - Nguyen Cong Dao, Dirk Koch:
Memristor-Based Pass Gate for FPGA Programmable Routing Switch. 1-5 - Linglong Gao, Li Teng, Junrui Liang, Jianping Guo:
A Switched-Mode Time-Sharing Solution for Piezoelectric Energy Harvesting and Vibration Sensing. 1-5 - Zhiqi Zhu, Benjamin Carrión Schäfer:
Reducing the Complexity of Fault-Tolerant System Amenable to Approximate Computing. 1-5 - Xichen Li, Fucheng Yin, Jacques Christophe Rudell:
Effects of Receiver Input Impedance on Nonlinear Distortion in Full-Duplex Radios. 1-5 - Mingxuan Liang, Jilin Zhang, Hong Chen:
A 1.13μJ/Classification Spiking Neural Network Accelerator with a Single-Spike Neuron Model and Sparse Weights. 1-5 - Sebastian Pointner, Sven Wenzek, Robert Wille:
SMT-Based Placement for System-on-Chip Design. 1-5 - Xingyu Meng, Rakibul Hassan, Sai Manoj Pudukotai Dinakarrao, Kanad Basu:
Can Overclocking Detect Hardware Trojans? 1-5 - Nestor Cuevas, Elkim Roa, Stefano Stanzione, Nick Van Helleputte, Bogdan C. Raducanu:
Modeling and Characterization of Intra-Body Links for a Smart Contact Lens. 1-5 - Zihan Wu, Yuxiao Zhao, Yanfei Sun, Hao Min, Na Yan:
A Self-Bias Rectifier with 27.6% PCE at -30dBm for RF Energy Harvesting. 1-5 - Robert Guirado, Akshay Jain, Sergi Abadal, Eduard Alarcón:
Characterizing the Communication Requirements of GNN Accelerators: A Model-Based Approach. 1-5 - Hongchang Long, Jietao Diao, Xi Zhu, Zhiwei Li, Haijun Liu:
Logic Implementation Based on Double Memristors. 1-5 - Guoqing Wu, Yan Huang, Chen Zhu, Li Song, Wenjun Zhang:
SVM Based Fast CU Partitioning Algorithm for VVC Intra Coding. 1-5 - Josep Angel Oltra, Jordi Madrenas, Mireya Zapata, Bernardo Vallejo Mancero, Diana Mata-Hernandez, Shigeo Sato:
Hardware-Software Co-Design for Efficient and Scalable Real-Time Emulation of SNNs on the Edge. 1-5 - Anastasios Vilouras, Ravinder Dahiya:
Ultra-Thin Chips with Current-Mode ISFET Array for Continuous Monitoring of Body Fluids pH. 1-5 - MohammadHossein AskariHemmat, Olexa Bilaniuk, Sean Wagner, Yvon Savaria, Jean-Pierre David:
RISC-V Barrel Processor for Deep Neural Network Acceleration. 1-5 - Alessio Di Pasquo, Claudio Nani, Enrico Monaco, Luca Fanucci:
A High Linearity Driver with Embedded Interleaved Track-and-Hold Array for High-Speed ADC. 1-5 - Danying Wang, Wenjie Zhu, Yingzhan Xu, Yiling Xu, Le Yang:
Visual Quality Optimization for View-Dependent Point Cloud Compression. 1-5 - Edwin Arkel Rios, Chih-Chieh Lai, Bo-Rong Yan, Bo-Cheng Lai:
Parametric Study of Performance of Remote Photopletysmography System. 1-4 - Kristian Fischer, Christian Blum, Christian Herglotz, André Kaup:
Robust Deep Neural Object Detection and Segmentation for Automotive Driving Scenario with Compressed Image Data. 1-5 - Konstantinos Maragos, George Lentaris, Dimitrios Soudris:
A PVT-Aware Voltage Scaling Method for Energy Efficient FPGAs. 1-5 - Guozhu Xin, Yifan Zhao, Jun Han:
A Multi-Layer Parallel Hardware Architecture for Homomorphic Computation in Machine Learning. 1-5 - Zhiguo Tong, Peng Cao, Peng Xu, Dehong Lv, Danzhu Lu, Jie He, Zhiliang Hong:
A Charge-Pump-Based SIMO Buck-Boost DC-DC Converter with Three Operation Modes. 1-4 - Ioannis Kouretas, Vassilis Paliouras:
Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference. 1-5 - Ville Yli-Mäyry, Akira Ito, Naofumi Homma, Shivam Bhasin, Dirmanto Jap:
Extraction of Binarized Neural Network Architecture and Secret Parameters Using Side-Channel Information. 1-5 - Jiyong Woo:
Device Engineering Strategy of Zr-Doped HfOx Ferroelectric Memory for Unconventional Computing Applications. 1-4 - Bojun Hu, Sanfeng Zhang, Xiong Zhou, Xiangxin Pan, Zhaoming Ding, Qiang Li:
A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs. 1-4 - Mohamed Faragalla, Wolfgang H. Krautschneider, Matthias Kuhl:
Low-Leakage Differential-Drive Rectifier as 13.56 MHz Inductive Energy Harvester for Deep Medical Implants with Field Exposure Compliance. 1-5 - Plinio Finkenauer, Henrique Kessler, Rafael Iankowski Soares, Vinícius V. Camargo:
Evaluating the Impact of BTI on Hiding Countermeasures for DPA and DEMA Attacks. 1-5 - Junjun Zou, Qi Wei, Bin Zhou, Xiang Li, Chunge Ju, Rong Zhang, Zhiyong Chen:
A 442.1 nVpp, 13.07 ppm/°C Ultra-Low Noise Bandgap Reference Circuit in 180 nm BCD Process. 1-4 - Ana Mitrovic, Eby G. Friedman:
MTJ-Based Dithering for Stochastic Analog-to-Digital Conversion. 1-5 - Oguzhan Oezdamar, Robert Weigel, Amelie Hagelauer, Valentyn Solomko:
An Integrated Circuit for Decoupling and Tuning of Inverted-F Antennas in Cellular User Equipment. 1-4 - Haibing Lu, Xi Chen, Jiangpeng Dai, Bin Wu, Yi Fang, Michele Samorani, Zhen Li:
Game Theoretic Approach to Extreme Fast Charging Location. 1-5 - Sheng Zhang, Wei Xing Zheng:
Performance Analysis of Compressive Diffusion Normalized LMS Algorithm with Link Noises. 1-5 - Shuo Xie, Junyao Tang, Cheng Huang:
A 94.1% Efficiency 20-180W GaN-Based Full-Bridge Wireless Power Receiver for High-Power Wireless Chargers. 1-4 - Doojin Jang, Unbong Lee, Jeongmyeong Kim, Jangwon Suh, Wanyeong Jung:
An On-Chip Dual-Output Switched-Capacitor DC- DC Converter with Fine-Grained Output Control. 1-5 - Haoyu Zhuang, He Tang, Xizhu Peng, Yuefeng Li:
A Back-Gate-Input Clocked Comparator with Improved Speed and Reduced Noise in 22-nm SOI CMOS. 1-5 - Ryan Reed, Fariborz Lohrabi Pour, Dong Sam Ha:
An Energy Efficient RF Backscatter Modulator for IoT Applications. 1-5 - Diogo Brito, João Silva, Gonçalo Rodrigues, António Pinto, Jorge R. Fernandes, Taimur Gibran Rabuske:
An On-Chip Clock Generation Circuit for Smart Catheters. 1-5 - Alireza Esmaeilzehi, M. Omair Ahmad, M. N. S. Swamy:
MISNet: Multi-Resolution Level Feature Interpolating Ultralight-Weight Residual Image Super Resolution Network. 1-5 - Savath Saypadith, Takao Onoye:
Video Anomaly Detection Based on Deep Generative Network. 1-5 - Francesca Romana Cavallo, Khalid B. Mirza, Sara de Mateo, Jesus Rodriguez-Manzano, Konstantin Nikolic, Christofer Toumazou:
A Point-of-Care Device for Sensitive Protein Quantification. 1-5 - Brady Taylor, Amar Shrestha, Qinru Qiu, Hai Helen Li:
1S1R-Based Stable Learning through Single-Spike-Encoded Spike-Timing-Dependent Plasticity. 1-5 - Pavlos Athanasiadis, Marios Neofytou, Marcello Ganzerli, Georgi I. Radulov, Kostas Doris:
Time Interleaved ADC Mismatch Error Correction Technique in I/Q Digital Beamforming Receivers. 1-5 - Rongfeng Xu, Zenan Zeng, Run Chen, Zhenqi Chen, Yonggang Chen, Zhijian Chen, Zhijian Li, Zhaohui Wu, Bin Li:
A PVT-Insensitive Capacitance-to-Digital Converter Using Ring-Based Time-Domain Quantizer. 1-5 - Salinna Abdullah, Majid Zamani, Andreas Demosthenous:
A Discrete Wavelet Transform-Based Voice Activity Detection and Noise Classification with Sub-Band Selection. 1-5 - Mostafa Amer, Ahmed Abuelnasr, Ahmed Ragab, Ahmad Hassan, Mohamed Ali, Benoit Gosselin, Mohamad Sawan, Yvon Savaria:
Design and Analysis of Combined Input-Voltage Feedforward and PI Controllers for the Buck Converter. 1-5 - Haikang Diao, Chen Chen, Wei Chen, Wei Yuan, Amara Amara:
Unobtrusive Smart Mat System for Sleep Posture Recognition. 1-5 - Oliver Ploder, Christian Motz, Thomas Paireder, Christina Auer, Harald Pretl, Mario Huemer:
Digitally Intensive Mixed-Signal Approach for Self-Interference Cancellation in LTE-A/5G-Transceivers. 1-5 - Xinyu Qin, Jingying Zhang, Liang Qi, Sai-Weng Sin, Rui Paulo Martins, Guoxing Wang:
Discrete-Time MASH Delta-Sigma Modulator with Second-Order Digital Noise Coupling for Wideband High-Resolution Applications. 1-5 - Chongguang Yao, Qiang Liu, Linan Wang, Qingye Zhang, Honghui Tang, Maoshen Zhang:
Lightweight and Configurable Synchronizer and Demodulator Design for PDSCH on FPGA. 1-5 - Matheus B. R. Cardoso, Samuel S. da Silva, Lucas Giovanni Nardo, Roberto M. Passos, Erivelton G. Nepomuceno, Janier Arias-Garcia:
A New PRNG Hardware Architecture Based on an Exponential Chaotic Map. 1-5 - Cheng Han, Jingna Mao, Xuedi Wang, Shan Yu, Zhiwei Zhang:
Body Channel Based Wireless Power Transfer Method for Implantable Bioelectronics. 1-5 - Seung-Hwan Bae, Hyuk-Jae Lee, Hyun Kim:
Cache Compression with Golomb-Rice Code and Quantization for Convolutional Neural Networks. 1-5 - Odilbek Urmonov, HyungWon Kim:
Multi-Agent Deep Reinforcement Learning Based Distributed Resource Allocation. 1-5 - Kengo Nakata, Daisuke Miyashita, Jun Deguchi, Ryuichi Fujimoto:
Adaptive Quantization Method for CNN with Computational-Complexity-Aware Regularization. 1-5 - Abdelrahman Emad, H. Mohamed, Abdulrahman Farid, Mohamed Hassan, Rawan Sayed, Hassan Aboushady, Hassan Mostafa:
Deep Learning Modulation Recognition for RF Spectrum Monitoring. 1-5 - Shanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu:
Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip Cloning. 1-5 - Christoph Ossimitz, Nima Taherinejad:
A Fast Line Segment Detector Using Approximate Computing. 1-5 - Hiroki Sato, Shigetaka Takagi:
Reduction on Power Dissipation of Filters Based on Local-Feedback Amplifier. 1-5 - Muhammad Asfandyar Awan, Bo Wang, Nasir Abdul Quadir, Amine Bermak:
Review and Analysis of CMOS Current Readout Circuits for Biosensing Applications. 1-5 - Lei Kuang, Junming Zeng, Pantelis Georgiou:
A USB 3.0 High Speed Digital Readout System with Dynamic Frame Rate Processing for ISFET Lab-on-Chip Platforms. 1-5 - Brunno A. Abreu, Augusto Andre Souza Berndt, Isac de Souza Campos, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi:
Fast Logic Optimization Using Decision Trees. 1-5 - Vishal Sharma, Ju Eon Kim, Yong-Jun Jo, Yuzong Chen, Tony Tae-Hyoung Kim:
AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing. 1-5 - Sudarsan Sadasivuni, Rahul Chowdhury, Vinay Elkoori Ghantala Karnam, Imon Banerjee, Arindam Sanyal:
Recurrent Neural Network Circuit for Automated Detection of Atrial Fibrillation from Raw ECG. 1-5 - Qinyu Chen, Bodo Rueckauer, Li Li, Tobi Delbruck, Shih-Chii Liu:
Reducing Latency in a Converted Spiking Video Segmentation Network. 1-5 - Zihan Zhou, Qinghan Lai, Shuai Ding, Song Liu:
Joint 2D Object Detection and 3D Reconstruction via Adversarial Fusion Mesh R-CNN. 1-5 - Karolos-Alexandros Tsakalos, Vasileios G. Ntinas, Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, Theodoros Panagiotis Chatzinikolaou, Nikolaos Vasileiadis, Panagiotis Dimitrakis, Astero Provata, Georgios Ch. Sirakoulis:
Emergence of Chimera States with Re-Programmable Memristor Crossbar Arrays. 1-5 - Linfang Wang, Wang Ye, Junjie An, Chunmeng Dou, Qi Liu, Meng-Fan Chang, Ming Liu:
Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory. 1-4 - Zexin Yuan, Lei Zhang, Yan Wang:
A K-Band Fractional-N PLL with Low-Spur Low-Power Linearization Circuit and PVT Robust Spur Trapper. 1-5 - Jason Kamran Eshraghian, Kyoungrok Cho, Sung Mo Kang:
A 3-D Reconfigurable RRAM Crossbar Inference Engine. 1-5 - Yousef Safari, Boris Vaisband:
Power Delivery for Silicon Interconnect Fabric. 1-5 - Liangbo Lei, Cong Tao, Zhiliang Hong, Yumei Huang:
A 5.7mW +30dBm IIP3, Tunable Active-RC LPF in 40nm CMOS. 1-4 - Xiangling Ding, Yifeng Pan, Kui Luo, Yanming Huang, Junlin Ouyang, Gaobo Yang:
Localization of Deep Video Inpainting Based on Spatiotemporal Convolution and Refinement Network. 1-5 - Jiachen Xu, Ethan Chen, Vanessa Chen:
Energy-Efficient Data Symbol Detection via Boosted Learning for Multi-Actuator Data Storage Systems. 1-5 - Cipriano Rey Hipolito, Angelito A. Silverio, Renan Nuestro:
High PSR LDO with Adaptive-EFFRC for Wearable Biomedical Application. 1-5 - Davide del Giudice, Federico Bizzarri, Daniele Linaro, Angelo Brambilla:
Stability Analysis of MMC/MTDC Systems Considering DC-Link Dynamics. 1-5 - Xinmiao Zhang, Yok Jye Tang:
Low-Complexity Parallel Cyclic Redundancy Check. 1-5 - Yu Wu, Dai Jiang, Nazanin Neshatvar, Andreas Demosthenous:
A Power Efficient Time-to-Current Stimulator for Vagal-Cardiac Connection after Heart Transplantation. 1-4 - Jian Xian Soo, Yue Zheng, Chip-Hong Chang:
Live Demonstration: Event-Driven Physical Unclonable Function for Proactive Monitoring System by Dynamic Vision Sensor. 1 - Van Ha Nguyen, Nam Ly, Abdul Hafiz Alameh, Yves Blaquière, Glenn E. R. Cowan:
Compact and Low-Power Under-Voltage Lockout and Thermal-Shutdown Protection Circuits Using a Novel Low-Iq All-in-One Bandgap Comparator. 1-5 - Mohammad Usaid Abbasi:
A Chopped Ultra-Low-Power, Low-Noise Wearable EEG Amplifier with Pseudo-Resistor Calibration. 1-5 - Yiheng Gao, Benjamin Carrión Schäfer:
Effective High-Level Synthesis Design Space Exploration through a Novel Cost Function Formulation. 1-5 - Edouard Giacomin, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow. 1-5 - Jorge Torres Gómez, Liset Martinez Marrero, Matthias Koepp, Rajesh Kumar Sharma:
Impact of Quantization Noise Errors in FPGA Based WLAN Timing Synchronization with the Schmidl and Cox Algorithm. 1-5 - Jing Li, Jiping Li, Jianyu Zhang, Yu He, Qiuzhen Xu, Pengda Qu, Weibo Hu, Zhiming Xiao:
An Adaptively Biased LDO Regulator with 11nA Quiescent Current and 50mA Available Load. 1-5 - Alejandro Suanes, Lluís Terés, Michele Dei, Francisco Serra-Graells:
A 0.8mW 50kHz 94.6dB-SNDR Bootstrapping-Free SC Delta-Sigma Modulator ADC with Flicker Noise Cancellation. 1-5 - Nueraimaiti Aimaier, Nam Ly, Gabriel Nobert, Yves Blaquière, Nicolas G. Constantin, Glenn E. R. Cowan:
SHEPWM Class-D Amplifier with a Reconfigurable Gate Driver Integrated Circuit. 1-5 - Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx:
Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation. 1-5 - Mousa Karimi, Mohamed Ali, Ahmad Hassan, Mohamad Sawan, Benoit Gosselin:
A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications. 1-5 - Sebastiaan Scholten, Danny Merkx, Odette Scharenborg:
Learning to Recognise Words Using Visually Grounded Speech. 1-5 - Hassan Aboushady, Alhassan Sayed, Luis A. Camuñas-Mesa, José M. de la Rosa:
Cognitive Radio Circuits and Systems - Application to Digitizers. 1-5 - Thi-Nhan Pham, Kien Trinh Quang, Ik-Joon Chang, Massimo Alioto:
STT-MRAM Architecture with Parallel Accumulator for In-Memory Binary Neural Networks. 1-5 - Guanglai Wu, Yi Zhang, Lin He, Diyang Gao, Yang Liu, Yufeng Guo, Hao Gao:
A 77 GHz Power Amplifier Design with in-Phase Power Combing for 20 dBm Psat in a 40-nm CMOS Technology. 1-4 - Mahmood A. Mohammed, Gordon W. Roberts:
A Scalable Many-Stage CMOS OTA for Closed-Loop Applications. 1-5 - Lucas Ferreira, Steffen Malkowsky, Patrik Persson, Karl Åström, Liang Liu:
Reconfigurable Multi-Access Pattern Vector Memory for Real-Time ORB Feature Extraction. 1-5 - Prabal Bhatnagar, Pydi Ganga Bahubalindruni, Pedro Barquinha:
Low-Power High Sensitive Capacitance Read-Out Circuit Using a-InGaZnO TFTs. 1-5 - Tsung-Kang Hung, Sachin K. Kaushal, Hsu-Feng Hsiao:
Content Distribution Network for Streaming Using Multiple Galois Fields. 1-5 - David Zagouri, Joseph Shor:
A Subthreshold Voltage Reference with Coarse- Fine Voltage Trimming. 1-4 - Chang Liu, Chun Zhao, Chuanjin Richard Shi:
A Fully-Synthesizable Fast-Response Digital LDO Using Automatic Offset Control and Reuse. 1-5 - Zekun Yang, Pei Yang, Xiumei Yin, Xueqing Li, Huazhong Yang:
Reducing Signal Swing Overheads to Only 8% in Background 3rd-Order Inter-Stage Gain Error Calibration for Pipeline ADCs. 1-5 - Nishtha Wadhwa, Pydi Bahubalindruni, Ana Correia, João Goes, Sujay Deb, Pedro Barquinha:
Mostly Passive Δ - Σ ADC with a-IGZO TFTs for Flexible Electronics. 1-6 - Xuewen Zhang, Wenxin Yu, Ning Jiang, Yunye Zhang, Zhiqiang Zhang:
SPS: A Subjective Perception Score for Text-to-Image Synthesis. 1-5 - Setareh Behroozi, Yao Yao, Hoeseok Yang, Younghyun Kim:
Scheduling of Iterative Computing Hardware Units for Accuracy and Energy Efficiency. 1-5 - Rongni Yang, Wei Xing Zheng:
Event-Driven Sliding Mode Control of Discrete-Time 2-D Roesser Systems. 1-5 - Jeffin Joy, Swetha Clara Jose, Vijaya Kumar Kanchetla, Shubham Jain, Rajesh H. Zele:
A High-Gain Low-Offset Baseband Design for Multi-Standard Navigation Receivers. 1-5 - Gianluca Zoppo, Francesco Marrone, Fernando Corinto:
Local Learning in Memristive Neural Networks for Pattern Reconstruction. 1-5 - Abdelrahman Elabany, Amin M. Nassar, Hassan Mostafa:
Design Optimization of Multi-Input Reconfigurable Capacitive DC-DC Converters: A CAD Tool Approach. 1-5 - Yangtao Dong, Chirn Chye Boon, Kaituo Yang, Ao Zhou, Xin Ding:
A Cross-Coupled Pair Regeneration Based dB-Linear Programable Gain Amplifier with THD Enhancement. 1-5 - Maria Rivola, Pietro Ibba, Paolo Lugli, Luisa Petti:
Bioimpedance Data Statistical Modelling for Food Quality Classification and Prediction. 1-5 - Huapin Chen, Lei Zhang, Yan Wang:
A 2.8 nV/√ Hz Chopper Amplifier for Bridge Readout with Dual Ripple Reduction and Noise- Nonlinearity -Cancelling Loop. 1-4 - Ícaro Siqueira, Guilherme Corrêa, Mateus Grellert:
Complexity and Coding Efficiency Assessment of the Versatile Video Coding Standard. 1-5 - Kai Tang, Chuanshi Yang, Zhongyuan Fang, Wensong Wang, Nan Wang, Yao Zhu, Eldwin Jiaqiang Ng, Chun-Huat Heng, Yuanjin Zheng:
A 75.3 pJ/b Ultra-Low Power MEMS-Based FSK Transmitter in ISM-915 MHz Band for Pico-IoT Applications. 1-4 - Cheng-Lin Lee, Yi-Ta Chen, An-Yeu Wu:
A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification. 1-5 - Hao Zhang, Jieyu Li, Weifeng He, Yanan Sun, Mingoo Seok:
An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM. 1-5 - Jiawen Hu, Yu Zhou:
A Buck Converter for 5G NR RF-PA with 400ns Rise- and Fall-Time and Spread Spectrum Switching. 1-4 - Jialong Liu, Wenjun Tang, Yongpan Liu, Huazhong Yang, Xueqing Li:
Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing. 1-5 - Hui Chen, Ruiqi Wu, Zhonghai Lu, Yuxiang Fu, Li Li, Zongguang Yu:
A General Methodology and Architecture for Arbitrary Complex Number Nth Root Computation. 1-5 - Junming Zeng, Pantelis Georgiou:
A 1000fps Programmable Gain CMOS ISFET SoC with Array-Level Offset Compensation for Real Time Ion Imaging. 1-5 - Donghyeok Cho, Nahmil Koo, Taekwang Jang, SeongHwan Cho:
An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction. 1-5 - Hang-Ting Lue, Han-Wen Hu, Tzu-Hsuan Hsu, Po-Kai Hsu, Keh-Chung Wang, Chih-Yuan Lu:
Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. 1-4 - Lidan Wang, Chenchang Zhan, Jie Lin, Shuangxing Zhao, Nian Zhang:
A 0.9-V 22.7-ppm/°C Sub-Bandgap Voltage Reference with Single BJT and Two Resistors. 1-4 - Adithya Krishna, Chetan Singh Thakur:
Bayesian Source Localization Using Stochastic Computation. 5 - Zhouchen Ma, Cheng Chen, Min Wang, Yang Zhao, Liang Ying, Guoxing Wang, Jian Zhao:
A Low-Power Heart Rate Sensor with Adaptive Heartbeat Locked Loop. 1-5 - Yaxin Liu, Hongyi Liu, Sujie Chen, Chen Lin, Jian Zhao:
Omni-Directional Transistors: Enabling Tensile-Force-Resilient Operation for Flexible Circuits and Systems. 1-5 - Shantanu Mehta, Brendan Mullane, Vincent O'Brien, Roberto Pelliconi, Christophe Erdmann:
A Higher-Order Programmable Amplitude and Timing Error Shaping Bandpass DEM for Nyquist-Rate D/A Converters. 1-5 - Lorenzo Lamberti, Manuele Rusci, Marco Fariselli, Francesco Paci, Luca Benini:
Low-Power License Plate Detection and Recognition on a RISC-V Multi-Core MCU-Based Vision System. 1-5 - Yuzong Chen, Lu Lu, Yuncheng Lu, Tony Tae-Hyoung Kim:
A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory. 1-5 - Lizhen Zhang, Jianhui Wu:
Background Calibration in Pipelined SAR ADCs Exploiting PVT-Tracking Metastability Detector. 1-5 - Chris Andriakopoulos, Kleanthis Papachatzopoulos, Vassilis Paliouras:
A Novel Stochastic Polar Architecture for All-Digital Transmission. 1-5 - Boyang Zhang, Weixin Gai, Haowei Niu, Bingyi Ye, Kai Sheng, Tianjian Zuo, Lei Liu:
Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver. 1-5 - Ali Rida Ismail, Slavisa Jovanovic, Sébastien Petit-Watelot, Hassan Rabah:
Novel Reservoir Computing Approach for the Detection of Chaos. 1-5 - Ting Guo, Kai Tang, Yuanjin Zheng:
A 1GHz Configurable Chirp Modulation Direct Digital Frequency Synthesizer in 65nm CMOS. 1-4 - Hong Liu, Hong Guo, Wei Hu:
EEG-Based Emotion Classification Using Joint Adaptation Networks. 1-5 - Ilenia D'Adda, Gianfranco Battaglin, Marco Carminati:
A Low-Cost Flexible Pipe Sheath for Multi-Parameter Monitoring of Water Distribution. 1-5 - Zixiang Yang, Qing Shen, Wei Liu, Yonina C. Eldar, Wei Cui:
Extended Cantor Arrays with Hole-Free Fourth-Order Difference Co-Arrays. 1-5 - Taeju Lee, Mi Kyung Kim, Hyunjoo Jenny Lee, Minkyu Je:
A 5.7µW/Channel Folded-Current-Mirror-Based Reconfigurable Multimodal Neural Recording IC with Improved Hardware Availability. 1-4 - Conor Smyth, Guoxin Wang, Rajesh C. Panicker, Avishek Nag, Barry Cardiff, Deepu John:
Continuous User Authentication Using IoT Wearable Sensors. 1-5 - Ilya Kiselev, Shih-Chii Liu:
Event-Driven Local Gain Control on a Spiking Cochlea Sensor. 1-5 - Silin Lu, Lei Lu, Shengdong Zhang, Hailong Jiao:
A Pull-Up Adaptive Sense Amplifier Based on Dual-Gate IGZO TFTs. 1-5 - Huan Cai, Jialiang Tang, Yihan Wu, Min Xia, Gang He, Yangsong Zhang:
The Detection of Attentive Mental State Using a Mixed Neural Network Model. 1-5 - Lu Liu, Wei Xing Zheng, Shihong Ding:
Controller Design for High-Order Sliding Mode Dynamics with Upper-Triangular Uncertainties. 1-5 - Yimin Wang, Zhuo Zou, Lirong Zheng:
Design Framework for SRAM-Based Computing-In-Memory Edge CNN Accelerators. 1-5 - Priyank H. Prajapati, Anand D. Darji:
Two Stage Step-Size Scaler Adaptive Filter Design for ECG Denoising. 1-5 - Ahmed Magdy, Sameh Ibrahim, Ahmed H. Khalil, Hassan Mostafa:
Low Power, Dual Mode Bluetooth 5.1/Bluetooth Low Energy Receiver Design. 1-5 - Ali Dabbous, Michele Mastella, Natarajan A., Elisabetta Chicca, Maurizio Valle, Chiara Bartolozzi:
Artificial Bio-Inspired Tactile Receptive Fields for Edge Orientation Classification. 1-5 - Takeru Kurumizawa, Hirotaka Koizumi:
Voltage-Source Parallel Resonant Class E Oscillator. 1-5 - Jiaxi Zhang, Tao Yang, Qingzheng Li, Bo Zhou, Yang Yang, Guojie Luo, Jianping Shi:
An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode. 1-5 - Thomas Mittelholzer, Milos Stanisavljevic, Nikolaos Papandreou, Haralampos Pozidis:
High-Throughput ECC with Integrated Chipkill Protection for Nonvolatile Memory Arrays. 1-5 - Xi Zhang, Dong Liu, Chi K. Tse, Zhen Li:
Assessing the Vulnerability of Cyber-Coupled Power Systems to Component Failures. 1-5 - Taishin Shimada, Makoto Ikeda:
High-Throughput Polynomial Multiplier Architecture for Lattice-Based Cryptography. 1-5 - Panni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu:
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator. 1-4 - Sammy Cerida Rengifo, Francesco Chicco, Erwan Le Roux, Christian C. Enz:
Modulation Scheme Impact on Phase Noise in FMCW Radar for Short-Range Applications. 1-4 - Hamza Al Maharmeh, Nabil J. Sarhan, Chung-Chih Hung, Mohammed Ismail, Mohammad Alhawari:
A Comparative Analysis of Time-Domain and Digital-Domain Hardware Accelerators for Neural Networks. 1-5 - Jiawen Xue, Guolin Li, Zhihua Wang, Xiang Xie:
A Novel Stripe Extraction Scheme for the Multi-Line Structured Light Systems. 1-5 - Rajasekhar Nagulapalli, Rakesh Kumar Palani, Sweta Agarwal, Shouri Chatterjee, K. Hayatleh, S. Barker:
A 15uW, 12 ppm/°C Curvature Compensated Bandgap in 0.85V Supply. 1-4 - Gianluca Giustolisi, Gaetano Palumbo:
Design of Three-Stage OTAs from Settling-Time and Slew-Rate Constraints. 1-5 - Yongquan Shi, Yongshuai Sun, Jianfei Jiang, Guanghui He, Qin Wang, Naifeng Jing:
Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. 1-5 - Abhishek Pullela, Ashfakh Ali, Arpan Jain, Adithya Banthi, Zia Abbas:
A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems. 1-5 - Wei-Chih Lai, Tzu-Hsiang Hsu, Chih-Cheng Chen, Chih-Cheng Hsieh:
A 12-Bit SAR ADC with Reference Voltage Ripple Suppression. 1-4 - Chao Fang, Liulu He, Haonan Wang, Jinghe Wei, Zhongfeng Wang:
Accelerating 3D Convolutional Neural Networks Using 3D Fast Fourier Transform. 1-5 - Rihat Rahman, Shiva Maleki Varnosfaderani, Omar Makke, Nabil J. Sarhan, Eishi Asano, Aimee F. Luat, Mohammad Alhawari:
Comprehensive Analysis of EEG Datasets for Epileptic Seizure Prediction. 1-5 - Julian Büchel, Jonathan Kakon, Michel Perez, Giacomo Indiveri:
Implementing Efficient Balanced Networks with Mixed-Signal Spike-Based Learning Circuits. 1-5 - Ankita Ahuja, Komail M. H. Badami, Cédric Barbelenet, Stéphane Emery:
Comparison of Capacitive DAC Architectures for Power and Area Efficient SAR ADC Designs. 1-5 - Rami A. Alzahrani, Alice C. Parker:
Neuromorphic Autonomous Spiking Encoding. 1-5 - Yu Su, Haihua Shen, Renjie Lu, Yunying Ye:
A Stealthy Hardware Trojan Design and Corresponding Detection Method. 1-6 - Jing-Ping Wu, Yi-Chien Lin, Ying-Wei Wu, Shih-Wei Hsieh, Ching-Hsuan Tai, Yi-Chang Lu:
A Memory-Efficient Accelerator for DNA Sequence Alignment with Two-Piece Affine Gap Tracebacks. 1-4 - Ander Arriandiaga, Giovanni Morrone, Luca Pasa, Leonardo Badino, Chiara Bartolozzi:
Audio-Visual Target Speaker Enhancement on Multi-Talker Environment Using Event-Driven Cameras. 1-5 - Dong Wang, Zhengkun Shen, Xiaolei Su, Zexue Liu, Yi Tan, Chen Xu, Junhua Liu, Huailin Liao:
A Gm-Compensated 46-101 GHz Broadband Power Amplifier for High-Resolution FMCW Radars. 1-5 - Isaac Nelson, Ricardo S. Ferreira, José Augusto Miranda Nacif, Peter Jamieson:
Is It Time to Include High-Level Synthesis Design in Digital System Education for Undergraduate Computer Engineers? 1-5 - Yujie Wang, Daohuai Jiang, Feng Gao, Fei Gao:
Low-Cost Photoacoustic Tomography System Enabled by Frequency-Division Multiplexing. 1-5 - Julian Arenas, Juan Sebastian Moya, Elkim Roa:
A 15000 Tuning Range Scalable Feed-Forward Oscillator with 0.05mm2 Area in CMOS Standard-Cell Format. 1-4 - Zhenzhe Han, Francesca R. Cavallo, Konstantin Nikolic, Khalid B. Mirza, Christofer Toumazou:
Signal Identification of DNA Amplification Curves in Custom-PCR Platforms. 1-5 - Qirui Hua, Miguel Cacho-Soblechero, Pantelis Georgiou:
A Multi-Sensing ISFET Array for Simultaneous In-Pixel Detection of Light, Temperature, Moisture and Ions. 1-5 - Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große:
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. 1-5 - Wei Tu, Miguel Cacho-Soblechero, Dan Terracina, Paul H. Strutton, Pantelis Georgiou:
A 4-Channel sEMG ASIC with Real-Time Muscle Fatigue Feature Extraction. 1-5 - Milad Diba, Ahmad Beilouni, Emrah Kalemci, Ayhan Bozkurt:
A Programmable Low-Power, Low-Noise Front-End Channel in 0.35- µm CMOS for CdZnTe Detectors. 1-5 - Aditi Saluja, Arnab Mitra, Ankur Deshwal, Kavitha T. Madhu, Ujjawal Chugh, Seungwon Lee, Joonho Song:
Autotuning LSTM for Accelerated Execution on Edge. 1-5 - Ana Laura Gonzalez Rios, Kamila Bekshentayeva, Maheeppartap Singh, Soroush Haeri, Ljiljana Trajkovic:
Virtual Network Embedding for Switch-Centric Data Center Networks. 1-5 - Haoyu Zhuang, Qifu Cao, Xizhu Peng, He Tang:
A Bootstrapped Switch with Accelerated Rising Speed and Reduced On-Resistance. 1-5 - Ahmed Abuelnasr, Mostafa Amer, Ahmed Ragab, Benoit Gosselin, Yvon Savaria:
Causal Information Prediction for Analog Circuit Design Using Variable Selection Methods Based on Machine Learning. 1-5 - Kai Wang, Bengbeng He, Wei-Ping Zhu:
CAUNet: Context-Aware U-Net for Speech Enhancement in Time Domain. 1-5 - Anil Kumar Kumaran, Masoud Pashaeifar, Marco D'Avino, Leo C. N. de Vreede, Morteza S. Alavi:
On-Chip Output Stage Design for a Continuous Class-F Power Amplifier. 1-5 - Donghyun Youn, Minkyu Je:
A 67-pJ/Bit 435-MHz 16-QAM Modulator for Capsule Endoscopy System with 18-ns Start-Up Using Transient DC Error Correction. 1-5 - Md Farhadur Reza, Tung Thanh Le:
Reinforcement Learning Enabled Routing for High-Performance Networks-on-Chip. 1-5 - Diego Barrettino, Thomas Gisler, Christoph Zumbühl, Christian Di Battista, Raphaël Kummer, Markus Thalmann:
An IoT Sensing System for Remote Monitoring the Grain Moisture Content. 1-5 - Jincheol Sim, Hyunsu Park, Youngwook Kwon, Seongcheol Kim, Chulwoo Kim:
A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector. 1-4 - Fatemeh Kiani, Jun Yin, Zhongrui Wang, J. Joshua Yang, Qiangfei Xia:
All Hardware-Based Two-Layer Perceptron Implemented in Memristor Crossbar Arrays. 1-5 - Prasenjit Saha, Salman Ahmed, Hema Sai Kalluru, Zia Abbas:
Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence. 1-5 - Jinpeng Lu, Shuguo Li:
A Multibit Left-Shift Modular Inverse Hardware Algorithm and its Implementation. 1-5 - Rashi Dutt, Sayon Mondal, Amit Acharyya:
Single Channel Blind Source Separation Using Dual Extended Kalman Filter. 1-5 - Zhengyuan Zhang, Haoran Jin, Zesheng Zheng, Yunqi Luo, Yuanjin Zheng:
Photoacoustic Microscopy Imaging from Acoustic Resolution to Optical Resolution Enhancement with Deep Learning. 1-5 - Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni:
Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors. 1-5 - Yuyang Li, Yawen Wu, Xincheng Zhang, Ehab A. Hamed, Jingtong Hu, Inhee Lee:
Developing a Miniature Energy-Harvesting-Powered Edge Device with Multi-Exit Neural Network. 1-5 - Erika Covi, Quang T. Duong, Suzanne Lancaster, Viktor Havel, Jean Coignus, Justine Barbot, Ole Richter, Philipp Klein, Elisabetta Chicca, Laurent Grenouillet, Athanasios Dimoulas, Thomas Mikolajick, Stefan Slesazeck:
Ferroelectric Tunneling Junctions for Edge Computing. 1-5 - Peilin Yang, Fule Li, Zhihua Wang:
A 12-Bit 2-GS/s Pipelined ADC Front-End Stage with Aperture Error Tuning and Split MDAC. 1-5
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-06-27 18:37 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
