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ORCID21st DDECS 2018: Budapest, Hungary
- 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2018, Budapest, Hungary, April 25-27, 2018. IEEE 2018, ISBN 978-1-5386-5754-6
Poster Session 1
- Theodor Hillebrand, Ludwig Karsthof, Steffen Paul, Dagmar Peters-Drolshagen:
Reliability-Aware Multi-Vth Domain Digital Design Assessment. 1-4 - Lukás Kohútka
, Viera Stopjaková:
Heap Queue: A Novel Efficient Hardware Architecture of MIN/MAX Queues for Real-Time Systems. 5-8 - Yuanqing Li, Anselm Breitenreiter, Marko S. Andjelkovic, Oliver Schrape, Milos Krstic:
Flip-Flop SEUs Mitigation through Partial Hardening of Internal Latch and Adjustment of Clock Duty Cycle. 9-14 - Ondreg Novak:
Nonlinear Binary Codes and Their Utilization for Test. 15-20 - Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar:
Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. 21-26 - Dominik Macko:
Contribution to Automated Generating of System Power-Management Specification. 27-32 - Izel Cagin Odabasi, Mustafa Berke Yelten, Engin Afacan, I. Faik Baskaya, Ali Emre Pusane, Günhan Dündar:
A Rare Event Based Yield Estimation Methodology for Analog Circuits. 33-38
Session 1: Analog Design
- Seyed Hamid Fani, Ali Peiravi, Hooman Farkhani, Farshad Moradi:
A Novel TFET 8T-SRAM Cell with Improved Noise Margin and Stability. 39-44 - Daniel Arbet, Martin Kovác, Lukás Nagy, Viera Stopjaková, Michal Sovcik:
Two-Stage Bulk-Driven Variable Gain Amplifier for Low-Voltage Applications. 45-50 - Lukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Viera Stopjaková:
Design and Performance Analysis of Ultra-Low Voltage Rail-to-Rail Comparator in 130 nm CMOS Technology. 51-54
Session 2: System Design
- Amila Akagic, Emir Buza, Razija Turcinhodzic, Hana Haseljic, Hiroyuki Noda, Hideharu Amano:
Superpixel Accelerator for Computer Vision Applications on Arria 10 SoC. 55-60 - Kai Lehniger, Stefan Weidling, Mario Schölzel:
Heuristic for Page-Based Incremental Reprogramming of Wireless Sensor Nodes. 61-66 - Serhiy Avramenko, Siavoosh Payandeh Azad, Stefano Esposito, Behrad Niazmand, Massimo Violante, Jaan Raik, Maksim Jenihhin:
QoSinNoC: Analysis of QoS-Aware NoC Architectures for Mixed-Criticality Applications. 67-72
Session 3: Digital Circuit Test
- Alexander Sprenger, Sybille Hellebrand:
Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. 73-78 - Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen:
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. 79-84 - Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio:
On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. 85-90
Poster Session 2
- Giulio D'Amato, Giovanni Piccinni, Gianfranco Avitabile, Giuseppe Coviello, Claudio Talarico:
An Integrated Phase Shifting Frequency Synthesizer for Active Electronically Scanned Arrays. 91-94 - Sara Divanbeigi, Felix Winkler, Martin Bergen, Markus Olbrich:
Modeling and Accelerated Mixed-Signal Simulation of a Control System. 95-100 - David Lemma, Daniel Große, Rolf Drechsler:
Natural Language Based Power Domain Partitioning. 101-106 - Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio:
Synthesis of Finite State Machines on Memristor Crossbars. 107-112 - Szymon Reszewicz, Krzysztof Siwiec, Witold A. Pleskacz:
2.4 GHz LC-VCO with Improved Robustness against PVT Using FD-SOI Body Biasing Technique. 113-116 - Abraham Temesgen Tibebu, Görschwin Fey:
Augmenting All Solution SAT Solving for Circuits with Structural Information. 117-122 - Milan R. Dincic, Zoran H. Peric, Dragan B. Denic, Zoran Stamenkovic:
Design of Low-Bit Robust Analog-to-Digital Converters for Signals with Gaussian Distribution. 123-128
Session 4: Reconfigurability
- Riccardo Cantoro, Luigi San Paolo, Matteo Sonza Reorda, Giovanni Squillero:
An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test. 129-134 - Hassan Ebrahimi, Hans G. Kerkhoff:
Intermittent Resistance Fault Detection at Board Level. 135-140
Session 5: Reliability
- Florian Huemer, Thomas Polzer, Andreas Steininger:
Using a Duplex Time-to-Digital Converter for Metastability Characterization of an FPGA. 141-146 - Karl Janson, Carl Johann Treudler, Thomas Hollstein, Jaan Raik, Maksim Jenihhin, Görschwin Fey:
Software-Level TMR Approach for On-Board Data Processing in Space Applications. 147-152
Session 6: Student Papers
- Omar Farag, Mariam Mohamed, Mohamed A. Abd El-Ghany, Klaus Hofmann:
Integrated Sensors for Early Breast Cancer Diagnostics. 153-157 - Miroslav Potocný, Viera Stopjaková, Martin Kovác:
Self Vth-Compensating CMOS On-Chip Rectifier for Inductively Powered Implantable Medical Devices. 158-161 - Navaneetha Channiganathota Manjappa, Anselm Breitenreiter, Markus Ulbricht, Milos Krstic:
A Methodology to Verify Digital IP's within Mixed-Signal Systems. 162-165
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