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ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 27
Volume 27, Number 1, January 2019
- Scott Lerner
, Baris Taskin:
Slew Merging Region Propagation for Bounded Slew and Skew Clock Tree Synthesis. 1-10 - Ryuichi Enomoto, Tetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada:
A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration. 11-19 - Martin Omaña, Alessandro Fiore, Marco Mongitore, Cecilia Metra:
Fault-Tolerant Inverters for Reliable Photovoltaic Systems. 20-28 - Chun-Chi Chen, Chao-Lieh Chen, Yi Lin, Song-Quan You:
An All-Digital Time-Domain Smart Temperature Sensor With a Cost-Efficient Curvature Correction. 29-36 - Maryam Rezaei Khezeli, Mohammad Hossein Moaiyeri, Ali Jalali:
Comparative Analysis of Simultaneous Switching Noise Effects in MWCNT Bundle and Cu Power Interconnects in CNTFET-Based Ternary Circuits. 37-46 - Pan Xue, Yilei Shen, Dan Fang, Chenyang Wang, Haijun Shao, Ting Yi, Xiaoyang Zeng, Zhiliang Hong:
A 2-D Predistortion Based on Profile Inversion for Fully Digital Cartesian Transmitter. 47-56 - Jai-Ming Lin, You-Lun Deng, Szu-Ting Li, Bo-Heng Yu, Li-Yen Chang, Te-Wei Peng:
Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits With Obstacles. 57-68 - Ricardo Martins, Nuno Lourenço, Nuno Horta, Jun Yin, Pui-In Mak, Rui Paulo Martins:
Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications. 69-82 - Ned Bingham, Rajit Manohar:
QDI Constant-Time Counters. 83-91 - Jiwoong Choi, Boyeal Kim, Hyun Kim, Hyuk-Jae Lee:
A High-Throughput Hardware Accelerator for Lossless Compression of a DDR4 Command Trace. 92-102 - Daniel Morrison, Dennis Delic, Mehmet Rasit Yuce, Jean-Michel Redoute:
Multistage Linear Feedback Shift Register Counters With Reduced Decoding Logic in 130-nm CMOS for Large-Scale Array Applications. 103-115 - Nuno Miguel Cardanha Paulino, João Canas Ferreira, João M. P. Cardoso:
Dynamic Partial Reconfiguration of Customized Single-Row Accelerators. 116-125 - Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Dongsuk Jeon, Dennis Sylvester, Tony Tae-Hyoung Kim:
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. 126-137 - Sungju Ryu, Naebeom Park, Jae-Joon Kim:
Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator. 138-146 - Jae Young Hur:
Contiguity Representation in Page Table for Memory Management Units. 147-158 - Xunzhao Yin, Xiaoming Chen, Michael T. Niemier, Xiaobo Sharon Hu:
Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits. 159-172 - Jiangtao Xu, Wei Li, Kaiming Nie, Liqiang Han, Xiyang Zhao:
A Method to Reduce the Effect on Image Quality Caused by Resistance of Column Bus. 173-181 - Amir Bazrafshan, Mohammad Taherzadeh-Sani, Frederic Nabki:
An Analog LO Harmonic Suppression Technique for SDR Receivers. 182-192 - ByongChan Lim, Mark Horowitz:
An Analog Model Template Library: Simplifying Chip-Level, Mixed-Signal Design Verification. 193-204 - Xu Fang, Yang Yu, Xiyuan Peng:
TSV Prebond Test Method Based on Switched Capacitors. 205-218 - Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek:
Multiloop Control for Fast Transient DC-DC Converter. 219-228 - Longfei Wang, S. Karen Khatamifard, Ulya R. Karpuzcu, Selçuk Köse:
Exploiting Algorithmic Noise Tolerance for Scalable On-Chip Voltage Regulation. 229-242 - Chenchang Zhan, Guigang Cai, Wing-Hung Ki:
A Transient-Enhanced Output-Capacitor-Free Low-Dropout Regulator With Dynamic Miller Compensation. 243-247 - Amandeep Kaur, Deepak Mishra, Mukul Sarkar:
A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC. 248-252
Volume 27, Number 2, February 2019
- Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. 253-280 - Guillaume Renaud, Mamadou Diallo, Manuel J. Barragán, Salvador Mir:
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs. 281-293 - Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal:
CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency. 294-303 - Nicolas Laflamme-Mayer, Gilbert Kowarzyk, Yves Blaquière, Yvon Savaria, Mohamad Sawan:
A Defect-Tolerant Reusable Network of DACs for Wafer-Scale Integration. 304-315 - Tomasz Kulej, Fabian Khateb, Luis Henrique de Carvalho Ferreira:
A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta-Sigma Modulator in 0.18-µm CMOS. 316-325 - Chih-Wen Lu, Ping-Yeh Yin, Mu-Yong Lin:
A 10-bit Two-Stage R-DAC With Isolating Source Followers for TFT-LCD and AMOLED Column-Driver ICs. 326-336 - Yang Zhang, Debajit Basak, Kong-Pang Pun:
Power-Efficient Gm-C DSMs With High Immunity to Aliasing, Clock Jitter, and ISI. 337-349 - Kshitij Bhardwaj, Steven M. Nowick:
A Continuous-Time Replication Strategy for Efficient Multicast in Asynchronous NoCs. 350-363 - Mohammad A. Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, Daniel E. Holcomb:
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration. 364-375 - Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan:
A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. 376-386 - Sara Choi, Hong Keun Ahn, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. 387-397 - Pratheep Bondalapati, Won Namgoong:
Timing Jitter Distribution and Power Spectral Density of a Second-Order Bang-Bang Digital PLL With Transport Delay Using Fokker-Planck Equations. 398-406 - Chunyu Peng, Jiati Huang, Changyong Liu, Qiang Zhao, Songsong Xiao, Xiulong Wu, Zhiting Lin, Junning Chen, Xuan Zeng:
Radiation-Hardened 14T SRAM Bitcell With Speed and Power Optimized for Space Application. 407-415 - Md. Badruddoja Majumder, Md Sakib Hasan, Mesbah Uddin, Garrett S. Rose:
A Secure Integrity Checking System for Nanoelectronic Resistive RAM. 416-429 - Murali Krishna Rajendran, V. Priya, Shourya Kansal, Gajendranath Chowdary, Ashudeb Dutta:
A 100-mV-2.5-V Burst Mode Constant on-Time- Controlled Battery Charger With 92% Peak Efficiency and Integrated FOCV Technique. 430-443 - Zahi Moudallal, Farid N. Najm:
Power Scheduling With Active RC Power Grids. 444-457 - Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng:
A New Cellular-Based Redundant TSV Structure for Clustered Faults. 458-467 - Panagiotis Chaourani, Saul Rodriguez, Per-Erik Hellström, Ana Rusu:
Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines. 468-480 - Jianwei Liu, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo Martins:
Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. 481-485 - Pedro Reviriego, Salvatore Pontarelli, Anees Ullah:
Error Detection and Correction in SRAM Emulated TCAMs. 486-490 - Elena Ioana Vatajelu, Giorgio Di Natale:
High-Entropy STT-MTJ-Based TRNG. 491-495 - Irith Pomeranz:
Test Compaction by Test Removal Under Transparent Scan. 496-500
Volume 27, Number 3, March 2019
- Cheng-En Hsieh, Shen-Iuan Liu:
A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. 501-510 - Shaohan Liu, Dake Liu:
A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. 511-523 - Liming Xiu, Xiangye Wei, Yuhai Ma:
A Full Digital Fractional-N TAF-FLL for Digital Applications: Demonstration of the Principle of a Frequency-Locked Loop Built on Time-Average-Frequency. 524-534 - Gaurav Saini, Maryam Shojaei Baghini:
A Generic Power Management Circuit for Energy Harvesters With Shared Components Between the MPPT and Regulator. 535-548 - Donkyu Baek, Naehyuck Chang:
Runtime Power Management of Battery Electric Vehicles for Extended Range With Consideration of Driving Time. 549-559 - Shubham Rai, Jens Trommer, Michael Raitza, Thomas Mikolajick, Walter M. Weber, Akash Kumar:
Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors. 560-572 - Muhammad Ali, Mohammad A. Ahmed, Malgorzata Chrzanowska-Jeske:
Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization. 573-586 - Amard Afzalian, Hossein Miar Naimi, Massoud Dousti:
What Is the Maximum Achievable Oscillation Frequency in a Specified CMOS Process? 587-600 - Marko Simicic, Pieter Weckx, Bertrand Parvais, Philippe Roussel, Ben Kaczer, Georges G. E. Gielen:
Understanding the Impact of Time-Dependent Random Variability on Analog ICs: From Single Transistor Measurements to Circuit Simulations. 601-610 - Xiang Ge, Fan Yang, Hengliang Zhu, Xuan Zeng, Dian Zhou:
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition. 611-623 - Haomiao Wang, Prabu Thiagaraj, Oliver Sinnen:
Harmonic-Summing Module of SKA on FPGA - Optimizing the Irregular Memory Accesses. 624-636 - Xifan Tang, Edouard Giacomin, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs. 637-650 - Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi:
Estimating and Mitigating Aging Effects in Routing Network of FPGAs. 651-664 - Zhiming Zhang, Laurent Njilla, Charles A. Kamhoua, Qiaoyan Yu:
Thwarting Security Threats From Malicious FPGA Tools With Novel FPGA-Oriented Moving Target Defense. 665-678 - Shinwoong Park, Sanjay Raman:
Analysis and Optimization of Multisection Capacitive DACs for Mixed-Signal Processing. 679-690 - Wael Dghais, Malek Souilem, Muhammad Alam:
Mixed-Signal Overclocked I/O Buffers Model Abstraction for Signal Integrity Assessment. 691-699 - Scott Lerner, Isikcan Yilmaz, Baris Taskin:
Custard: ASIC Workload-Aware Reliable Design for Multicore IoT Processors. 700-710 - Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak:
Design and Optimization of Inductive-Coupling Links for 3-D-ICs. 711-723 - Daewoong Lee, Dongil Lee, Yong-Hun Kim, Lee-Sup Kim:
A 0.9-V 12-Gb/s Two-FIR Tap Direct DFE With Feedback-Signal Common-Mode Control. 724-728 - Arpan Thakkar, Srinivas Theertham, Peeyoosh Mirajkar, Sankaran Aniruddhan:
Techniques for Improved Continuous and Discrete Tuning Range in Millimeter-Wave VCOs. 729-733 - Mehrnaz Ahmadi, Sahand Salamat, Bijan Alizadeh:
A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs. 734-737 - Ausmita Sarker, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Hardware Constructions for Error Detection of Number-Theoretic Transform Utilized in Secure Cryptographic Architectures. 738-741 - Yuqi Wang, Amira Aouina, Hui Li, Ian O'Connor, Gabriela Nicolescu, Sébastien Le Beux:
Thermal-Aware Design Method for Laser Group Control in Nanophotonic Interconnects. 742-746
Volume 27, Number 4, April 2019
- Thinh Hung Pham, Phong Tran, Siew-Kei Lam:
High-Throughput and Area-Optimized Architecture for rBRIEF Feature Extraction. 747-756 - Tianchan Guan, Xiaoyang Zeng, Mingoo Seok:
Recursive Synaptic Bit Reuse: An Efficient Way to Increase Memory Capacity in Associative Memory. 757-768 - Duncan J. M. Moss, David Boland, Philip H. W. Leong:
A Two-Speed, Radix-4, Serial-Parallel Multiplier. 769-777 - Siyuan Xu, Benjamin Carrión Schäfer:
Toward Self-Tunable Approximate Computing. 778-789 - Dina M. Ellaithy, Magdy A. El-Moursy, Amal Zaki, Abdelhalim Zekry:
Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics. 790-798 - Nitish Kumar Srivastava, Rajit Manohar:
Operation-Dependent Frequency Scaling Using Desynchronization. 799-809 - Christopher Cowan:
Drafting in Self-Timed Circuits. 810-820 - Takao Oshita, Jonathan Douglas, Arun Krishnamoorthy:
High-Volume Testing and DC Offset Trimming Technique of On-Die Bandgap Voltage Reference for SOCs and Microprocessors. 821-829 - Shirin Pourashraf, Jaime Ramírez-Angulo, Jose Maria Hinojo Montero, Ramón González Carvajal, Antonio J. López-Martín:
±0.25-V Class-AB CMOS Capacitance Multiplier and Precision Rectifiers. 830-842 - Bing Li, Ji-Ping Na, Wei Wang, Jia Liu, Qian Yang, Pui-In Mak:
A 13-bit 8-kS/s Δ-Σ Readout IC Using ZCB Integrators With an Embedded Resistive Sensor Achieving 1.05-pJ/Conversion Step and a 65-dB PSRR. 843-853 - Xuan Dong, Lihong Zhang:
EA-Based LDE-Aware Fast Analog Layout Retargeting With Device Abstraction. 854-863 - Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang:
SLECTS: Slew-Driven Clock Tree Synthesis. 864-874 - Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. 875-887 - Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim:
System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs. 888-898 - Abdullah Guler, Niraj K. Jha:
Three-Dimensional Monolithic FinFET-Based 8T SRAM Cell Design for Enhanced Read Time and Low Leakage. 899-912 - Christian Pilato, Kanad Basu, Francesco Regazzoni, Ramesh Karri:
Black-Hat High-Level Synthesis: Myth or Reality? 913-926 - Hadi Jahanirad:
CC-SPRA: Correlation Coefficients Approach for Signal Probability-Based Reliability Analysis. 927-939 - Han Zhou, Zeyu Sun, Sheriff Sadiqbatcha, Naehyuck Chang, Sheldon X.-D. Tan:
EM-Aware and Lifetime-Constrained Optimization for Multisegment Power Grid Networks. 940-953 - Yintang Yang, Ke Chen, Huaxi Gu, Bowen Zhang, Lijing Zhu:
TAONoC: A Regular Passive Optical Network-on-Chip Architecture Based on Comb Switches. 954-963 - Fabio Frustaci, Stefania Perri, Pasquale Corsonello, Massimo Alioto:
Energy-Quality Scalable Adders Based on Nonzeroing Bit Truncation. 964-968 - Yi-An Chang, Trio Adiono, Amy Hamidah, Shen-Iuan Liu:
An On-Chip Relaxation Oscillator With Comparator Delay Compensation. 969-973 - Jusung Kim, Han-Shin Jo, Kyoung-Jae Lee, Dong-Ho Lee, Dae-Hyun Choi, Sangkil Kim:
A Low-Complexity I/Q Imbalance Calibration Method for Quadrature Modulator. 974-977 - Joo-Hyung Chae, Hyeongjun Ko, Jihwan Park, Suhwan Kim:
A Quadrature Clock Corrector for DRAM Interfaces, With a Duty-Cycle and Quadrature Phase Detector Based on a Relaxation Oscillator. 978-982 - Safwat Mostafa Noor, Eugene John, Manoj Panday:
Design and Implementation of an Ultralow-Energy FFT ASIC for Processing ECG in Cardiac Pacemakers. 983-987 - Panni Wang, Feng Xu, Bo Wang, Bin Gao, Huaqiang Wu, He Qian, Shimeng Yu:
Three-Dimensional nand Flash for Vector-Matrix Multiplication. 988-991
Volume 27, Number 5, May 2019
- Manas Kumar Lenka, Gaurab Banerjee:
A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback. 993-1006 - Omar Elsayed, Jorge Zarate-Roldan, Amr Abuellil, Faisal Abdel-Latif Hussien, Ahmed Eladawy, Edgar Sánchez-Sinencio:
Highly Linear Low-Power Wireless RF Receiver for WSN. 1007-1016 - Tutu Wan, Yasha Karimi, Milutin Stanacevic, Emre Salman:
AC Computing Methodology for RF-Powered IoT Devices. 1017-1028 - Heikki Kultala, Timo Viitanen, Heikki Berg, Pekka Jääskeläinen, Joonas Multanen, Mikko Kokkonen, Kalle Raiskila, Tommi Zetterman, Jarmo Takala:
LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor. 1029-1042 - Yuejun Zhang, Zhao Pan, Pengjun Wang, Dailu Ding, Qiaoyan Yu:
A 0.1-pJ/b and ACF <0.04 Multiple-Valued PUF for Chip Identification Using Bit-Line Sharing Strategy in 65-nm CMOS. 1043-1052 - Sandhya Koteshwara, Amitabh Das, Keshab K. Parhi:
Architecture Optimization and Performance Comparison of Nonce-Misuse-Resistant Authenticated Encryption Algorithms. 1053-1066 - Michael Weiner, Wolfgang Wieser, Emili Lupon, Georg Sigl, Salvador Manich:
A Calibratable Detector for Invasive Attacks. 1067-1079 - Partha De, Chittaranjan Mandal, Udaya Parampalli:
Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks. 1080-1092 - Yushan Jiang, Dong Wang, Pak Kwong Chan:
A Quiescent 407-nA Output-Capacitorless Low-Dropout Regulator With 0-100-mA Load Current Range. 1093-1104 - Yaqub Mahnashi, Fang Z. Peng:
A Monolithic Voltage-Scalable Fibonacci Switched-Capacitor DC-DC Converter With Intrinsic Parasitic Charge Recycling. 1105-1113 - Abdulqader Nael Mahmoud, Mohammad Alhawari, Baker Mohammad, Hani H. Saleh, Mohammed Ismail:
A Gain-Controlled, Low-Leakage Dickson Charge Pump for Energy-Harvesting Applications. 1114-1123 - Swati Bhardwaj, Shashank Raghuraman, Amit Acharyya:
Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA. 1124-1137 - Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin:
Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures. 1138-1147 - Mario Garrido, Jesús Grajal, Oscar Gustafsson:
Optimum Circuits for Bit-Dimension Permutations. 1148-1160 - Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
TOSAM: An Energy-Efficient Truncation- and Rounding-Based Scalable Approximate Multiplier. 1161-1173 - Qinghui Hong, Qiujie Wu, Xiaoping Wang, Zhigang Zeng:
Novel Nonlinear Function Shift Method for Generating Multiscroll Attractors Using Memristor-Based Control Circuit. 1174-1185 - John Vista, Ashish Ranjan:
A Simple Floating MOS-Memristor for High-Frequency Applications. 1186-1195 - Pavan Kumar Javvaji, Spyros Tragoudas:
On the Sensitization Probability of a Critical Path Considering Process Variations and Path Correlations. 1196-1205 - Hadi Ahmadi Balef, Hamed Fatemi, Kees Goossens, José Pineda de Gyvez:
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. 1206-1217 - Bo-Cheng Lai, Jyun-Wei Pan, Chien-Yu Lin:
Enhancing Utilization of SIMD-Like Accelerator for Sparse Convolutional Neural Networks. 1218-1222 - Subrahmanyam Mula, Vinay Chakravarthi Gogineni, Anindya Sundar Dhar:
Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise. 1223-1227 - Felipe S. Marranghello, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Four-Level Forms for Memristive Material Implication Logic. 1228-1232 - Sami Ur Rehman, Mohammad Mahdi Khafaji, Corrado Carta, Frank Ellinger:
A 10-Gb/s 20-ps Delay-Range Digitally Controlled Differential Delay Element in 45-nm SOI CMOS. 1233-1237 - Manas Kumar Lenka, Gaurab Banerjee:
Corrections Corrections to "A Wideband Blocker-Tolerant Receiver With Frequency-Translational Resistive Feedback". 1238
Volume 27, Number 6, June 2019
- Huanyu Wang, Qihang Shi, Domenic Forte, Mark M. Tehranipoor:
Probing Assessment Framework and Evaluation of Antiprobing Solutions. 1239-1252 - Ahish Shylendra, Swarup Bhunia, Amit Ranjan Trivedi:
An Intrinsic and Database-Free Authentication by Exploiting Process Variation in Back-End Capacitors. 1253-1261 - Shrinidhi Udupi, Joakim Urdahl, Dominik Stoffel, Wolfgang Kunz:
Exploiting Hardware Unobservability for Low-Power Design and Safety Analysis in Formal Verification-Driven Design Flows. 1262-1275 - Tianwen Li, Hongjin Liu, Haigang Yang:
Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA. 1276-1283 - Jakub Siast, Adam Luczak, Marek Domanski:
RingNet: A Memory-Oriented Network-On-Chip Designed for FPGA. 1284-1297 - Inayat Ullah, Zahid Ullah, Umar Afzaal, Jeong-A Lee:
DURE: An Energy- and Resource-Efficient TCAM Architecture for FPGAs With Dynamic Updates. 1298-1307 - Daniel Kraak, Mottaqiallah Taouil, Innocent Agbo, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor:
Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM. 1308-1321 - Jeetendra Singh, Balwinder Raj:
Design and Investigation of 7T2M-NVSRAM With Enhanced Stability and Temperature Impact on Store/Restore Energy. 1322-1328 - Nour Sayed, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme. 1329-1342 - Gyuseong Kang, Jongsun Park:
Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM. 1343-1352 - Anindita Paul, Jaime Ramírez-Angulo, Antonio Torralba:
Analysis, Comparison, and Experimental Validation of a Class AB Voltage Follower With Enhanced Bandwidth and Slew Rate. 1353-1364 - Baibhab Chatterjee, Priyadarshini Panda, Shovan Maity, Ayan Biswas, Kaushik Roy, Shreyas Sen:
Exploiting Inherent Error Resiliency of Deep Neural Networks to Achieve Extreme Energy Efficiency Through Mixed-Signal Neurons. 1365-1377 - Xu Meng, Lianhong Zhou, Fujiang Lin, Chun-Huat Heng:
A Low-Noise Digital-to-Frequency Converter Based on Injection-Locked Ring Oscillator and Rotated Phase Selection for Fractional- $N$ Frequency Synthesis. 1378-1389 - Song-Nien Tang, Fu-Chiang Jan:
Energy-Efficient and Calibration-Aware Fourier-Domain OCT Imaging Processor. 1390-1403 - Eduardo Weber Wächter, Cedric de Bellefroid, Basireddy Karunakar Reddy, Amit Kumar Singh, Bashir M. Al-Hashimi, Geoff V. Merrett:
Predictive Thermal Management for Energy-Efficient Execution of Concurrent Applications on Heterogeneous Multicores. 1404-1415 - Yao Xiao, Shahin Nazarian, Paul Bogdan:
Self-Optimizing and Self-Programming Computing Systems: A Combined Compiler, Complex Networks, and Machine Learning Approach. 1416-1427 - Irith Pomeranz:
Extracting a Close-to-Minimum Multicycle Functional Broadside Test Set From a Functional Test Sequence. 1428-1437 - P. R. Chithira, Vinita Vasudevan:
Potential Critical Path Selection Based on a Time-Varying Statistical Timing Analysis Framework. 1438-1449 - Ding-Yuan Lee, Ching-Che Wang, An-Yeu Wu:
Bundle-Updatable SRAM-Based TCAM Design for OpenFlow-Compliant Packet Processor. 1450-1454 - Suhong Moon, Kwanghyun Shin, Dongsuk Jeon:
Enhancing Reliability of Analog Neural Network Processors. 1455-1459 - Georgios Zervakis, Konstantina Koliogeorgi, Dimitrios Anagnostos, Nikolaos Zompakis, Kostas Siozios:
VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits. 1460-1464 - Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim:
A Restore-Free Mode for MLC STT-RAM Caches. 1465-1469 - Liang Wen, Yuejun Zhang, Xiaoyang Zeng:
Column-Selection-Enabled 10T SRAM Utilizing Shared Diff-VDD Write and Dropped-VDD Read for Power Reduction. 1470-1474 - Shao-I Chu, Chen-En Hsieh, Yu-Jung Huang:
Design of FSM-Based Function With Reduced Number of States in Integral Stochastic Computing. 1475-1479 - Tejinder Singh Sandhu, Kamal El-Sankary:
Supply-Insensitive Digitally Controlled Delay Lines for 3-D IC Clock Synchronization Architectures. 1480-1484
Volume 27, Number 7, July 2019
- Massimo Alioto:
Editorial: TVLSI Keynote Papers Enriching Our Transactions With Invited Contributions. 1485 - Giovanni V. Resta, Alessandra Leonhardt, Yashwanth Balaji, Stefan De Gendt, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems. 1486-1503 - Hasan Ulusan, Salar Chamanian, Bedirhan Ilik, Ali Muhtaroglu, Haluk Külah:
Fully Implantable Cochlear Implant Interface Electronics With 51.2- μW Front-End Circuit. 1504-1512 - Yuan Liang, Chirn Chye Boon, Chenyang Li, Xiao-Lan Tang, Herman Jalli Ng, Dietmar Kissinger, Yong Wang, Qingfeng Zhang, Hao Yu:
Design and Analysis of $D$ -Band On-Chip Modulator and Signal Source Based on Split-Ring Resonator. 1513-1526 - Jeng-Han Tsai:
Design of a 5.3-GHz 31.3-dBm Fully Integrated CMOS Power Amplifier Using Folded Splitting and Combining Architecture. 1527-1536 - Anil Kumar Gundu, Volkan Kursun:
Low Leakage Clock Tree With Dual-Threshold- Voltage Split Input-Output Repeaters. 1537-1547 - Christopher Williams, Diaaeldin Abdelrahman, Xiangdong Jia, Abdullah Ibn Abbas, Odile Liboiron-Ladouceur, Glenn E. R. Cowan:
Reconfiguration in Source-Synchronous Receivers for Short-Reach Parallel Optical Links. 1548-1560 - Luong N. Nguyen, Chia-Lin Cheng, Milos Prvulovic, Alenka G. Zajic:
Creating a Backscattering Side Channel to Enable Detection of Dormant Hardware Trojans. 1561-1574 - Uthman Alsaiari, Fayez Gebali:
Hardware Trojan Detection Using Reconfigurable Assertion Checkers. 1575-1586 - Debapriya Basu Roy, Debdeep Mukhopadhyay:
High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves. 1587-1600 - Amin Norollah, Danesh Derafshi, Hakem Beitollahi, Mahdi Fazeli:
RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm. 1601-1613 - Jeng-Shyang Pan, Chiou-Yng Lee, Anissa Sghaier, Zeghid Medien, Jiafeng Xie:
Novel Systolization of Subquadratic Space Complexity Multipliers Based on Toeplitz Matrix-Vector Product Approach. 1614-1622 - Shirshendu Roy, Debiprasad Priyabrata Acharya, Ajit Kumar Sahoo:
Low-Complexity Architecture of Orthogonal Matching Pursuit Based on QR Decomposition. 1623-1632 - Somayeh Rahimipour, Runjie Zhang, Ke Wang, Kevin Skadron, Fakhrul Zaman Rokhani, Mircea R. Stan:
MTTF Enhancement Power-C4 Bump Placement Optimization. 1633-1639 - Dae-Hyun Kim, Shu-Han Hsu, Linda Milor:
Optimization of Experimental Designs for System- Level Accelerated Life Test in a Memory System Degraded by Time-Dependent Dielectric Breakdown. 1640-1651 - Sami Salamin, Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra, Jörg Henkel:
Modeling the Interdependences Between Voltage Fluctuation and BTI Aging. 1652-1665 - Zeyu Sun, Sheriff Sadiqbatcha, Hengyang Zhao, Sheldon X.-D. Tan:
Saturation-Volume Estimation for Multisegment Copper Interconnect Wires. 1666-1674 - Nezam Rohbani, Hiroaki Gau, Sara Mohammadinejad, Tapas Kumar Maiti, Dondee Navarro, Mitiko Miura-Mattausch, Hans Jürgen Mattausch, Hirotaka Takatsuka:
Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values. 1675-1684 - Govind Radhakrishnan, Youngki Yoon, Manoj Sachdev:
A Parametric DFT Scheme for STT-MRAMs. 1685-1696 - Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM. 1697-1710 - Fabrizio Riente, Daniel Melis, Marco Vacca:
Exploring the 3-D Integrability of Perpendicular Nanomagnet Logic Technology. 1711-1719 - Irith Pomeranz:
Test Scores for Improving the Accuracy of Logic Diagnosis for Multiple Defects. 1720-1724 - Yi-An Chang, Shen-Iuan Liu:
A 13.4-MHz Relaxation Oscillator With Temperature Compensation. 1725-1729
Volume 27, Number 8, August 2019
- Andrew J. Douglass, Sunil P. Khatri:
Fast, Ring-Based Design of 3-D Stacked DRAM. 1731-1741 - Debasri Saha, Susmita Sur-Kolay:
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs. 1742-1750 - Jiann-Jong Chen, Yuh-Shyan Hwang, Jun-Yi Lin, Yitsen Ku:
A Dead-Beat-Controlled Fast-Transient-Response Buck Converter With Active Pseudo-Current-Sensing Techniques. 1751-1759 - Shuenn-Yuh Lee, Zhan-Xian Liao, Chih-Hung Lee:
Energy-Harvesting Circuits With a High-Efficiency Rectifier and a Low Temperature Coefficient Bandgap Voltage Reference. 1760-1767 - Venkata Chaitanya Krishna Chekuri, Monodeep Kar, Arvind Singh, Saibal Mukhopadhyay:
Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations. 1768-1778 - Albert Ciprut, Eby G. Friedman:
Stability of On-Chip Power Delivery Systems With Multiple Low-Dropout Regulators. 1779-1789 - Archit Joshi, Mukul Sarkar:
A Low-Pass Filter Bandwidth Adaptation Technique for Phase Interpolators. 1790-1798 - Chihiro Matsui, Ken Takeuchi:
Dynamic Adjustment of Storage Class Memory Capacity in Memory-Resource Disaggregated Hybrid Storage With SCM and NAND Flash Memory. 1799-1810 - Kwangmin Kim, Seokjoon Kang, Byungsub Kim:
A Code Inversion Encoding Technique to Improve Read Margin of A Cross-Point Phase Change Memory. 1811-1818 - Randy W. Mann, Meixiong Zhao, Sanjay Parihar, Qun Gao, Ankur Arya, Carl Radens, Shesh Mani Pandey, Joseph Versaggi, Jack M. Higman, Rick Carter:
An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM. 1819-1827 - Junyoung Ko, Younghwi Yang, Jisu Kim, Cheon An Lee, Young-Sun Min, Jin-Young Chun, Moosung Kim, Seong-Ook Jung:
Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory. 1828-1839 - Jisu Min, Cheol Kim, Sung-Yong Kim, Kee-Won Kwon:
A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training. 1840-1850 - Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang, Dijun Liu, Weisheng Zhao:
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design. 1851-1860 - Duy Thanh Nguyen, Tuan Nghia Nguyen, Hyun Kim, Hyuk-Jae Lee:
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection. 1861-1873 - Xiaocong Lian, Zhenyu Liu, Zhourui Song, Jiwu Dai, Wei Zhou, Xiangyang Ji:
High-Performance FPGA-Based CNN Accelerator With Block-Floating-Point Arithmetic. 1874-1885 - Seongjong Kim, Joao Pedro Cerqueira, Mingoo Seok:
A Near-Threshold Spiking Neural Network Accelerator With a Body-Swapping-Based In Situ Error Detection and Correction Technique. 1886-1896 - Aayush Ankit, Minsuk Koo, Shreyas Sen, Kaushik Roy:
Powerline Communication for Enhanced Connectivity in Neuromorphic Systems. 1897-1906 - Eberle A. Rambo, Yunsheng Shang, Rolf Ernst:
Providing Integrity in Real-Time Networks-on-Chip. 1907-1920 - Tao-Chun Yu, An-Jie Shih, Shao-Yun Fang:
Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. 1921-1932 - Kyeongrok Jo, Seyong Ahn, Jungho Do, Taejoong Song, Taewhan Kim, Kyu-Myung Choi:
Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. 1933-1946 - Libo Qian, Kefang Qian, Xitao He, Zhufei Chu, Yidie Ye, Shi Ge, Yinshui Xia:
Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design. 1947-1951 - Pedro Reviriego, Anees Ullah, Salvatore Pontarelli:
PR-TCAM: Efficient TCAM Emulation on Xilinx FPGAs Using Partial Reconfiguration. 1952-1956 - Myeongjin Kim, Wontaeck Jung, Hyukjun Lee, Eui-Young Chung:
A Novel NAND Flash Memory Architecture for Maximally Exploiting Plane-Level Parallelism. 1957-1961 - Olivier Muller, Adrien Prost-Boucle, Alban Bourge, Frédéric Pétrot:
Efficient Decompression of Binary Encoded Balanced Ternary Sequences. 1962-1966 - Rafael Sanchotene Silva, Lucas Pereira Luiz, Márcio Cherem Schneider, Carlos Galup-Montoro:
A Test Chip for Characterization of the Series Association of MOSFETs. 1967-1971 - Jihye Kim, Sangjun Lee, Sungho Kang:
Test-Friendly Data-Selectable Self-Gating (DSSG). 1972-1976
Volume 27, Number 9, September 2019
- Chuanjin Richard Shi, Aili Wang:
Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. 1977-1989 - Daiguo Xu, Hequan Jiang, Lei Qiu, Xiaoquan Yu, Jianan Wang, Zhengping Zhang, Can Zhu, Shiliu Xu:
A Linearity-Enhanced 10-Bit 160-MS/s SAR ADC With Low-Noise Comparator Technique. 1990-1997 - Guanhua Wang, Kexu Sun, Qing Zhang, Salam Elahmadi, Ping Gui:
A 43.6-dB SNDR 1-GS/s 3.2-mW SAR ADC With Background-Calibrated Fine and Coarse Comparators in 28-nm CMOS. 1998-2007 - Congyi Zhu, Renrong Liang, Jun Lin, Zhongfeng Wang, Li Li:
Analysis and Design of a Large Dither Injection Circuit for Improving Linearity in Pipelined ADCs. 2008-2020 - Prathamesh Khatavkar, Sankaran Aniruddhan:
432 nW per Channel 130 nV/rtHz ECG Acquisition Front End With Multifrequency Chopping. 2021-2032 - Wonyoung Lee, Mincheol Kang, Seokin Hong, Soontae Kim:
Interpage-Based Endurance-Enhancing Lower State Encoding for MLC and TLC Flash Memory Storages. 2033-2045 - Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yufei Ding, Weisheng Zhao, Yuan Xie:
DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System. 2046-2059 - Shuo-Han Chen, Yuan-Hao Chang, Yu-Ming Chang, Wei-Kuan Shih:
mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM Storages. 2060-2073 - Shahzad Muzaffar, Ibrahim M. Elfadel:
A Domain-Specific Processor Microarchitecture for Energy-Efficient, Dynamic IoT Communication. 2074-2087 - Yupeng Fu, Lianming Li, Dongming Wang, Xuan Wang, Long He:
28-GHz CMOS VCO With Capacitive Splitting and Transformer Feedback Techniques for 5G Communication. 2088-2095 - Irith Pomeranz:
Extended Transparent-Scan. 2096-2104 - Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. 2105-2118 - Jiafeng Xie, Chiou-Yng Lee, Pramod Kumar Meher, Zhi-Hong Mao:
Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis. 2119-2130 - Ned Bingham, Rajit Manohar:
Self-Timed Adaptive Digit-Serial Addition. 2131-2141 - Fereshteh Jafarzadehpour, Amir Sabbagh Molahosseini, Azadeh Alsadat Emrani Zarandi, Leonel Sousa:
Efficient Modular Adder Designs Based on Thermometer and One-Hot Coding. 2142-2155 - Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan:
Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base. 2156-2169 - Chaudhry Indra Kumar, Ishant Bhatia, Arvind Kumar Sharma, Deep Sehgal, H. S. Jatana, Anand Bulusu:
A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. 2170-2179 - Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac:
Modeling and Detectability of Full Open Gate Defects in FinFET Technology. 2180-2190 - Khushboo Rani, Hemangee K. Kapoor:
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects. 2191-2204 - Jiyong Woo, Shimeng Yu:
Impact of Selector Devices in Analog RRAM-Based Crossbar Arrays for Inference and Training of Neuromorphic System. 2205-2212 - Yidong Liu, Leibo Liu, Fabrizio Lombardi, Jie Han:
An Energy-Efficient and Noise-Tolerant Recurrent Neural Network Using Stochastic Computing. 2213-2221 - Yuanyong Luo, Yuxuan Wang, Yajun Ha, Zhongfeng Wang, Siyuan Chen, Hongbing Pan:
Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base". 2222
Volume 27, Number 10, October 2019
- Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui-In Mak, Rui Paulo Martins:
Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter. 2223-2236 - Seong-Jin Yun, Jiseong Lee, Yun Chan Im, Yong Sin Kim:
A Digital LDO Regulator With a Self-Clocking Burst Logic for Ultralow Power Applications. 2237-2245 - Anindita Paul, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, José Miguel Rocha-Pérez:
Pseudo-Three-Stage Miller Op-Amp With Enhanced Small-Signal and Large-Signal Performance. 2246-2259 - Iman Y. Taha, Mitra Mirhassani:
A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar. 2260-2271 - Sadegh Yazdanshenas, Vaughn Betz:
The Costs of Confidentiality in Virtualized FPGAs. 2272-2283 - Kokila Jagadeesh, N. Ramasubramanian, Nagi Naganathan:
Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications. 2284-2295 - Shukla Banik, Suchismita Roy, Bibhash Sen:
Application-Dependent Testing of FPGA Interconnect Network. 2296-2304 - Umamaheswara Rao Tida, Cheng Zhuo, Yiyu Shi:
Single-Inductor-Multiple-Tier Regulation: TSV-Inductor-Based On-Chip Buck Converters for 3-D IC Power Delivery. 2305-2316 - Lennart Bamberg, Alberto García Ortiz:
Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs. 2317-2330 - Saru Vig, Rohan Juneja, Guiyuan Jiang, Siew-Kei Lam, Changhai Ou:
Framework for Fast Memory Authentication Using Dynamically Skewed Integrity Tree. 2331-2343 - Yajuan He, Jiubai Zhang, Xiaoqing Wu, Xin Si, Shaowei Zhen, Bo Zhang:
A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations. 2344-2353 - Cuiping Shao, Huiyun Li, Jiayan Fang, Qihua Deng:
An Error Location and Correction Method for Memory Based on Data Similarity Analysis. 2354-2364 - Hayoung Lee, Donghyun Han, Seungtaek Lee, Sungho Kang:
Dynamic Built-In Redundancy Analysis for Memory Repair. 2365-2374 - Fazal Hameed, Jerónimo Castrillón:
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. 2375-2386 - Wooyoung Jang:
Unaligned Burst-Aware Memory Subsystem. 2387-2400 - Ing-Chao Lin, Da-Wei Chang, Chen-Tai Kao, Sheng-Xuan Lin:
Infection-Based Dead Page Prediction in Hybrid Memory Architecture. 2401-2412 - Suk Min Kim, Byungkyu Song, Seong-Ook Jung:
Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM. 2413-2422 - Hang Wang, Tiancheng Wang, Longjun Liu, Hongbin Sun, Nanning Zheng:
Efficient Compression-Based Line Buffer Design for Image/Video Processing Circuits. 2423-2433 - Tai-Cheng Lee, Yih-Lang Li:
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. 2434-2446 - Mohamed Kouki:
Model Order Reduction Method for Large-Scale RC Interconnect and Implementation of Adaptive Digital PI Controller. 2447-2458 - Weiqiang Liu, Sailong Fan, Ayesha Khalid, Ciara Rafferty, Máire O'Neill:
Optimized Schoolbook Polynomial Multiplication for Compact Lattice-Based Cryptography on FPGA. 2459-2463 - Chua-Chin Wang, Pang-Yen Lou, Tsung-Yi Tsai, Hsiang-Yu Shih:
74-dBc SFDR 71-MHz Four-Stage Pipeline ROM-Less DDFS Using Factorized Second-Order Parabolic Equations. 2464-2468
Volume 27, Number 11, November 2019
- Anupam Chattopadhyay, Swaroop Ghosh, Wayne P. Burleson, Debdeep Mukhopadhyay:
Guest Editorial Special Section on Security Challenges and Solutions With Emerging Computing Technologies. 2469-2472 - Ben Perach, Shahar Kvatinsky:
An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. 2473-2484 - Ting-Sheng Chen, Kai-Ni Hou, Win-Ken Beh, An-Yeu Wu:
Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks. 2485-2497 - Lukas Zimmermann, Alexander Scholz, Mehdi Baradaran Tahoori, Jasmin Aghassi-Hagmann, Axel Sikora:
Design and Evaluation of a Printed Analog-Based Differential Physical Unclonable Function. 2498-2510 - Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori:
A Spintronics Memory PUF for Resilience Against Cloning Counterfeit. 2511-2522 - Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri:
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. 2523-2535 - Yanping Gong, Fengyu Qian, Lei Wang:
Design for Test and Hardware Security Utilizing Retention Loss of Memristors. 2536-2547 - Taehui Na, Byungkyu Song, Sara Choi, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung:
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. 2548-2555 - Akhilesh Jaiswal, Indranil Chakraborty, Amogh Agrawal, Kaushik Roy:
8T SRAM Cell as a Multibit Dot-Product Engine for Beyond Von Neumann Computing. 2556-2567 - Xizhu Peng, Jinfeng Guo, Qingqing Bao, Zeyu Li, Haoyu Zhuang, He Tang:
A Low-Power Low-Cost On-Chip Digital Background Calibration for Pipelined ADCs. 2568-2574 - Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura:
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. 2575-2586 - Irith Pomeranz:
Padding of Multicycle Broadside and Skewed-Load Tests. 2587-2595 - Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras:
Postbond Test of Through-Silicon Vias With Resistive Open Defects. 2596-2607 - Wenqing Song, Huayi Zhou, Kai Niu, Zaichen Zhang, Li Li, Xiaohu You, Chuan Zhang:
Efficient Successive Cancellation Stack Decoder for Polar Codes. 2608-2619 - Jing Guo, Shanshan Liu, Lei Zhu, Fabrizio Lombardi:
A CMOS Majority Logic Gate and its Application to One-Step ML Decodable Codes. 2620-2628 - Florian Zaruba, Luca Benini:
The Cost of Application-Class Processing: Energy and Performance Analysis of a Linux-Ready 1.7-GHz 64-Bit RISC-V Core in 22-nm FDSOI Technology. 2629-2640 - Xin Zhan, Jianhao Chen, Edgar Sánchez-Sinencio, Peng Li:
Power Management for Multicore Processors via Heterogeneous Voltage Regulation and Machine Learning Enabled Adaptation. 2641-2654 - Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. 2655-2667 - Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yuan Xie, Weisheng Zhao:
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks. 2668-2679 - Jackson Melchert, Setareh Behroozi, Jingjie Li, Younghyun Kim:
SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency. 2680-2692 - Rahul Kumar, Brajesh Kumar Kaushik, R. Balasubramanian:
Multispectral Transmission Map Fusion Method and Architecture for Image Dehazing. 2693-2697 - Yu-Kai Chiu, Shen-Iuan Liu:
A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor. 2698-2702
Volume 27, Number 12, December 2019
- Prabhat Mishra, Debdeep Mukhopadhyay, Swarup Bhunia:
Guest Editorial: Special Section on Autonomous Intelligence for Security and Privacy Analytics. 2703-2705 - Rana Elnaggar, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori:
Hardware Trojan Detection Using Changepoint-Based Anomaly Detection Techniques. 2706-2719 - Anupam Golder, Debayan Das, Josef Danial, Santosh Ghosh, Shreyas Sen, Arijit Raychowdhury:
Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack. 2720-2733 - Vojtech Mrazek, Lukás Sekanina, Roland Dobai, Marek Sýs, Petr Svenda:
Efficient On-Chip Randomness Testing Utilizing Machine Learning Techniques. 2734-2744 - Jingyan Fu, Zhiheng Liao, Jinhui Wang:
Memristor-Based Neuromorphic Hardware Improvement for Privacy-Preserving ANN. 2745-2754 - Mohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty, Ramesh Karri:
Toward Secure Microfluidic Fully Programmable Valve Array Biochips. 2755-2766 - Wei Zeng, Boyu Zhang, Azadeh Davoodi:
Analysis of Security of Split Manufacturing Using Machine Learning. 2767-2780 - Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly:
Securing a Wireless Network-on-Chip Against Jamming-Based Denial-of-Service and Eavesdropping Attacks. 2781-2791 - Zhaojun Lu, Qian Wang, Gang Qu, Haichun Zhang, Zhenglin Liu:
A Blockchain-Based Privacy-Preserving Authentication Scheme for VANETs. 2792-2801 - Stjepan Picek, Annelie Heuser, Alan Jovic, Lejla Batina:
A Systematic Evaluation of Profiling Through Focused Feature Selection. 2802-2815 - S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. 2816-2828 - Rajat Sadhukhan, Nilanjan Datta, Debdeep Mukhopadhyay:
Power Efficiency of S-Boxes: From a Machine-Learning-Based Tool to a Deterministic Model. 2829-2841 - Sumit K. Mandal, Ganapati Bhat, Chetan Arvind Patil, Janardhan Rao Doppa, Partha Pratim Pande, Ümit Y. Ogras:
Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning. 2842-2854 - Yuhua Liang, Zhangming Zhu, Xueqing Li, Sumeet Kumar Gupta, Suman Datta, Vijaykrishnan Narayanan:
Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances. 2855-2860 - Wookpyo Hong, Bai Nguyen, Zhiyuan Zhou, Nghia Tang, Jong-Hoon Kim, Partha Pratim Pande, Deukhyoun Heo:
A Dual-Output Step-Down Switched-Capacitor Voltage Regulator With a Flying Capacitor Crossing Technique for Enhanced Power Efficiency. 2861-2871 - Yongkang Tang, Shaoqing Li, Liang Fang, Xiao Hu, Jihua Chen:
Golden-Chip-Free Hardware Trojan Detection Through Quiescent Thermal Maps. 2872-2883 - Xiaoxiao Wang, Yueying Han, Mark M. Tehranipoor:
System-Level Counterfeit Detection Using On-Chip Ring Oscillator Array. 2884-2896 - Md. Mahbub Alam, Mark M. Tehranipoor, Domenic Forte:
Recycled FPGA Detection Using Exhaustive LUT Path Delay Characterization and Voltage Scaling. 2897-2910 - Ashiq A. Sakib, Scott C. Smith, Sudarshan K. Srinivasan:
Formal Modeling and Verification of PCHB Asynchronous Circuits. 2911-2924 - M. Hassan Najafi, Devon Jenson, David J. Lilja, Marc D. Riedel:
Performing Stochastic Computation Deterministically. 2925-2938 - Jiaquan Wu, Feiteng Li, Zhijian Chen, Xiaoyan Xiang:
A 3.89-GOPS/mW Scalable Recurrent Neural Network Processor With Improved Efficiency on Memory and Computation. 2939-2943 - Soon-Won Kwon, Hyeon-Min Bae:
A Fully Digital Semirotational Frequency Detection Algorithm for Bang-Bang CDRs. 2944-2948 - Ruikuan Lu, A. K. M. Arifuzzman, Md. Kamal Hossain, Steven D. Gardner, Sazia A. Eliza, J. Iwan D. Alexander, Yehia Massoud, Mohammad Rafiqul Haider:
A Low-Power Sensitive Integrated Sensor System for Thermal Flow Monitoring. 2949-2953 - Yun Fang, Zhong Tang, Xiao-Peng Yu, Zheng Shi, Kiat Seng Yeo:
A Reliability-Oriented Startup Analysis of Injection-Locked Frequency Divider Based on Broken Symmetry Theory. 2954-2958
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