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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 36
Volume 36, Number 1, January 2017
- Colin C. McAndrew
:
Layout Symmetries: Quantification and Application to Cancel Nonlinear Process Gradients. 1-14 - Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal:
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors. 15-26 - Mengying Zhao, Yuan Xue, Jingtong Hu, Chengmo Yang, Tiantian Liu, Zhiping Jia, Chun Jason Xue:
State Asymmetry Driven State Remapping in Phase Change Memory. 27-40 - Skyler Windh, Calvin Phung, Daniel T. Grissom, Paul Pop, Philip Brisk:
Performance Improvements and Congestion Reduction for Routing-Based Synthesis for Digital Microfluidic Biochips. 41-54 - Kai Hu, Trung Anh Dinh, Tsung-Yi Ho, Krishnendu Chakrabarty:
Control-Layer Routing and Control-Pin Minimization for Flow-Based Microfluidic Biochips. 55-68 - Jeffrey McDaniel, Zachary Zimmerman, Daniel T. Grissom, Philip Brisk:
PCB Escape Routing and Layer Minimization for Digital Microfluidic Biochips. 69-82 - Jeffrey Goeders, Steven J. E. Wilton:
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. 83-96 - Benjamin Carrión Schäfer:
Enabling High-Level Synthesis Resource Sharing Design Space Exploration in FPGAs Through Automatic Internal Bitwidth Adjustments. 97-105 - Matthew J. Walker, Stephan Diestelhorst, Andreas Hansson, Anup Das, Sheng Yang, Bashir M. Al-Hashimi, Geoff V. Merrett:
Accurate and Stable Run-Time Power Modeling for Mobile and Embedded CPUs. 106-119 - Zhezhao Xu, Chao Zhang, Wenjian Yu:
Floating Random Walk-Based Capacitance Extraction for General Non-Manhattan Conductor Structures. 120-133 - Chien-Chih Huang, Jwu-E Chen, Chin-Long Wey:
PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays. 134-145 - Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang:
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction. 146-155 - Shao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu:
Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly. 156-169 - Tuck-Boon Chan, Puneet Gupta, Kwangsoo Han, Abde Ali Kagalwalla, Andrew B. Kahng:
Benchmarking of Mask Fracturing Heuristics. 170-183 - Jhen-Zong Chen, Kuen-Jong Lee:
Test Stimulus Compression Based on Broadcast Scan With One Single Input. 184-197
Volume 36, Number 2, February 2017
- Yingjie Lao, Bo Yuan, Chris H. Kim, Keshab K. Parhi:
Reliable PUF-Based Local Authentication With Self-Correction. 201-213 - Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty:
Generalized Asynchronous Time-Triggered Scheduling for FlexRay. 214-226 - Zidong Du, Shaoli Liu, Robert Fasthuber, Tianshi Chen, Paolo Ienne, Ling Li, Tao Luo, Qi Guo, Xiaobing Feng, Yunji Chen, Olivier Temam:
An Accelerator for High Efficient Vision Processing. 227-240 - Rui Wang, Dan Jia, Tao Li, Depei Qian:
Achieving Versatile and Simultaneous Cache Optimizations With Nonvolatile SRAM. 241-254 - Xiaodao Chen, Dongmei Zhang, Lizhe Wang, Ning Jia, Zhijiang Kang, Yun Zhang, Shiyan Hu:
Design Automation for Interwell Connectivity Estimation in Petroleum Cyber-Physical Systems. 255-264 - Arash Saifhashemi, Hsin-Ho Huang, Peter A. Beerel:
Reconditioning: A Framework for Automatic Power Optimization of QDI Circuits. 265-278 - Qiao Chen, Xiaoping Wang, Haibo Wan, Ran Yang:
A Logic Circuit Design for Perfecting Memristor-Based Material Implication. 279-284 - Changlin Chen, Yaowen Fu, Sorin Cotofana:
Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links. 285-298 - Zhuoran Zhao, Andreas Gerstlauer, Lizy K. John:
Source-Level Performance, Energy, Reliability, Power and Thermal (PERPT) Simulation. 299-312 - Xin Lou, Ya Jun Yu, Pramod Kumar Meher:
Lower Bound Analysis and Perturbation of Critical Path for Area-Time Efficient Multiple Constant Multiplications. 313-324 - Ahish Mysore Somashekar, Spyros Tragoudas:
Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements. 325-335 - Jaeseok Park, Hyunyul Lim, Sungho Kang:
FRESH: A New Test Result Extraction Scheme for Fast TSV Tests. 336-345 - Liheng Zhu, Yasmine Badr, Shaodi Wang, Subramanian S. Iyer, Puneet Gupta:
Assessing Benefits of a Buried Interconnect Layer in Digital Designs. 346-350 - Irith Pomeranz:
Sequential Test Generation Based on Preferred Primary Input Cubes. 351-355
Volume 36, Number 3, March 2017
- Da-Wei Chang, Ing-Chao Lin, Lin-Chun Yong:
ROHOM: Requirement-Aware Online Hybrid On-Chip Memory Management for Multicore Systems. 357-369 - Sukanta Bhattacharjee, Sharbatanu Chatterjee, Ansuman Banerjee, Tsung-Yi Ho, Krishnendu Chakrabarty, Bhargab B. Bhattacharya:
Adaptation of Biochemical Protocols to Handle Technology-Change for Digital Microfluidics. 370-383 - Mohamed Ben Hammouda, Philippe Coussy, Loïc Lagadec:
A Unified Design Flow to Automatically Generate On-Chip Monitors During High-Level Synthesis of Hardware Accelerators. 384-397 - Miroslav Kvassay, Elena Zaitseva, Vitaly G. Levashenko, Jozef Kostolny:
Reliability Analysis of Multiple-Outputs Logic Circuits Based on Structure Function Approach. 398-411 - AmirMahdi Ahmadinejad, Hamid Zarrabi-Zadeh:
Finding Maximum Disjoint Set of Boundary Rectangles With Application to PCB Routing. 412-420 - Xiaochen Liu, Shupeng Sun, Xin Li, Haifeng Qian, Pingqiang Zhou:
Machine Learning for Noise Sensor Placement and Full-Chip Voltage Emergency Detection. 421-434 - Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, Luca P. Carloni:
System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip. 435-448 - Haoran Li, Xuan Wang, Jiang Xu, Zhe Wang, Rafael K. V. Maeda, Zhehui Wang, Peng Yang, Luan H. K. Duong, Zhifei Wang:
Energy-Efficient Power Delivery System Paradigms for Many-Core Processors. 449-462 - Ronald Shawn Blanton, Fa Wang, Cheng Xue, Pranab K. Nag, Yang Xue, Xin Li:
DFM Evaluation Using IC Diagnosis Data. 463-474 - Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso:
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. 475-488 - Mohammad Fawaz, Farid N. Najm:
Fast Vectorless RLC Grid Verification. 489-502 - Irith Pomeranz:
LFSR-Based Generation of Multicycle Tests. 503-507 - Elishai Ezra Tsur:
Computer Aided Design of a Microscale Digitally Controlled Hydraulic Resistor. 508-512 - Chao Wang, Lei Gong, Qi Yu, Xi Li, Yuan Xie, Xuehai Zhou:
DLAU: A Scalable Deep Learning Accelerator Unit on FPGA. 513-517
Volume 36, Number 4, April 2017
- Zheng Zhang, Kim Batselier, Haotian Liu, Luca Daniel, Ngai Wong:
Tensor Computation: A New Framework for High-Dimensional Problems in EDA. 521-536 - Ranjan Pal, Viktor K. Prasanna:
The STREAM Mechanism for CPS Security The Case of the Smart Grid. 537-550 - Ta-Yang Huang, Chia-Jui Chang, Chung-Wei Lin, Sudip Roy, Tsung-Yi Ho:
Delay-Bounded Intravehicle Network Routing Algorithm for Minimization of Wiring Weight and Wireless Transmit Power. 551-561 - Jin Huang, Qingmin Huang, Yangdong Deng, Ye-Hwa Chen:
Toward Robust Vehicle Platooning With Bounded Spacing Error. 562-572 - Hantao Huang, Yuehua Cai, Hang Xu, Hao Yu:
A Multiagent Minority-Game-Based Demand-Response Management of Smart Buildings Toward Peak Load Reduction. 573-585 - Wanli Chang, Dip Goswami, Samarjit Chakraborty, Lei Ju, Chun Jason Xue, Sidharta Andalam:
Memory-Aware Embedded Control Systems Design. 586-599 - Joon-Young Paik, Tae-Sun Chung, Eun-Sun Cho:
Dynamic Allocation Mechanism to Reduce Read Latency in Collaboration With a Device Queue in Multichannel Solid-State Devices. 600-613 - Sukanta Bhattacharjee, Sudip Poddar, Sudip Roy, Juinn-Dar Huang, Bhargab B. Bhattacharya:
Dilution and Mixing Algorithms for Flow-Based Microfluidic Biochips. 614-627 - Vivek Mishra, Sachin S. Sapatnekar:
Probabilistic Wire Resistance Degradation Due to Electromigration in Power Grids. 628-640 - Juyeon Kim, Taewhan Kim:
Adjustable Delay Buffer Allocation under Useful Clock Skew Scheduling. 641-654 - Anirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty:
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis. 655-668 - Mladen Skelin, Marc Geilen, Francky Catthoor, Sverre Hendseth:
Parameterized Dataflow Scenarios. 669-682 - Grzegorz Mrugalski, Janusz Rajski, Lukasz Rybak, Jedrzej Solecki, Jerzy Tyszer:
Star-EDT: Deterministic On-Chip Scheme Using Compressed Test Patterns. 683-693 - Matthias Kauer, Swaminathan Narayanaswamy, Sebastian Steinhorst, Samarjit Chakraborty:
Rapid Analysis of Active Cell Balancing Circuits. 694-698 - Endri Bezati, Simone Casale Brunet, Marco Mattavelli, Jörn W. Janneck:
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs. 699-703
Volume 36, Number 5, May 2017
- Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li:
Retention-Aware DRAM Assembly and Repair for Future FGR Memories. 705-718 - Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Design-Space Exploration and Optimization of an Energy-Efficient and Reliable 3-D Small-World Network-on-Chip. 719-732 - Mohamed Ibrahim, Krishnendu Chakrabarty, Kristin Scott:
Synthesis of Cyberphysical Digital-Microfluidic Biochips for Real-Time Quantitative Analysis. 733-746 - Onur Tunali, Mustafa Altun:
Permanent and Transient Fault Tolerance for Reconfigurable Nano-Crossbar Arrays. 747-760 - Felix Winterstein, Kermin Elliott Fleming, Hsin-Jung Yang, George A. Constantinides:
Custom Multicache Architectures for Heap Manipulating Programs. 761-774 - Khalid Al-Jabery, Zhezhao Xu, Wenjian Yu, Donald C. Wunsch, Jinjun Xiong, Yiyu Shi:
Demand-Side Management of Domestic Electric Water Heaters Using Approximate Dynamic Programming. 775-788 - Luc Michel, Frédéric Pétrot:
Dynamic Binary Translation of VLIW Codes on Scalar Architectures. 789-800 - José L. Abellán, Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Cristian Morales, John Recchio, Vaishnav Srinivas, Tiansheng Zhang:
Adaptive Tuning of Photonic Devices in a Photonic NoC Through Dynamic Workload Allocation. 801-814 - Yongkun Li, Biaobiao Shen, Yubiao Pan, Yinlong Xu, Zhipeng Li, John C. S. Lui:
Workload-Aware Elastic Striping With Hot Data Identification for SSD RAID Arrays. 815-828 - Eric Schneider, Michael A. Kochte, Stefan Holst, Xiaoqing Wen, Hans-Joachim Wunderlich:
GPU-Accelerated Simulation of Small Delay Faults. 829-841 - Mehdi Sadi, Sukeshwar Kannan, LeRoy Winemberg, Mark Tehranipoor:
SoC Speed Binning Using Machine Learning and On-Chip Slack Sensors. 842-854 - Xiaoxiao Wang, Pengyuan Jiao, Mehdi Sadi, Donglin Su, LeRoy Winemberg, Mark Tehranipoor:
TRO: An On-Chip Ring Oscillator-Based GHz Transient IR-Drop Monitor. 855-868 - Fatemeh Negin Javaheri, Katell Morin-Allory, Dominique Borrione:
Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware. 869-882
Volume 36, Number 6, June 2017
- Li-C. Wang:
Experience of Data Analytics in EDA and Test - Principles, Promises, and Challenges. 885-898 - Wei Zeng, Hengliang Zhu, Xuan Zeng, Dian Zhou, Ruey-Wen Liu, Xin Li:
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations. 899-912 - Yasmine Badr, Andres Torres, Puneet Gupta:
Mask Assignment and DSA Grouping for DSA-MP Hybrid Lithography for Sub-7 nm Contact/Via Holes. 913-926 - Konrad Möller, Martin Kumm, Marco Kleinlein, Peter Zipf:
Reconfigurable Constant Multiplication for FPGAs. 927-937 - Frank P. Burns, Danil Sokolov, Alex Yakovlev:
A Structured Visual Approach to GALS Modeling and Verification of Communication Circuits. 938-951 - Jin-Tai Yan:
One-Sided Net Untangling With Internal Detours for Bus Routing. 952-963 - Yu-Hsuan Su, Yao-Wen Chang:
Nanowire-Aware Routing Considering High Cut Mask Complexity. 964-977 - Elena Kakoulli, Vassos Soteriou, Charalambos Koutsides, Kyriacos Kalli:
Silica-Embedded Silicon Nanophotonic On-Chip Networks. 978-991 - Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, Sung Kyu Lim:
Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs. 992-1003 - Wen-Hsuan Hsu, Michael Andreas Kochte, Kuen-Jong Lee:
Built-In Test and Diagnosis for TSVs With Different Placement Topologies and Crosstalk Impact Ranges. 1004-1017 - Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis:
More Efficient Testing of Metal-Oxide Memristor-Based Memory. 1018-1029 - Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty:
ExTest Scheduling and Optimization for 2.5-D SoCs With Wrapped Tiles. 1030-1042 - Chandra K. H. Suresh, Sule Ozev, Ozgur Sinanoglu:
Adaptive Reduction of the Frequency Search Space for Multi-Vdd Digital Circuits Using Variation Sensitive Ring Oscillators. 1043-1053 - Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra, Jörg Henkel:
Optimal Greedy Algorithm for Many-Core Scheduling. 1054-1058
Volume 36, Number 7, July 2017
- Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano:
ToPoliNano: A CAD Tool for Nano Magnetic Logic. 1061-1074 - Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. 1075-1088 - Kan Wang, Sheqin Dong, Fengxian Jiao:
TSF3D: MSV-Driven Power Optimization for Application-Specific 3D Network-on-Chip. 1089-1102 - Wai-Kei Mak, Wan-Sin Kuo, Shi-Han Zhang, Seong-I Lei, Chris Chu:
Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. 1103-1112 - Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan:
Redundant Local-Loop Insertion for Unidirectional Routing. 1113-1125 - Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. 1126-1139 - Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. 1140-1152 - Mohamad Najem, Pascal Benoit, Mohamad El Ahmad, Gilles Sassatelli, Lionel Torres:
A Design-Time Method for Building Cost-Effective Run-Time Power Monitoring. 1153-1166 - Jie Guo, Wujie Wen, Jingtong Hu, Danghui Wang, Hai Helen Li, Yiran Chen:
FlexLevel NAND Flash Storage System Design to Reduce LDPC Latency. 1167-1180 - Yaojun Zhang, Bonan Yan, Xiaobin Wang, Yiran Chen:
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. 1181-1192 - Eddie Hung, Tim Todman, Wayne Luk:
Transparent In-Circuit Assertions for FPGAs. 1193-1202 - Renhai Chen, Yi Wang, Jingtong Hu, Duo Liu, Zili Shao, Yong Guan:
vFlash: Virtualized Flash for Optimizing the I/O Performance in Mobile Devices. 1203-1214 - Irith Pomeranz:
Identifying Biases of a Defect Diagnosis Procedure. 1215-1225 - Xiaoping Wang, Bowen Xu, Lin Chen:
Efficient Memristor Model Implementation for Simulation and Application. 1226-1230 - Irith Pomeranz:
Clock Sequences for Increasing the Fault Coverage of Functional Test Sequences. 1231-1235
Volume 36, Number 8, August 2017
- Wen-Hsiang Chang, Chien-Hsueh Lin, Szu-Pang Mu, Li-De Chen, Cheng-Hong Tsai, Yen-Chih Chiu, Mango C.-T. Chao:
Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique. 1237-1250 - Hsiao-Lei Chien, Mei-Yen Chiu, Jie-Hong R. Jiang:
A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning. 1251-1264 - Shreepad Panth, Sandeep Kumar Samal, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes. 1265-1273 - Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin, Nai-Chen Chen:
Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing. 1274-1286 - Qi Xu, Song Chen, Xiaodong Xu, Bei Yu:
Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits. 1287-1300 - Daohang Shi, Edward Tashjian, Azadeh Davoodi:
Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment. 1301-1312 - Tsun-Ming Tseng, Bing Li, Ching-Feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann:
An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation. 1313-1326 - Ming Tang, Zhipeng Guo, Annelie Heuser, Yanzhen Ren, Jie Li, Jean-Luc Danger:
PFD - A Flexible Higher-Order Masking Scheme. 1327-1339 - Edwin Hsing-Mean Sha, Congming Gao, Liang Shi, Kaijie Wu, Mengying Zhao, Chun Jason Xue:
Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems. 1340-1352 - Miao Hu, Yiran Chen, J. Joshua Yang, Yu Wang, Hai Helen Li:
A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks. 1353-1366 - Vicky S. Kalogeiton, Dim P. Papadopoulos, Orestis Liolis, Vasilios A. Mardiris, Georgios Ch. Sirakoulis, Ioannis G. Karafyllidis:
Programmable Crossbar Quantum-Dot Cellular Automata Circuits. 1367-1380 - Yixiao Ding, Chris Chu, Wai-Kei Mak:
Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment. 1381-1394 - Xuan Dong, Lihong Zhang:
Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration. 1395-1405 - Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty:
Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs. 1406-1419
Volume 36, Number 9, September 2017
- Sanjit A. Seshia, Shiyan Hu, Wenchao Li, Qi Zhu:
Design Automation of Cyber-Physical Systems: Challenges, Advances, and Opportunities. 1421-1434 - Nicole Fern, Ismail San, Çetin Kaya Koç, Kwang-Ting (Tim) Cheng:
Hiding Hardware Trojan Communication Channels in Partially Specified SoC Bus Functionality. 1435-1444 - Wei Yan, Fatemeh Tehranipoor, John A. Chandy:
PUF-Based Fuzzy Authentication Without Error Correcting Codes. 1445-1457 - Hoda Aghaei Khouzani, Fateme S. Hosseini, Chengmo Yang:
Segment and Conflict Aware Page Allocation and Migration in DRAM-PCM Hybrid Main Memory. 1458-1470 - Bajaj Ronak, Suhaib A. Fahmy:
Multipumping Flexible DSP Blocks for Resource Reduction on Xilinx FPGAs. 1471-1482 - Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Transistor Count Optimization in IG FinFET Network Design. 1483-1496 - Hyungmin Cho, Eric Cheng, Thomas Shepherd, Chen-Yong Cher, Subhasish Mitra:
System-Level Effects of Soft Errors in Uncore Components. 1497-1510 - Woong Choi, Jongsun Park:
Improved Perturbation Vector Generation Method for Accurate SRAM Yield Estimation. 1511-1521 - Seongbo Shim, Youngsoo Shin:
Fast Verification of Guide-Patterns for Directed Self-Assembly Lithography. 1522-1531 - Yibo Lin, Bei Yu, David Z. Pan:
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. 1532-1544 - Fan Yang, Subarna Sinha, Charles C. Chiang, Xuan Zeng, Dian Zhou:
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification. 1545-1556 - Pietro Mercati, Francesco Paterna, Andrea Bartolini, Luca Benini, Tajana Simunic Rosing:
WARM: Workload-Aware Reliability Management in Linux/Android. 1557-1570 - Taehee Lee, Nur A. Touba, Joon-Sung Yang:
Enhancing Test Compression With Dependency Analysis for Multiple Expansion Ratios. 1571-1579 - Hyunseung Han, Nur A. Touba, Joon-Sung Yang:
Exploiting Unused Spare Columns and Replaced Columns to Enhance Memory ECC. 1580-1591
Volume 36, Number 10, October 2017
- Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, Ankur Srivastava:
TSV-Based 3-D ICs: Design Methods and Tools. 1593-1619 - Rodrigo Alves De Lima Moreto, Carlos Eduardo Thomaz, Salvador Pinillos Gimenez:
Gaussian Fitness Functions for Optimizing Analog CMOS Integrated Circuits. 1620-1632 - Xiaoming Chen, Lin Wang, Yu Wang, Yongpan Liu, Huazhong Yang:
A General Framework for Hardware Trojan Detection in Digital Circuits by Statistical Learning Algorithms. 1633-1646 - Cunxi Yu, Xiangyu Zhang, Duo Liu, Maciej J. Ciesielski, Daniel E. Holcomb:
Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits. 1647-1659 - Yongpan Liu, Jinshan Yue, Hehe Li, Qinghang Zhao, Mengying Zhao, Chun Jason Xue, Guangyu Sun, Meng-Fan Chang, Huazhong Yang:
Data Backup Optimization for Nonvolatile SRAM in Energy Harvesting Sensor Nodes. 1660-1673 - Jincheng Su, Fan Yang, Xuan Zeng, Dian Zhou, Jie Chen:
Efficient Memory Partitioning for Parallel Data Access in FPGA via Data Reuse. 1674-1687 - Deepashree Sengupta, Sachin S. Sapatnekar:
Estimating Circuit Aging Due to BTI and HCI Using Ring-Oscillator-Based Sensors. 1688-1701 - Sara Vinco, Yukai Chen, Franco Fummi, Enrico Macii, Massimo Poncino:
A Layered Methodology for the Simulation of Extra-Functional Properties in Smart Systems. 1702-1715 - Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim:
Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs. 1716-1724 - Nezam Rohbani, Zahra Shirmohammadi, Maryam Zare, Seyed Ghassem Miremadi:
LAXY: A Location-Based Aging-Resilient Xy-Yx Routing Algorithm for Network on Chip. 1725-1738 - Irith Pomeranz:
Restoration-Based Merging of Functional Test Sequences. 1739-1749 - Srivatsan Subramanian, Mehran Mozaffari Kermani, Reza Azarderakhsh, Mehrdad Nojoumian:
Reliable Hardware Architectures for Cryptographic Block Ciphers LED and HIGHT. 1750-1758 - Young-Woo Lee, Hyeonchan Lim, Sungho Kang:
Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs. 1759-1763
Volume 36, Number 11, November 2017
- Guoyong Shi:
Topological Approach to Symbolic Pole-Zero Extraction Incorporating Design Knowledge. 1765-1778 - Ming Tang, Zhenlong Qiu, Zhipeng Guo, Yi Mu, Xinyi Huang, Jean-Luc Danger:
A Generic Table Recomputation-Based Higher-Order Masking. 1779-1789 - Peter Waszecki, Philipp Mundhenk, Sebastian Steinhorst, Martin Lukasiewycz, Ramesh Karri, Samarjit Chakraborty:
Automotive Electrical and Electronic Architecture Security via Distributed In-Vehicle Traffic Monitoring. 1790-1803 - Mengying Zhao, Chenchen Fu, Zewei Li, Qing'an Li, Mimi Xie, Yongpan Liu, Jingtong Hu, Zhiping Jia, Chun Jason Xue:
Stack-Size Sensitive On-Chip Memory Backup for Self-Powered Nonvolatile Processors. 1804-1816 - Gai Liu, Mingxing Tan, Steve Dai, Ritchie Zhao, Zhiru Zhang:
Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests. 1817-1830 - Ben Schaeffer:
Product Transformation and Heuristic EXOR-AND-OR Logic Synthesis of Incompletely Specified Functions. 1831-1841 - Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Exact Synthesis of Majority-Inverter Graphs and Its Applications. 1842-1855 - Jai-Ming Lin, Jung-An Yang:
Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D ICs. 1856-1868 - Yuxiang Fu, Li Li, Kun Wang, Chuan Zhang:
Kalman Predictor-Based Proactive Dynamic Thermal Management for 3-D NoC Systems With Noisy Thermal Sensors. 1869-1882 - Ivan Ukhov, Petru Eles, Zebo Peng:
Probabilistic Analysis of Electronic Systems via Adaptive Hierarchical Interpolation. 1883-1896 - Ermao Cai, Diana Marculescu:
Temperature Effect Inversion-Aware Power-Performance Optimization for FinFET-Based Multicore Systems. 1897-1910 - Fotis Vartziotis, Xrysovalantis Kavousianos, Panagiotis Georgiou, Krishnendu Chakrabarty:
A Branch-&-Bound Test-Access-Mechanism Optimization Method for Multi-Vdd SoCs. 1911-1924 - Mahdieh Grailoo, Bijan Alizadeh, Behjat Forouzandeh:
Improved Range Analysis in Fixed-Point Polynomial Data-Path. 1925-1929
Volume 36, Number 12, December 2017
- Vijaykrishnan Narayanan:
Editorial. 1933 - Mousumi Bhanja, Baidya Nath Ray:
Synthesis Procedure of Configurable Building Block-Based Linear and Nonlinear Analog Circuits. 1940-1953 - Michael Zwerger, Maximilian Neuner, Helmut Graeb:
Analog Power-Down Synthesis. 1954-1967 - Abhishek Chakraborty, Bodhisatwa Mazumdar, Debdeep Mukhopadhyay:
A Combined Power and Fault Analysis Attack on Protected Grain Family of Stream Ciphers. 1968-1977 - Sangyun Oh, Hongsik Lee, Jongeun Lee:
Efficient Execution of Stream Graphs on Coarse-Grained Reconfigurable Architectures. 1978-1988 - Yongxiang Bao, Mingsong Chen, Qi Zhu, Tongquan Wei, Frédéric Mallet, Tingliang Zhou:
Quantitative Performance Evaluation of Uncertainty-Aware Hybrid AADL Designs Using Statistical Model Checking. 1989-2002 - Duo Liu, Yi Lin, Po-Chun Huang, Xiao Zhu, Liang Liang:
Durable and Energy Efficient In-Memory Frequent-Pattern Mining. 2003-2016 - Priyadarshini Panda, Aayush Ankit, Parami Wijesinghe, Kaushik Roy:
FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition. 2017-2029 - Cong Hao, Nan Wang, Takeshi Yoshimura:
A Unified Scheduling Approach for Power and Resource Optimization With Multiple Vdd or/and Vth in High-Level Synthesis. 2030-2043 - German Agustin Patterson, Jordi Suñé, Enrique Miranda:
Voltage-Driven Hysteresis Model for Resistive Switching: SPICE Modeling and Circuit Applications. 2044-2051 - Yu-Min Lee, Chia-Tung Ho:
InTraSim: Incremental Transient Simulation of Power Grids. 2052-2065 - Zhi-Wen Lin, Yao-Wen Chang:
Cut Redistribution With Directed-Self-Assembly Templates for Advanced 1-D Gridded Layouts. 2066-2079 - Iris Hui-Ru Jiang, Hua-Yu Chang:
Multiple Patterning Layout Decomposition Considering Complex Coloring Rules and Density Balancing. 2080-2092 - Gang Wu, Chris Chu:
Two Approaches for Timing-Driven Placement by Lagrangian Relaxation. 2093-2105 - Yun Liang, Wai Teng Tang, Ruizhe Zhao, Mian Lu, Huynh Phung Huynh, Rick Siow Mong Goh:
Scale-Free Sparse Matrix-Vector Multiplication on Many-Core Architectures. 2106-2119 - Ali Ahmadi, Haralampos-G. D. Stratigopoulos, Ke Huang, Amit Nahar, Bob Orr, Michael Pas, John M. Carulli, Yiorgos Makris:
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations. 2120-2133 - Arman Roohi, Ramtin Zand, Deliang Fan, Ronald F. DeMara:
Voltage-Based Concatenatable Full Adder Using Spin Hall Effect Switching. 2134-2138 - Irith Pomeranz:
Close-to-Functional Broadside Tests With a Safety Margin. 2139-2143 - Yanwen Guo, Xiaoping Wang, Zhigang Zeng:
A Compact Memristor-CMOS Hybrid Look-Up-Table Design and Potential Application in FPGA. 2144-2148 - Weize Yu, Selçuk Köse:
False Key-Controlled Aggressive Voltage Scaling: A Countermeasure Against LPA Attacks. 2149-2153
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