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ORCIDDavid Z. Pan
David Zhigang Pan
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- affiliation: University of Texas at Austin, USA
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2020 – today
- 2020
[j90]Jing Chen
, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo, David Z. Pan:
Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks. IEEE Access 8: 25372-25382 (2020)- [j89]David Z. Pan:
Report on the 38th ACM/IEEE International Conference on Computer-Aided Design (ICCAD 2019). IEEE Des. Test 37(2): 121-122 (2020) - [j88]Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55(3): 666-679 (2020) - [j87]Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun:
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits 55(4): 1011-1022 (2020) - [j86]Shaolan Li, David Z. Pan, Nan Sun:
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits 55(5): 1337-1350 (2020) - [j85]Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun:
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(11): 3064-3075 (2020) - [j84]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semisupervised Hotspot Detection With Self-Paced Multitask Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1511-1523 (2020) - [j83]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement With Unconventional Timing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4482-4495 (2020) - [j82]Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan:
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5083-5096 (2020) - [j81]Taehyun Kwon, Muhammad Imran, David Z. Pan, Joon-Sung Yang:
Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1256-1268 (2020) - [c221]Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan:
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC 2020: 26-31 - [c220]Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c219]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Mingjie Liu, Ray T. Chen, David Z. Pan:
Towards Area-Efficient Optical Neural Networks: An FFT-based Architecture. ASP-DAC 2020: 476-481 - [c218]Mohamed Baker Alawieh, Duane Boning, David Z. Pan:
Wafer Map Defect Patterns Classification using Deep Selective Learning. DAC 2020: 1-6 - [c217]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Wuxi Li, Ray T. Chen, David Z. Pan:
FLOPS: EFficient On-Chip Learning for OPtical Neural Networks Through Stochastic Zeroth-Order Optimization. DAC 2020: 1-6 - [c216]Navid Khoshavi, Arman Roohi, Connor Broyles, Saman Sargolzaei, Yu Bi, David Z. Pan:
SHIELDeNN: Online Accelerated Framework for Fault-Tolerant Deep Neural Network Architectures. DAC 2020: 1-6 - [c215]Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan:
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC 2020: 1-6 - [c214]Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE 2020: 496-501 - [c213]Jiaqi Gu, Zheng Zhao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan:
ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit Controls. DATE 2020: 1586-1589 - [c212]Zixuan Jiang, Keren Zhu, Mingjie Liu, Jiaqi Gu, David Z. Pan:
An Efficient Training Framework for Reversible Neural Architectures. ECCV (27) 2020: 275-289 - [c211]Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan:
TEMPO: Fast Mask Topography Effect Modeling with Deep Learning. ISPD 2020: 127-134 - [c210]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC 2020: 162-164 - [c209]Raviv Gal, David Z. Pan, Haoxing Ren, Manish Pandey, Marilyn Wolf, Avi Ziv:
ML for CAD - Where is the Treasure Hiding? MLCAD 2020: 137 - [c208]Keren Zhu, Mingjie Liu, Hao Chen, Zheng Zhao, David Z. Pan:
Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network. MLCAD 2020: 145-150 - [i18]Grace Li Zhang, Bing Li, Meng Li, Bei Yu, David Z. Pan, Michaela Brunner, Georg Sigl, Ulf Schlichtmann:
TimingCamouflage+: Netlist Security Enhancement with Unconventional Timing (with Appendix). CoRR abs/2003.00862 (2020)
2010 – 2019
- 2019
- [j80]Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(6): 1147-1160 (2019) - [j79]Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan:
Provably Secure Camouflaging Strategy for IC Protection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1399-1412 (2019) - [j78]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1585-1598 (2019) - [j77]Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan:
Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1900-1913 (2019) - [j76]Wuxi Li, David Z. Pan:
A New Paradigm for FPGA Placement Without Explicit Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2113-2126 (2019) - [j75]Kaveh Shamsi, Travis Meade, Meng Li, David Z. Pan, Yier Jin:
On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes. IEEE Trans. Inf. Forensics Secur. 14(2): 347-359 (2019) - [j74]Kaveh Shamsi, Meng Li, Kenneth Plaks, Saverio Fazzari, David Z. Pan, Yier Jin:
IP Protection and Supply Chain Security through Logic Obfuscation: A Systematic Overview. ACM Trans. Design Autom. Electr. Syst. 24(6): 65:1-65:36 (2019) - [c207]Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON 2019: 1-4 - [c206]Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
Tackling signal electromigration with learning-based detection and multistage mitigation. ASP-DAC 2019: 167-172 - [c205]Mohamed Baker Alawieh, Xiyuan Tang, David Z. Pan:
S2-PM: semi-supervised learning for efficient performance modeling of analog and mixed signal circuits. ASP-DAC 2019: 268-273 - [c204]Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan:
LithoROC: lithography hotspot detection with explicit ROC optimization. ASP-DAC 2019: 292-298 - [c203]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semi-supervised hotspot detection with self-paced multi-task learning. ASP-DAC 2019: 420-425 - [c202]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
A shape-driven spreading algorithm using linear programming for global placement. ASP-DAC 2019: 563-568 - [c201]Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan:
Hardware-software co-design of slimmed optical neural networks. ASP-DAC 2019: 705-710 - [c200]Shaolan Li, Biying Xu, David Z. Pan, Nan Sun:
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC 2019: 1-4 - [c199]Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC 2019: 1-3 - [c198]Mohamed Baker Alawieh, Sinead A. Williamson, David Z. Pan:
Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab Models. DAC 2019: 65 - [c197]Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan:
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC 2019: 66 - [c196]Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. DAC 2019: 107 - [c195]Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan:
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. DAC 2019: 117 - [c194]Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan:
GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks. DAC 2019: 149 - [c193]Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, David Z. Pan:
Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection. DATE 2019: 54-59 - [c192]Kaveh Shamsi, Meng Li, David Z. Pan, Yier Jin:
KC2: Key-Condition Crunching for Fast Sequential Circuit Deobfuscation. DATE 2019: 534-539 - [c191]Zheng Zhao, Derong Liu, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen, David Z. Pan:
Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis. DATE 2019: 1567-1570 - [c190]Wuxi Li, Mehrdad E. Dehkordi, Stephen Yang, David Z. Pan:
Simultaneous Placement and Clock Tree Construction for Modern FPGAs. FPGA 2019: 132-141 - [c189]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
FPGA Accelerated FPGA Placement. FPL 2019: 404-410 - [c188]Kaveh Shamsi, David Z. Pan, Yier Jin:
On the Impossibility of Approximation-Resilient Circuit Locking. HOST 2019: 161-170 - [c187]Shounak Dhar, Love Singhal, Mahesh A. Iyer, David Z. Pan:
FPGA-Accelerated Spreading for Global Placement. HPEC 2019: 1-7 - [c186]ChengYue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan:
Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning. ICCAD 2019: 1-7 - [c185]Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c184]Kaveh Shamsi, David Z. Pan, Yier Jin:
IcySAT: Improved SAT-based Attacks on Cyclic Locked Circuits. ICCAD 2019: 1-7 - [c183]Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD 2019: 1-8 - [c182]Zheng Zhao, Jiaqi Gu, Zhoufeng Ying, Chenghao Feng, Ray T. Chen, David Z. Pan:
Design Technology for Scalable and Robust Photonic Integrated Circuits: Invited Paper. ICCAD 2019: 1-7 - [c181]Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD 2019: 1-8 - [c180]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - [e3]David Z. Pan:
Proceedings of the International Conference on Computer-Aided Design, ICCAD 2019, Westminster, CO, USA, November 4-7, 2019. ACM 2019, ISBN 9781728123509 [contents] - 2018
- [j73]Sri Parameswaran, R. Iris Bahar, David Z. Pan:
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). IEEE Des. Test 35(2): 101-102 (2018) - [j72]Shaolan Li, Bo Qiao, Miguel Gandara, David Z. Pan, Nan Sun:
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits 53(12): 3484-3496 (2018) - [j71]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 231-244 (2018) - [j70]Taehee Lee, David Z. Pan, Joon-Sung Yang:
Clock Network Optimization With Multibit Flip-Flop Generation Considering Multicorner Multimode Timing Constraint. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(1): 245-256 (2018) - [j69]Hengliang Zhu, Feng Hu, Hao Zhou, David Z. Pan, Dian Zhou, Xuan Zeng:
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 770-781 (2018) - [j68]Wuxi Li, Shounak Dhar, David Z. Pan:
UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(4): 869-882 (2018) - [j67]Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan:
Subresolution Assist Feature Generation With Supervised Data Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1225-1236 (2018) - [j66]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018) - [j65]Yibo Lin, Bei Yu, Meng Li, David Z. Pan:
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1574-1587 (2018) - [j64]Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan:
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine. ACM Trans. Design Autom. Electr. Syst. 23(4): 42:1-42:23 (2018) - [j63]Hao Zhou, Hengliang Zhu, Tao Cui, David Z. Pan, Dian Zhou, Xuan Zeng:
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1312-1325 (2018) - [j62]Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng:
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1613-1626 (2018) - [j61]Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu:
Graph-Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2504-2517 (2018) - [c179]Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan:
Layout-dependent aging mitigation for critical path timing. ASP-DAC 2018: 153-158 - [c178]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. ASP-DAC 2018: 265-270 - [c177]Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan:
Logic synthesis for energy-efficient photonic integrated circuits. ASP-DAC 2018: 355-360 - [c176]Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan:
OPERON: optical-electrical power-efficient route synthesis for on-chip signals. DAC 2018: 75:1-75:6 - [c175]Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann:
TimingCamouflage: Improving circuit security against counterfeiting by unconventional timing. DATE 2018: 91-96 - [c174]Kaveh Shamsi, Meng Li, David Z. Pan, Yier Jin:
Cross-Lock: Dense Layout-Level Interconnect Locking using Cross-bar Architectures. ACM Great Lakes Symposium on VLSI 2018: 147-152 - [c173]Shounak Dhar, David Z. Pan:
GDP: GPU accelerated Detailed Placement. HPEC 2018: 1-7 - [c172]Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan:
Power Grid Reduction by Sparse Convex Optimization. ISPD 2018: 60-67 - [c171]Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan:
Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning. ISPD 2018: 82-89 - [c170]Biying Xu, Bulent Basaran, Ming Su, David Z. Pan:
Analog Placement Constraint Extraction and Exploration with the Application to Layout Retargeting. ISPD 2018: 98-105 - [c169]Meng Li, Kaveh Shamsi, Yier Jin, David Z. Pan:
TimingSAT: Decamouflaging Timing-based Logic Obfuscation. ITC 2018: 1-10 - [c168]Yibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan:
Machine Learning for Yield Learning and Optimization. ITC 2018: 1-10 - [c167]David Z. Pan:
Machine learning for IC design and technology co-optimization in extreme scaling. VLSI-DAT 2018: 1 - [i17]Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan:
Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection. CoRR abs/1807.03257 (2018) - [i16]Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer. CoRR abs/1809.07554 (2018) - 2017
- [j60]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58: 47-54 (2017) - [j59]Xiaoqing Xu, David Z. Pan:
Toward Unidirectional Routing Closure in Advanced Technology Nodes. IPSJ Trans. Syst. LSI Des. Methodol. 10: 2-12 (2017) - [j58]Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan:
Redundant Local-Loop Insertion for Unidirectional Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1113-1125 (2017) - [j57]Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos:
Incremental Layer Assignment Driven by an External Signoff Timing Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1126-1139 (2017) - [j56]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1140-1152 (2017) - [j55]Yibo Lin, Bei Yu, David Z. Pan:
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1532-1544 (2017) - [j54]Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan:
Incremental Layer Assignment for Timing Optimization. ACM Trans. Design Autom. Electr. Syst. 22(4): 75:1-75:25 (2017) - [j53]Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng:
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation. ACM Trans. Design Autom. Electr. Syst. 23(1): 11:1-11:27 (2017) - [c166]Zheng Zhao, Zheng Wang, Zhoufeng Ying, Shounak Dhar, Ray T. Chen, David Z. Pan:
Optical computing on silicon-on-insulator-based photonic integrated circuits. ASICON 2017: 472-475 - [c165]Biying Xu, Shaolan Li, Nan Sun, David Z. Pan:
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. DAC 2017: 12:1-12:6 - [c164]Meng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan:
Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack. DAC 2017: 17:1-17:6 - [c163]Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. DAC 2017: 18:1-18:6 - [c162]Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan:
Concurrent Pin Access Optimization for Unidirectional Routing. DAC 2017: 20:1-20:6 - [c161]Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
Cyclic Obfuscation for Creating SAT-Unresolvable Circuits. ACM Great Lakes Symposium on VLSI 2017: 173-178 - [c160]Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail? ACM Great Lakes Symposium on VLSI 2017: 357-362 - [c159]Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
AppSAT: Approximately deobfuscating integrated circuits. HOST 2017: 95-100 - [c158]Wuxi Li, Meng Li, Jiajun Wang, David Z. Pan:
UTPlaceF 3.0: A parallelization framework for modern FPGA global placement: (Invited paper). ICCAD 2017: 922-928 - [c157]Jiaojiao Ou, Xiaoqing Xu, Brian Cline, Greg Yeric, David Z. Pan:
DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node. ICCD 2017: 403-410 - [c156]Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan:
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD 2017: 415-418 - [c155]Travis Meade, Zheng Zhao, Shaojie Zhang, David Z. Pan, Yier Jin:
Revisit sequential logic obfuscation: Attacks and defenses. ISCAS 2017: 1-4 - [c154]Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan, David Z. Pan:
Placement mitigation techniques for power grid electromigration. ISLPED 2017: 1-6 - [c153]Biying Xu, Shaolan Li, Xiaoqing Xu, Nan Sun, David Z. Pan:
Hierarchical and Analytical Placement Techniques for High-Performance Analog Circuits. ISPD 2017: 55-62 - [c152]Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan:
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. ISPD 2017: 91-98 - [c151]Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan:
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD 2017: 151-157 - [i15]Meng Li, Liangzhen Lai, Naveen Suda, Vikas Chandra, David Z. Pan:
PrivyNet: A Flexible Framework for Privacy-Preserving Deep Neural Network Training with A Fine-Grained Privacy Control. CoRR abs/1709.06161 (2017) - 2016
- [j52]Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan:
Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59(6): 061406:1-061406:23 (2016) - [j51]Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan:
Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(5): 820-831 (2016) - [j50]