"Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs."

Jae-Seok Yang et al. (2011)

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DOI: 10.1109/ASPDAC.2011.5722264

access: closed

type: Conference or Workshop Paper

metadata version: 2022-10-02

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  - https://dblp.org/rec/conf/aspdac/YangPZLP11
Jae-Seok Yang, Jiwoo Pak, Xin Zhao, Sung Kyu Lim, David Z. Pan:
Robust Clock Tree Synthesis with timing yield optimization for 3D-ICs. ASP-DAC 2011: 621-626

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