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"An Effective Timing-Driven Detailed Placement Algorithm for FPGAs."

Shounak Dhar et al. (2017)

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DOI: 10.1145/3036669.3036682

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/ispd/DharIASRP17
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  - https://dblp.org/rec/conf/ispd/DharIASRP17
Shounak Dhar, Mahesh A. Iyer, Saurabh N. Adya, Love Singhal, Nikolay Rubanov, David Z. Pan:
An Effective Timing-Driven Detailed Placement Algorithm for FPGAs. ISPD 2017: 151-157

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