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ORCIDJason Cong
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- affiliation: University of California, Los Angeles, USA
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2020 – today
- 2024
[j136]Daniel Bochen Tan
, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong:
Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. Quantum 8: 1281 (2024)- [j135]Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin:
Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1177-1190 (2024) - [j134]Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang:
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(3): 42:1-42:31 (2024) - [j133]Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Shixin Ji, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Yiyu Shi, Deming Chen, Jason Cong, Peipei Zhou:
CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture. ACM Trans. Reconfigurable Technol. Syst. 17(3): 51:1-51:31 (2024) - [c421]Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong:
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. ASPLOS (3) 2024: 966-980 - [c420]Daniel Bochen Tan, Shuohao Ping, Jason Cong:
Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. DATE 2024: 1-6 - [c419]Hanyu Wang, Jason Cong, Giovanni De Micheli:
Quantum State Preparation Using an Exact CNOT Synthesis Formulation. DATE 2024: 1-6 - [c418]Zifan He, Linghao Song, Robert F. Lucas, Jason Cong:
LevelST: Stream-based Accelerator for Sparse Triangular Solver. FPGA 2024: 67-77 - [c417]Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. FPGA 2024: 184 - [c416]Hanrui Wang, Pengyu Liu, Daniel Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han:
Atomique: A Quantum Compiler for Reconfigurable Neutral Atom Arrays. ISCA 2024: 293-309 - [c415]Jason Cong:
Scheduling and Physical Design. ISPD 2024: 219-225 - [c414]Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing Ren, Yizhou Sun, Jason Cong:
Learning to Compare Hardware Designs for High-Level Synthesis. MLCAD 2024: 2:1-2:7 - [c413]Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong:
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. MLCAD 2024: 14:1-14:12 - [i45]Hanyu Wang, Bochen Tan, Jason Cong, Giovanni De Micheli:
Quantum State Preparation Using an Exact CNOT Synthesis Formulation. CoRR abs/2401.01009 (2024) - [i44]Daniel Bochen Tan, Shuohao Ping, Jason Cong:
Depth-Optimal Addressing of 2D Qubit Array with 1D Controls Based on Exact Binary Matrix Factorization. CoRR abs/2401.13807 (2024) - [i43]Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
Enhancing High-Level Synthesis with Automated Pragma Insertion and Code Transformation Framework. CoRR abs/2405.03058 (2024) - [i42]Zifan He, Zongyue Qin, Neha Prakriya, Yizhou Sun, Jason Cong:
HMT: Hierarchical Memory Transformer for Long Context Language Processing. CoRR abs/2405.06067 (2024) - [i41]Stéphane Pouget, Louis-Noël Pouchet, Jason Cong:
Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach. CoRR abs/2405.12304 (2024) - [i40]Daniel Bochen Tan, Wan-Hsuan Lin, Jason Cong:
Compilation for Dynamically Field-Programmable Qubit Arrays with Efficient and Provably Near-Optimal Scheduling. CoRR abs/2405.15095 (2024) - [i39]Wan-Hsuan Lin, Jason Cong:
ML-QLS: Multilevel Quantum Layout Synthesis. CoRR abs/2405.18371 (2024) - [i38]Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong:
Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis. CoRR abs/2406.09606 (2024) - [i37]Zongyue Qin, Ziniu Hu, Zifan He, Neha Prakriya, Jason Cong, Yizhou Sun:
Multi-Token Joint Speculative Decoding for Accelerating Large Language Model Inference. CoRR abs/2407.09722 (2024) - [i36]Zijian Ding, Atefeh Sohrabizadeh, Weikai Li, Zongyue Qin, Yizhou Sun, Jason Cong:
Efficient Task Transfer for HLS DSE. CoRR abs/2408.13270 (2024) - [i35]Neha Prakriya, Jui-Nan Yen, Cho-Jui Hsieh, Jason Cong:
Accelerating Large Language Model Pretraining via LFR Pedagogy: Learn, Focus, and Review. CoRR abs/2409.06131 (2024) - [i34]Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Rongjian Liang, Weikai Li, Ding Wang, Haoxing Ren, Yizhou Sun, Jason Cong:
Learning to Compare Hardware Designs for High-Level Synthesis. CoRR abs/2409.13138 (2024) - [i33]Zongyue Qin, Zifan He, Neha Prakriya, Jason Cong, Yizhou Sun:
Dynamic-Width Speculative Beam Decoding for Efficient LLM Inference. CoRR abs/2409.16560 (2024) - 2023
- [j132]Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
Democratizing Domain-Specific Computing. Commun. ACM 66(1): 74-85 (2023) - [j131]Gert Cauwenberghs, Jason Cong, X. Sharon Hu, Siddharth Joshi, Subhasish Mitra, Wolfgang Porod, H.-S. Philip Wong:
Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. Proc. IEEE 111(6): 561-574 (2023) - [j130]Zhe Chen, Garrett J. Blair, Chengdi Cao, Jim Zhou, Daniel Aharoni, Peyman Golshani, Hugh T. Blair, Jason Cong:
FPGA-Based In-Vivo Calcium Image Decoding for Closed-Loop Feedback Applications. IEEE Trans. Biomed. Circuits Syst. 17(2): 169-179 (2023) - [j129]Young Kyu Choi, Yuze Chi, Jason Lau, Jason Cong:
TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2423-2427 (2023) - [j128]Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong:
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-Based FPGAs. IEEE Trans. Emerg. Top. Comput. 11(2): 404-419 (2023) - [j127]Young Kyu Choi, Carlos Santillana, Yujia Shen, Adnan Darwiche, Jason Cong:
FPGA Acceleration of Probabilistic Sentential Decision Diagrams with High-level Synthesis. ACM Trans. Reconfigurable Technol. Syst. 16(2): 18:1-18:22 (2023) - [j126]Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Licheng Guo, Jason Cong:
FlexCNN: An End-to-end Framework for Composing CNN Accelerators on FPGA. ACM Trans. Reconfigurable Technol. Syst. 16(2): 23:1-23:32 (2023) - [j125]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 16(4): 59:1-59:30 (2023) - [j124]Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong:
TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design. ACM Trans. Reconfigurable Technol. Syst. 16(4): 63:1-63:31 (2023) - [c412]Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Jason Cong:
Caffeine: Towards Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. ACM TUR-C 2023: 47-48 - [c411]Suhail Basalama, Jie Wang, Jason Cong:
A Comprehensive Automated Exploration Framework for Systolic Array Designs. DAC 2023: 1-6 - [c410]Jason Cong:
Lightning Talk: Scaling Up Quantum Compilation - Challenges and Opportunities. DAC 2023: 1-2 - [c409]Wan-Hsuan Lin, Jason Kimko, Bochen Tan, Nikolaj S. Bjørner, Jason Cong:
Scalable Optimal Layout Synthesis for NISQ Quantum Processors. DAC 2023: 1-6 - [c408]Zizhang Luo, Liqiang Lu, Size Zheng, Jieming Yin, Jason Cong, Jianwei Yin, Yun Liang:
Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. DAC 2023: 1-6 - [c407]Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang:
PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs. FCCM 2023: 12-22 - [c406]Michael Lo, Young-kyu Choi, Weikang Qiao, Mau-Chung Frank Chang, Jason Cong:
HMLib: Efficient Data Transfer for HLS Using Host Memory. FPGA 2023: 50 - [c405]Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou:
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture. FPGA 2023: 153-164 - [c404]Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong:
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. FPGA 2023: 247-258 - [c403]Neha Prakriya, Yu Yang, Baharan Mirzasoleiman, Cho-Jui Hsieh, Jason Cong:
NeSSA: Near-Storage Data Selection for Accelerated Machine Learning Training. HotStorage 2023: 8-15 - [c402]Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Robust GNN-Based Representation Learning for HLS. ICCAD 2023: 1-9 - [c401]Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, Jason Cong:
Towards a Comprehensive Benchmark for High-Level Synthesis Targeted to FPGAs. NeurIPS 2023 - [i32]Jinming Zhuang, Jason Lau, Hanchen Ye, Zhuoping Yang, Yubo Du, Jack Lo, Kristof Denolf, Stephen Neuendorffer, Alex K. Jones, Jingtong Hu, Deming Chen, Jason Cong, Peipei Zhou:
CHARM: Composing Heterogeneous Accelerators for Matrix Multiply on Versal ACAP Architecture. CoRR abs/2301.02359 (2023) - [i31]Jason Cong, Michalis Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie:
Locality and Utilization in Placement Suboptimality. CoRR abs/2305.16413 (2023) - [i30]Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong:
Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors. CoRR abs/2306.03487 (2023) - [i29]Shichang Zhang, Atefeh Sohrabizadeh, Cheng Wan, Zijie Huang, Ziniu Hu, Yewen Wang, Yingyan Lin, Jason Cong, Yizhou Sun:
A Survey on Graph Neural Network Acceleration: Algorithms, Systems, and Customized Hardware. CoRR abs/2306.14052 (2023) - [i28]Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong:
TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs. CoRR abs/2311.10189 (2023) - [i27]Hanrui Wang, Pengyu Liu, Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han:
FPQA-C: A Compilation Framework for Field Programmable Qubit Array. CoRR abs/2311.15123 (2023) - [i26]Hanrui Wang, Bochen Tan, Pengyu Liu, Yilian Liu, Jiaqi Gu, Jason Cong, Song Han:
Q-Pilot: Field Programmable Quantum Array Compilation with Flying Ancillas. CoRR abs/2311.16190 (2023) - 2022
- [j123]Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu, Jason Kimko, Jason Cong:
Domain-Specific Quantum Architecture Optimization. IEEE J. Emerg. Sel. Topics Circuits Syst. 12(3): 624-637 (2022) - [j122]Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong:
AutoDSE: Enabling Software Programmers to Design Efficient FPGA Accelerators. ACM Trans. Design Autom. Electr. Syst. 27(4): 32:1-32:27 (2022) - [j121]Zhe Chen, Hugh T. Blair, Jason Cong:
Energy-Efficient LSTM Inference Accelerator for Real-Time Causal Prediction. ACM Trans. Design Autom. Electr. Syst. 27(5): 44:1-44:19 (2022) - [j120]Jason Cong, Jason Lau, Gai Liu, Stephen Neuendorffer, Peichen Pan, Kees A. Vissers, Zhiru Zhang:
FPGA HLS Today: Successes, Challenges, and Opportunities. ACM Trans. Reconfigurable Technol. Syst. 15(4): 51:1-51:42 (2022) - [c400]Yuanhao Wu, Faruk V. Mutlu, Yuezhou Liu, Edmund Yeh, Ran Liu, Catalin Iordache, Justas Balcas, Harvey B. Newman, Raimondas Sirvinskas, Michael Lo, Sichen Song, Jason Cong, Lixia Zhang, Sankalpa Timilsina, Susmit Shannigrahi, Chengyu Fan, Davide Pesavento, Junxiao Shi, Lotfi Benmohamed:
N-DISE: NDN-based data distribution for large-scale data-intensive science. ICN 2022: 103-113 - [c399]Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing. CICC 2022: 1-8 - [c398]Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Automated accelerator optimization aided by graph neural networks. DAC 2022: 55-60 - [c397]Linghao Song, Yuze Chi, Licheng Guo, Jason Cong:
Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication. DAC 2022: 211-216 - [c396]Yunsheng Bai, Atefeh Sohrabizadeh, Yizhou Sun, Jason Cong:
Improving GNN-based accelerator design automation with meta learning. DAC 2022: 1347-1350 - [c395]Suhail Basalama, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
A Versatile Systolic Array for Transposed and Dilated Convolution on FPGA. FCCM 2022: 1-2 - [c394]Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong:
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. FCCM 2022: 1 - [c393]Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong:
RapidStream: Parallel Physical Implementation of FPGA HLS Designs. FPGA 2022: 1-12 - [c392]Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Automated Accelerator Optimization Aided by Graph Neural Networks. FPGA 2022: 50 - [c391]Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong:
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. FPGA 2022: 65-77 - [c390]Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation. FPGA 2022: 156 - [c389]Yuze Chi, Licheng Guo, Jason Cong:
Accelerating SSSP for Power-Law Graphs. FPGA 2022: 190-200 - [c388]Linghao Song, Yuze Chi, Jason Cong:
PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators. ICASSP 2022: 76-80 - [c387]Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong:
Qubit Mapping for Reconfigurable Atom Arrays. ICCAD 2022: 107:1-107:9 - [c386]Zhe Chen, Jim Zhou, Garrett J. Blair, Hugh T. Blair, Jason Cong:
Efficient Kernels for Real-Time Position Decoding from In Vivo Calcium Images. ISCAS 2022: 1872-1876 - [c385]Sihao Liu, Jian Weng, Dylan Kupsh, Atefeh Sohrabizadeh, Zhengrong Wang, Licheng Guo, Jiuyang Liu, Maxim Zhulin, Rishabh Mani, Lucheng Zhang, Jason Cong, Tony Nowatzki:
OverGen: Improving FPGA Usability through Domain-specific Overlay Generation. MICRO 2022: 35-56 - [i25]Weikang Qiao, Licheng Guo, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong:
TopSort: A High-Performance Two-Phase Sorting Accelerator Optimized on HBM-based FPGAs. CoRR abs/2205.07991 (2022) - [i24]Wan-Hsuan Lin, Bochen Tan, Murphy Yuezhen Niu, Jason Kimko, Jason Cong:
Domain-Specific Quantum Architecture Optimization. CoRR abs/2207.14482 (2022) - [i23]Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong:
TAPA: A Scalable Task-Parallel Dataflow Programming Framework for Modern FPGAs with Co-Optimization of HLS and Physical Design. CoRR abs/2209.02663 (2022) - [i22]Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
Democratizing Domain-Specific Computing. CoRR abs/2209.02951 (2022) - [i21]Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong:
Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver. CoRR abs/2209.14350 (2022) - 2021
- [j119]Bochen Tan, Jason Cong:
Optimality Study of Existing Quantum Computing Layout Synthesis Tools. IEEE Trans. Computers 70(9): 1363-1373 (2021) - [c384]Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong:
Fast Calcium Trace Extraction for Large-Field-of-View Miniscope. BioCAS 2021: 1-5 - [c383]Zhe Chen, Garrett J. Blair, Changliang Guo, Daniel Aharoni, Hugh T. Blair, Jason Cong:
Live Demonstration: Real-Time Calcium Trace Extraction from Large-Field-of-View Miniscope. BioCAS 2021: 1 - [c382]Weikang Qiao, Jihun Oh, Licheng Guo, Mau-Chung Frank Chang, Jason Cong:
FANS: FPGA-Accelerated Near-Storage Sorting. FCCM 2021: 106-114 - [c381]Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. FCCM 2021: 204-213 - [c380]Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra:
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. FMCAD 2021: 42-52 - [c379]Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong:
AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs. FPGA 2021: 81-92 - [c378]Jie Wang, Licheng Guo, Jason Cong:
AutoSA: A Polyhedral Compiler for High-Performance Systolic Arrays on FPGA. FPGA 2021: 93-104 - [c377]Young-kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, Jason Cong:
HBM Connect: High-Performance HLS Interconnect for FPGA HBM. FPGA 2021: 116-126 - [c376]Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong:
AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. FPGA 2021: 147 - [c375]Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. FPGA 2021: 225 - [c374]Peipei Zhou, Jiayi Sheng, Cody Hao Yu, Peng Wei, Jie Wang, Di Wu, Jason Cong:
MOCHA: Multinode Cost Optimization in Heterogeneous Clouds with Accelerators. FPGA 2021: 273-279 - [c373]Bochen Tan, Jason Cong:
Optimal Qubit Mapping with Simultaneous Gate Absorption ICCAD Special Session Paper. ICCAD 2021: 1-8 - [c372]Jason Cong:
From Parallelization to Customization - Challenges and Opportunities. IPDPS 2021: 682 - [c371]Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang:
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. ISCA 2021: 720-733 - [i20]Liqiang Lu, Naiqing Guan, Yuyue Wang, Liancheng Jia, Zizhang Luo, Jieming Yin, Jason Cong, Yun Liang:
TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. CoRR abs/2105.01892 (2021) - [i19]Saranyu Chattopadhyay, Florian Lonsing, Luca Piccolboni, Deepraj Soni, Peng Wei, Xiaofan Zhang, Yuan Zhou, Luca P. Carloni, Deming Chen, Jason Cong, Ramesh Karri, Zhiru Zhang, Caroline Trippel, Clark W. Barrett, Subhasish Mitra:
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition. CoRR abs/2108.06081 (2021) - [i18]Bochen Tan, Jason Cong:
Optimal Qubit Mapping with Simultaneous Gate Absorption. CoRR abs/2109.06445 (2021) - [i17]Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong:
Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication. CoRR abs/2109.11081 (2021) - [i16]Linghao Song, Yuze Chi, Jason Cong:
Pyxis: An Open-Source Performance Dataset of Sparse Accelerators. CoRR abs/2110.04280 (2021) - [i15]Atefeh Sohrabizadeh, Yuze Chi, Jason Cong:
SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation. CoRR abs/2111.05936 (2021) - [i14]Atefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong:
Enabling Automated FPGA Accelerator Optimization Using Graph Neural Networks. CoRR abs/2111.08848 (2021) - [i13]Linghao Song, Yuze Chi, Licheng Guo, Jason Cong:
Serpens: A High Bandwidth Memory Based Accelerator for General-Purpose Sparse Matrix-Vector Multiplication. CoRR abs/2111.12555 (2021) - [i12]Jie Wang, Jason Cong:
Search for Optimal Systolic Arrays: A Comprehensive Automated Exploration Framework and Lessons Learned. CoRR abs/2111.14252 (2021) - 2020
- [j118]Giovanni De Micheli, Antun Domic, Massimiliano Di Ventra, Martin Roettler, Jason Cong:
2019 DAC Roundtable. IEEE Des. Test 37(3): 100-114 (2020) - [j117]Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, Yuan Xie:
Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs. IEEE Trans. Computers 69(7): 931-943 (2020) - [j116]Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong:
FLASH: Fast, Parallel, and Accurate Simulator for HLS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4828-4841 (2020) - [j115]Meng Li, William Hsu, Xiaodong Xie, Jason Cong, Wen Gao:
SACNN: Self-Attention Convolutional Neural Network for Low-Dose CT Denoising With Self-Supervised Perceptual Loss Network. IEEE Trans. Medical Imaging 39(7): 2289-2301 (2020) - [c370]Yuze Chi, Jason Cong:
Exploiting Computation Reuse for Stencil Accelerators. DAC 2020: 1-6 - [c369]Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. DAC 2020: 1-6 - [c368]Eshan Singh, Florian Lonsing, Saranyu Chattopadhyay, Maxwell Strange, Peng Wei, Xiaofan Zhang, Yuan Zhou, Deming Chen, Jason Cong, Priyanka Raina, Zhiru Zhang, Clark W. Barrett, Subhasish Mitra:
A-QED Verification of Hardware Accelerators. DAC 2020: 1-6 - [c367]Michael Lo, Zhenman Fang, Jie Wang, Peipei Zhou, Mau-Chung Frank Chang, Jason Cong:
Algorithm-Hardware Co-design for BQSR Acceleration in Genome Analysis ToolKit. FCCM 2020: 157-166 - [c366]Jiajie Li, Yuze Chi, Jason Cong:
HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration. FPGA 2020: 51-57 - [c365]Atefeh Sohrabizadeh, Jie Wang, Jason Cong:
End-to-End Optimization of Deep Learning Applications. FPGA 2020: 133-139 - [c364]Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong:
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. FPGA 2020: 311 - [c363]Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong:
CANSEE: Customized Accelerator for Neural Signal Enhancement and Extraction from the Calcium Image in Real Time. FPGA 2020: 318 - [c362]Yi-Hsiang Lai, Hongbo Rong, Size Zheng, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang, Brendan Sullivan, Zhiru Zhang, Yun Liang, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey:
SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAs. ICCAD 2020: 73:1-73:9 - [c361]Bochen Tan, Jason Cong:
Optimal Layout Synthesis for Quantum Computing. ICCAD 2020: 137:1-137:9 - [c360]Jason Lau, Aishwarya Sivaraman, Qian Zhang, Muhammad Ali Gulzar, Jason Cong, Miryung Kim:
HeteroRefactor: refactoring for heterogeneous computing with FPGA. ICSE 2020: 493-505 - [c359]Nikola Samardzic, Weikang Qiao, Vaibhav Aggarwal, Mau-Chung Frank Chang, Jason Cong:
Bonsai: High-Performance Adaptive Merge Tree Sorting. ISCA 2020: 282-294 - [c358]Zhe Chen, Garrett J. Blair, Hugh T. Blair, Jason Cong:
BLINK: bit-sparse LSTM inference kernel enabling efficient calcium trace extraction for neurofeedback devices. ISLPED 2020: 217-222 - [i11]Bochen Tan, Jason Cong:
Optimality Study of Existing Quantum Computing Layout Synthesis Tools. CoRR abs/2002.09783 (2020) - [i10]Bochen Tan, Jason Cong:
Optimal Layout Synthesis for Quantum Computing. CoRR abs/2007.15671 (2020) - [i9]Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong:
Extending High-Level Synthesis for Task-Parallel Programs. CoRR abs/2009.11389 (2020) - [i8]Atefeh Sohrabizadeh, Cody Hao Yu, Min Gao, Jason Cong:
AutoDSE: Enabling Software Programmers Design Efficient FPGA Accelerators. CoRR abs/2009.14381 (2020) - [i7]Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong:
When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization. CoRR abs/2010.06075 (2020)
2010 – 2019
- 2019
- [j114]Yanghyo Kim, Boyu Hu, Yuan Du, Wei-Han Cho, Rulin Huang, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang:
A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. IEEE J. Solid State Circuits 54(6): 1600-1612 (2019) - [j113]Jason Cong, Zhenman Fang, Muhuan Huang, Peng Wei, Di Wu, Cody Hao Yu:
Customizable Computing - From Single Chip to Datacenters. Proc. IEEE 107(1): 185-203 (2019) - [j112]Shuo Li, Nong Xiao, Peng Wang, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Helen Li, Jason Cong, Tao Zhang:
RC-NVM: Dual-Addressing Non-Volatile Memory Architecture Supporting Both Row and Column Memory Accesses. IEEE Trans. Computers 68(2): 239-254 (2019) - [j111]Chen Zhang, Guangyu Sun, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong:
Caffeine: Toward Uniformed Representation and Acceleration for Deep Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(11): 2072-2085 (2019) - [j110]Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei:
In-Depth Analysis on Microarchitectures of Modern Heterogeneous CPU-FPGA Platforms. ACM Trans. Reconfigurable Technol. Syst. 12(1): 4:1-4:20 (2019) - [c357]Zhenman Fang, Farnoosh Javadi, Jason Cong, Glenn Reinman:
Understanding Performance Gains of Accelerator-Rich Architectures. ASAP 2019: 239-246 - [c356]Xuechao Wei, Yun Liang, Jason Cong:
Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory Management. DAC 2019: 125 - [c355]Weikang Qiao, Zhenman Fang, Mau-Chung Frank Chang, Jason Cong:
An FPGA-Based BWT Accelerator for Bzip2 Data Compression. FCCM 2019: 96-99 - [c354]Licheng Guo, Jason Lau, Zhenyuan Ruan, Peng Wei, Jason Cong:
Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU. FCCM 2019: 127-135 - [c353]Zhe Chen, Hugh T. Blair, Jason Cong:
LANMC: LSTM-Assisted Non-Rigid Motion Correction on FPGA for Calcium Image Stabilization. FPGA 2019: 104-109 - [c352]Xuechao Wei, Yun Liang, Peng Zhang, Cody Hao Yu, Jason Cong:
Overcoming Data Transfer Bottlenecks in DNN Accelerators via Layer-Conscious Memory Managment. FPGA 2019: 120 - [c351]Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang:
Rapid Cycle-Accurate Simulator for High-Level Synthesis. FPGA 2019: 178-183 - [c350]Jie Liu, Jason Cong:
Dataflow Systolic Array Implementations of Matrix Decomposition Using High Level Synthesis. FPGA 2019: 187 - [c349]Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang:
HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing. FPGA 2019: 242-251 - [c348]Zhenyuan Ruan, Tong He, Jason Cong:
Analyzing and Modeling In-Storage Computing Workloads On EISC - An FPGA-Based System-Level Emulation Platform. ICCAD 2019: 1-8 - [c347]Jiaxi Zhang, Wentai Zhang, Guojie Luo, Xuechao Wei, Yun Liang, Jason Cong:
Frequency Improvement of Systolic Array-Based CNNs on FPGAs. ISCAS 2019: 1-4 - [c346]Zhenyuan Ruan, Tong He, Jason Cong:
INSIDER: Designing In-Storage Computing System for Emerging High-Performance Drive. USENIX ATC 2019: 379-394 - 2018
- [b2]Ruipeng Gao, Fan Ye, Guojie Luo, Jason Cong:
Smartphone-Based Indoor Map Construction - Principles and Applications. Springer Briefs in Computer Science, Springer 2018, ISBN 978-981-10-8377-8, pp. 1-109 - [j109]Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu:
CPU-FPGA Coscheduling for Big Data Applications. IEEE Des. Test 35(1): 16-22 (2018) - [c345]Cody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarkar, Jason Cong:
S2FA: an accelerator automation framework for heterogeneous computing in datacenters. DAC 2018: 153:1-153:6 - [c344]Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang:
Automated accelerator generation and optimization with composable, parallel and pipeline architecture. DAC 2018: 154:1-154:6 - [c343]Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou, Jason Cong:
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA. FCCM 2018: 9-16 - [c342]Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong:
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. FCCM 2018: 37-44 - [c341]Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang:
Understanding Performance Differences of FPGAs and GPUs. FCCM 2018: 93-96 - [c340]Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou:
Latte: Locality Aware Transformation for High-Level Synthesis. FCCM 2018: 125-128 - [c339]Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu:
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. FCCM 2018: 206 - [c338]Jason Cong, Jie Wang:
Automatic Interior I/O Elimination in Systolic Array Architecture. FCCM 2018: 228 - [c337]Yuze Chi, Peipei Zhou, Jason Cong:
An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only). FPGA 2018: 286 - [c336]Jason Cong, Zhenman Fang, Yao Hu, Di Wu:
K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only). FPGA 2018: 287 - [c335]Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong:
FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only). FPGA 2018: 288 - [c334]Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang:
Understanding Performance Differences of FPGAs and GPUs: (Abtract Only). FPGA 2018: 288 - [c333]Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong:
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only). FPGA 2018: 291 - [c332]Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu:
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for Genome Sequencing. FPL 2018: 210-214 - [c331]Jason Cong, Peng Wei, Cody Hao Yu:
From JVM to FPGA: Bridging Abstraction Hierarchy via Optimized Deep Pipelining. HotCloud 2018 - [c330]Peng Wang, Shuo Li, Guangyu Sun, Xiaoyang Wang, Yiran Chen, Hai Li, Jason Cong, Nong Xiao, Tao Zhang:
RC-NVM: Enabling Symmetric Row and Column Memory Accesses for In-memory Databases. HPCA 2018: 518-530 - [c329]Xuechao Wei, Yun Liang, Xiuhong Li, Cody Hao Yu, Peng Zhang, Jason Cong:
TGPA: tile-grained pipeline architecture for low latency CNN inference. ICCAD 2018: 58 - [c328]Young-kyu Choi, Jason Cong:
HLS-based optimization and design space exploration for applications with variable loop bounds. ICCAD 2018: 103 - [c327]Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou:
SODA: stencil with optimized dataflow architecture. ICCAD 2018: 116 - [c326]Jason Cong, Jie Wang:
PolySA: polyhedral-based systolic array auto-compilation. ICCAD 2018: 117 - [c325]Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong:
CLINK: Compact LSTM Inference Kernel for Energy Efficient Neurofeedback Devices. ISLPED 2018: 2:1-2:6 - [c324]Peipei Zhou, Zhenyuan Ruan, Zhenman Fang, Megan Shand, David Roazen, Jason Cong:
Doppio: I/O-Aware Performance Analysis, Modeling and Optimization for In-memory Computing Framework. ISPASS 2018: 22-32 - [c323]Yanghyo Kim, Boyu Hu, Yuan Du, Adrian Tang, Huan-Neng Ron Chen, Chewnpu Jou, Jason Cong, Tatsuo Itoh, Mau-Chung Frank Chang:
A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. ISSCC 2018: 278-280 - [c322]Meng Li, Shiwen Shen, Wen Gao, William Hsu, Jason Cong:
Computed Tomography Image Enhancement Using 3D Convolutional Neural Network. DLMIA/ML-CDS@MICCAI 2018: 291-299 - [p4]Jason Cong, Joseph R. Shinnerl:
Large-Scale Global Placement. Handbook of Approximation Algorithms and Metaheuristics (2) 2018 - [i6]Jason Cong, Zhenman Fang, Yuchen Hao, Peng Wei, Cody Hao Yu, Chen Zhang, Peipei Zhou:
Best-Effort FPGA Programming: A Few Steps Can Go a Long Way. CoRR abs/1807.01340 (2018) - [i5]Meng Li, Shiwen Shen, Wen Gao, William Hsu, Jason Cong:
Computed Tomography Image Enhancement using 3D Convolutional Neural Network. CoRR abs/1807.06821 (2018) - [i4]Jason Cong, Peng Wei, Cody Hao Yu, Peng Zhang:
AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture. CoRR abs/1809.07683 (2018) - [i3]Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang:
Rapid Cycle-Accurate Simulator for High-Level Synthesis. CoRR abs/1812.07012 (2018) - 2017
- [c321]Yijin Guan, Ningyi Xu, Chen Zhang, Zhihang Yuan, Jason Cong:
Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators. APPT 2017: 14-26 - [c320]Xuechao Wei, Yun Liang, Tao Wang, Songwu Lu, Jason Cong:
Throughput optimization for streaming applications on CPU-FPGA heterogeneous systems. ASP-DAC 2017: 488-493 - [c319]Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong:
FPGA-based accelerator for long short-term memory recurrent neural networks. ASP-DAC 2017: 629-634 - [c318]Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong:
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. DAC 2017: 29:1-29:6 - [c317]Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou:
Bandwidth Optimization Through On-Chip Memory Restructuring for HLS. DAC 2017: 43:1-43:6 - [c316]Young Kyu Choi, Jason Cong:
HLScope: High-Level Performance Debugging for FPGA Designs. FCCM 2017: 125-128 - [c315]Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong:
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. FCCM 2017: 152-159 - [c314]Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu:
CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only). FPGA 2017: 291 - [c313]Yuchen Hao, Zhenman Fang, Glenn Reinman, Jason Cong:
Supporting Address Translation for Accelerator-Centric Architectures. HPCA 2017: 37-48 - [c312]Meng Li, Huizhu Jia, Xiaodong Xie, Jason Cong, Wen Gao:
A cache-based bandwidth optimized motion compensation architecture for video decoder. ICASSP 2017: 1303-1307 - [c311]Young-kyu Choi, Peng Zhang, Peng Li, Jason Cong:
HLScope+, : Fast and accurate performance estimation for FPGA HLS. ICCAD 2017: 691-698 - [c310]Jason Cong:
Characterization and acceleration for genomic sequencing and analysis. IISWC 2017: 1 - [c309]Jie Wang, Xinfeng Xie, Jason Cong:
Communication Optimization on GPU: A Case Study of Sequence Alignment Algorithms. IPDPS 2017: 72-81 - [c308]Jason Cong, Zhenman Fang, Michael Gill, Farnoosh Javadi, Glenn Reinman:
AIM: accelerating computational genomics through scalable and noninvasive accelerator-interposed memory. MEMSYS 2017: 3-14 - 2016
- [j108]Deming Chen, Jason Cong, Swathi T. Gurumani, Wen-mei W. Hwu, Kyle Rupnow, Zhiru Zhang:
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 70-77 (2016) - [j107]Young Kyu Choi, Jason Cong:
Acceleration of EM-Based 3D CT Reconstruction Using FPGA. IEEE Trans. Biomed. Circuits Syst. 10(3): 754-767 (2016) - [j106]Paolo Montuschi, Edward J. McCluskey, Samarjit Chakraborty, Jason Cong, Ramón M. Rodríguez-Dagnino, Fred Douglis, Lieven Eeckhout, Gernot Heiser, Sushil Jajodia, Ruby B. Lee, Dinesh Manocha, Tomás F. Pena, Isabelle Puaut, Hanan Samet, Donatella Sciuto:
State of the Journal. IEEE Trans. Computers 65(7): 2014-2018 (2016) - [j105]Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang:
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 407-418 (2016) - [j104]Alberto A. Del Barrio, Jason Cong, Román Hermida:
A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(3): 419-432 (2016) - [j103]Ying Chen, Tan Nguyen, Yao Chen, Swathi T. Gurumani, Yun Liang, Kyle Rupnow, Jason Cong, Wen-mei W. Hwu, Deming Chen:
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2032-2045 (2016) - [c307]Jason Cong, Hui Huang, Mohammad Ali Ghodrat:
A scalable communication-aware compilation flow for programmable accelerators. ASP-DAC 2016: 503-510 - [c306]Muhuan Huang, Di Wu, Cody Hao Yu, Zhenman Fang, Matteo Interlandi, Tyson Condie, Jason Cong:
Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale. SoCC 2016: 456-469 - [c305]Jason Cong, Muhuan Huang, Di Wu, Cody Hao Yu:
Invited - Heterogeneous datacenters: options and opportunities. DAC 2016: 16:1-16:6 - [c304]Young-kyu Choi, Jason Cong, Zhenman Fang, Yuchen Hao, Glenn Reinman, Peng Wei:
A quantitative analysis on microarchitectures of modern CPU-FPGA platforms. DAC 2016: 109:1-109:6 - [c303]Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei:
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. FCCM 2016: 29 - [c302]Mau-Chung Frank Chang, Yu-Ting Chen, Jason Cong, Po-Tsang Huang, Chun-Liang Kuo, Cody Hao Yu:
The SMEM Seeding Acceleration for DNA Sequence Alignment. FCCM 2016: 32-39 - [c301]Peipei Zhou, Hyunseok Park, Zhenman Fang, Jason Cong, André DeHon:
Energy Efficiency of Full Pipelining: A Case Study for Matrix Multiplication. FCCM 2016: 172-175 - [c300]Jie Lei, Yu-Ting Chen, Yunsong Li, Jason Cong:
A High-throughput Architecture for Lossless Decompression on FPGA Designed Using HLS (Abstract Only). FPGA 2016: 277 - [c299]Yu-Ting Chen, Jason Cong, Zhenman Fang, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architecture (Abstact Only). FPGA 2016: 281 - [c298]Yu-Ting Chen, Jason Cong, Zhenman Fang, Jie Lei, Peng Wei:
When Spark Meets FPGAs: A Case Study for Next-Generation DNA Sequencing Acceleration. HotCloud 2016 - [c297]Chen Zhang, Zhenman Fang, Peipei Zhou, Peichen Pan, Jason Cong:
Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. ICCAD 2016: 12:1-12:8 - [c296]Jason Cong, Muhuan Huang, Peichen Pan, Di Wu, Peng Zhang:
Software Infrastructure for Enabling FPGA-Based Accelerations in Data Centers: Invited Paper. ISLPED 2016: 154-155 - [c295]Chen Zhang, Di Wu, Jiayu Sun, Guangyu Sun, Guojie Luo, Jason Cong:
Energy-Efficient CNN Implementation on a Deeply Pipelined FPGA Cluster. ISLPED 2016: 326-331 - [c294]Guojie Luo, Wentai Zhang, Jiaxi Zhang, Jason Cong:
Scaling Up Physical Design: Challenges and Opportunities. ISPD 2016: 131-137 - [p3]Jason Cong, Muhuan Huang, Peichen Pan, Yuxin Wang, Peng Zhang:
Source-to-Source Optimization for HLS. FPGAs for Software Programmers 2016: 137-163 - [r4]Jason Cong, Yuzheng Ding:
FPGA Technology Mapping. Encyclopedia of Algorithms 2016: 773-777 - [i2]Yu-Ting Chen, Jason Cong, Zhenman Fang, Bingjun Xiao, Peipei Zhou:
ARAPrototyper: Enabling Rapid Prototyping and Evaluation for Accelerator-Rich Architectures. CoRR abs/1610.09761 (2016) - [i1]Jason Cong, Zhenman Fang, Hassan Kianinejad, Peng Wei:
Revisiting FPGA Acceleration of Molecular Dynamics Simulation with Dynamic Data Flow Behavior in High-Level Synthesis. CoRR abs/1611.04474 (2016) - 2015
- [b1]Yu-Ting Chen, Jason Cong, Michael Gill, Glenn Reinman, Bingjun Xiao:
Customizable Computing. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2015, ISBN 978-3-031-00620-3 - [j102]Shiwen Shen, Alex A. T. Bui, Jason Cong, William Hsu:
An automated lung segmentation approach using bidirectional chain codes to improve nodule detection accuracy. Comput. Biol. Medicine 57: 139-149 (2015) - [c293]Peng Wang, Le Cao, Chunbo Lai, Leqi Zou, Guangyu Sun, Jason Cong:
InterFS: An Interplanted Distributed File System to Improve Storage Utilization. APSys 2015: 14:1-14:8 - [c292]Jason Cong, Michael Gill, Yuchen Hao, Glenn Reinman, Bo Yuan:
On-chip interconnection network for accelerator-rich architectures. DAC 2015: 8:1-8:6 - [c291]Peng Zhang, Muhuan Huang, Bingjun Xiao, Hui Huang, Jason Cong:
CMOST: a system-level FPGA compilation framework. DAC 2015: 158:1-158:6 - [c290]Yu-Ting Chen, Jason Cong, Jie Lei, Peng Wei:
A Novel High-Throughput Acceleration Engine for Read Alignment. FCCM 2015: 199-202 - [c289]John Lockwood, Michael Adler, Dan Mansur, Derek Chiou, Mike Strickland, Jason Cong, Steve Teig:
Growing a Healthy FPGA Ecosystem. FPGA 2015: 160 - [c288]Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong:
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks. FPGA 2015: 161-170 - [c287]Peng Li, Peng Zhang, Louis-Noël Pouchet, Jason Cong:
Resource-Aware Throughput Optimization for High-Level Synthesis. FPGA 2015: 200-209 - [c286]Wentai Zhang, Li Shen, Thomas Page, Guojie Luo, Peng Li, Peter Maaß, Ming Jiang, Jason Cong:
FPGA Acceleration for Simultaneous Image Reconstruction and Segmentation based on the Mumford-Shah Regularization (Abstract Only). FPGA 2015: 261 - [c285]Jie Wang, Jason Cong:
Customizable and High Performance Matrix Multiplication Kernel on FPGA (Abstract Only). FPGA 2015: 276 - [c284]Jason Cong, Cody Hao Yu:
Impact of Loop Transformations on Software Reliability. ICCAD 2015: 278-285 - [c283]Jason Cong, Zhenman Fang, Michael Gill, Glenn Reinman:
PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and Exploration. ICCAD 2015: 380-387 - [c282]Meng Li, Peng Zhang, Chuang Zhu, Huizhu Jia, Xiaodong Xie, Jason Cong, Wen Gao:
High efficiency VLSI implementation of an edge-directed video up-scaler using high level synthesis. ICCE 2015: 92-95 - [c281]Yu-Ting Chen, Jason Cong:
Interconnect synthesis of heterogeneous accelerators in a shared memory architecture. ISLPED 2015: 359-364 - [c280]Yu-Ting Chen, Jason Cong, Bingjun Xiao:
ARACompiler: a prototyping flow and evaluation framework for accelerator-rich architectures. ISPASS 2015: 157-158 - [c279]Chunbo Lai, Song Jiang, Liqiong Yang, Shiding Lin, Guangyu Sun, Zhenyu Hou, Can Cui, Jason Cong:
Atlas: Baidu's key-value storage system for cloud data. MSST 2015: 1-14 - [c278]Jason Cong:
"High-level synthesis and beyond - From datacenters to IoTs". SoCC 2015 - 2014
- [j101]Jason Cong, Henry Duwe, Rakesh Kumar, Sen Li:
Better-Than-Worst-Case Design: Progress and Opportunities. J. Comput. Sci. Technol. 29(4): 656-663 (2014) - [j100]Tao Wang, Guangyu Sun, Jiahua Chen, Jian Gong, Haoyang Wu, Xiaoguang Li, Songwu Lu, Jason Cong:
GRT: A Reconfigurable SDR Platform with High Performance and Usability. SIGARCH Comput. Archit. News 42(4): 51-56 (2014) - [j99]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman:
Architecture Support for Domain-Specific Accelerator-Rich CMPs. ACM Trans. Embed. Comput. Syst. 13(4s): 131:1-131:26 (2014) - [j98]Anpeng Huang, Wenyao Xu, Zhinan Li, Linzhen Xie, Majid Sarrafzadeh, Xiaoming Li, Jason Cong:
System Light-Loading Technology for mHealth: Manifold-Learning-Based Medical Data Cleansing and Clinical Trials in WE-CARE Project. IEEE J. Biomed. Health Informatics 18(5): 1581-1589 (2014) - [j97]Jason Cong, Bingjun Xiao:
FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 22(4): 864-877 (2014) - [c277]Jason Cong, Peng Li, Bingjun Xiao, Peng Zhang:
An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers. DAC 2014: 77:1-77:6 - [c276]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Karthik Gururaj, Glenn Reinman:
Accelerator-Rich Architectures: Opportunities and Progresses. DAC 2014: 180:1-180:6 - [c275]Peng Wang, Guangyu Sun, Song Jiang, Jian Ouyang, Shiding Lin, Chen Zhang, Jason Cong:
An efficient design and implementation of LSM-tree based key-value store on open-channel SSD. EuroSys 2014: 16:1-16:14 - [c274]Jason Cong, Hui Huang, Chiyuan Ma, Bingjun Xiao, Peipei Zhou:
A Fully Pipelined and Dynamically Composable Architecture of CGRA. FCCM 2014: 9-16 - [c273]Young Kyu Choi, Jason Cong, Di Wu:
FPGA Implementation of EM Algorithm for 3D CT Reconstruction. FCCM 2014: 157-160 - [c272]Peng Li, Thomas Page, Guojie Luo, Wentai Zhang, Pei Wang, Peng Zhang, Peter Maass, Ming Jiang, Jason Cong:
FPGA Acceleration for Simultaneous Medical Image Reconstruction and Segmentation. FCCM 2014: 172 - [c271]Yuxin Wang, Peng Li, Jason Cong:
Theory and algorithm for generalized memory partitioning in high-level synthesis. FPGA 2014: 199-208 - [c270]Jason Cong, Muhuan Huang, Peng Zhang:
Combining computation and communication optimizations in system synthesis for streaming applications. FPGA 2014: 213-222 - [c269]Peng Li, Louis-Noël Pouchet, Deming Chen, Jason Cong:
Transformations for throughput optimization in high-level synthesis (abstract only). FPGA 2014: 245 - [c268]Jian Gong, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong, Tao Wang:
EPEE: an efficient PCIe communication library with easy-host-integration property for FPGA accelerators (abstract only). FPGA 2014: 255 - [c267]Jian Gong, Tao Wang, Jiahua Chen, Haoyang Wu, Fan Ye, Songwu Lu, Jason Cong:
An efficient and flexible host-FPGA PCIe communication library. FPL 2014: 1-6 - [c266]Muhuan Huang, Kevin Lim, Jason Cong:
A scalable, high-performance customized priority queue. FPL 2014: 1-4 - [c265]Jason Cong:
Automating customized computing. FPT 2014: 2 - [c264]Jason Cong, Bingjun Xiao:
Minimizing Computation in Convolutional Neural Networks. ICANN 2014: 281-290 - [c263]Jason Cong:
Accelerator-rich architectures: from single-chip to datacenters. ISLPED 2014: 139-140 - [c262]Jason Cong:
From design to design automation. ISPD 2014: 121-126 - 2013
- [j96]Chunhua Xiao, M.-C. Frank Chang, Jason Cong, Michael Gill, Zhangqin Huang, Chunyue Liu, Glenn Reinman, Hao Wu:
Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects. ACM Trans. Archit. Code Optim. 9(4): 60:1-60:27 (2013) - [j95]Guojie Luo, Yiyu Shi, Jason Cong:
An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(4): 510-523 (2013) - [j94]Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
Efficient compilation of CUDA kernels for high-performance computing on FPGAs. ACM Trans. Embed. Comput. Syst. 13(2): 25:1-25:26 (2013) - [j93]Amit Agarwal, Jason Cong, Brian Tagiku:
The survivability of design-specific spare placement in FPGA architectures with high defect rates. ACM Trans. Design Autom. Electr. Syst. 18(2): 33:1-33:22 (2013) - [c261]Jason Cong, Guojie Luo, Kalliopi Tsota, Bingjun Xiao:
Optimizing routability in large-scale mixed-size placement. ASP-DAC 2013: 441-446 - [c260]Wei Zuo, Peng Li, Deming Chen, Louis-Noël Pouchet, Shunan Zhong, Jason Cong:
Improving polyhedral code generation for high-level synthesis. CODES+ISSS 2013: 15:1-15:10 - [c259]Jason Cong, Bingjun Xiao:
Defect tolerance in nanodevice-based programmable interconnects: utilization beyond avoidance. DAC 2013: 9:1-9:8 - [c258]Alexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu, Jason Cong, Yun Liang:
Throughput-oriented kernel porting onto FPGAs. DAC 2013: 11:1-11:10 - [c257]Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong:
Memory partitioning for multidimensional arrays in high-level synthesis. DAC 2013: 12:1-12:8 - [c256]Jason Cong, Hugh T. Blair, Di Wu:
FPGA Simulation Engine for Customized Construction of Neural Microcircuit. FCCM 2013: 229 - [c255]Wei Zuo, Yun Liang, Peng Li, Kyle Rupnow, Deming Chen, Jason Cong:
Improving high level synthesis optimization opportunity through polyhedral transformations. FPGA 2013: 9-18 - [c254]Louis-Noël Pouchet, Peng Zhang, P. Sadayappan, Jason Cong:
Polyhedral-based data reuse optimization for configurable computing. FPGA 2013: 29-38 - [c253]Vaughn Betz, Jason Cong:
Are FPGAs suffering from the innovator's dilemna? FPGA 2013: 135-136 - [c252]Jason Cong, Karthik Gururaj:
Architecture support for custom instructions with memory operations. FPGA 2013: 231-234 - [c251]Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, Jason Cong:
Automatic multidimensional memory partitioning for FPGA-based accelerators (abstract only). FPGA 2013: 269 - [c250]Jason Cong, Muhuan Huang, Peng Zhang:
Efficient system-level mapping from streaming applications to FPGAs (abstract only). FPGA 2013: 277 - [c249]Jason Cong, Bingjun Xiao:
Defect recovery in nanodevice-based programmable interconnects (abstract only). FPGA 2013: 277-278 - [c248]Hugh T. Blair, Jason Cong, Di Wu:
FPGA simulation engine for customized construction of neural microcircuits. ICCAD 2013: 607-614 - [c247]Jason Cong, Bingjun Xiao:
Optimization of interconnects between accelerators and shared memories in dark silicon. ICCAD 2013: 630-637 - [c246]Yu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou:
Accelerator-rich CMPs: From concept to real hardware. ICCD 2013: 169-176 - [c245]Peng Wang, Guangyu Sun, Tao Wang, Yuan Xie, Jason Cong:
Designing scratchpad memory architecture with emerging STT-RAM memory technologies. ISCAS 2013: 1244-1247 - [c244]Jason Cong, Milos D. Ercegovac, Muhuan Huang, Sen Li, Bingjun Xiao:
Energy-efficient computing using adaptive table lookup based on nonvolatile memories. ISLPED 2013: 280-285 - [c243]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Hui Huang, Glenn Reinman:
Composable accelerator-rich microprocessor enhanced for adaptivity and longevity. ISLPED 2013: 305-310 - 2012
- [j92]Yanghyo Kim, Sai-Wang Tam, Gyungsu Byun, Hao Wu, Lan Nan, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang:
Analysis of Noncoherent ASK Modulation-Based RF-Interconnect for Memory Interface. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 200-209 (2012) - [j91]Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang:
Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 210-227 (2012) - [j90]Jianwen Chen, Jason Cong, Luminita A. Vese, John D. Villasenor, Ming Yan, Yi Zou:
A Hybrid Architecture for Compressive Sensing 3-D CT Reconstruction. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 616-625 (2012) - [j89]Jason Cong, Karthik Gururaj, Peng Zhang, Yi Zou:
Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections. J. Electr. Comput. Eng. 2012: 691864:1-691864:24 (2012) - [j88]Kanit Therdsteerasukdi, Gyungsu Byun, Jason Cong, M. Frank Chang, Glenn Reinman:
Utilizing RF-I and intelligent scheduling for better throughput/watt in a mobile GPU memory system. ACM Trans. Archit. Code Optim. 8(4): 51:1-51:19 (2012) - [c242]Alex A. T. Bui, Kwang-Ting Cheng, Jason Cong, Luminita A. Vese, Yi-Chu Wang, Bo Yuan, Yi Zou:
Platform characterization for Domain-Specific Computing. ASP-DAC 2012: 94-99 - [c241]Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong:
An integrated and automated memory optimization flow for FPGA behavioral synthesis. ASP-DAC 2012: 257-262 - [c240]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Hui Huang, Bin Liu, Raghu Prabhakar, Glenn Reinman, Marco Vitanza:
Compilation and architecture support for customized vector instruction extension. ASP-DAC 2012: 652-657 - [c239]Hao Wu, Lan Nan, Sai-Wang Tam, Hsieh-Hung Hsieh, Chewnpu Jou, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang:
A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration. CICC 2012: 1-4 - [c238]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman:
Architecture support for accelerator-rich CMPs. DAC 2012: 843-849 - [c237]Jason Cong, Peng Zhang, Yi Zou:
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis. DAC 2012: 1233-1238 - [c236]Jason Cong, Bin Liu:
A metric for layout-friendly microarchitecture optimization in high-level synthesis. DAC 2012: 1239-1244 - [c235]Yu-Ting Chen, Jason Cong, Hui Huang, Bin Liu, Chunyue Liu, Miodrag Potkonjak, Glenn Reinman:
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design. DATE 2012: 45-50 - [c234]Jason Cong, Muhuan Huang, Bin Liu, Peng Zhang, Yi Zou:
Combining module selection and replication for throughput-driven streaming programs. DATE 2012: 1018-1023 - [c233]Jianwen Chen, Jason Cong, Ming Yan, Yi Zou:
FPGA-accelerated 3D reconstruction using compressive sensing. FPGA 2012: 163-166 - [c232]Jason Cong, Bingjun Xiao:
FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only). FPGA 2012: 268 - [c231]Peng Li, Yuxin Wang, Peng Zhang, Guojie Luo, Tao Wang, Jason Cong:
Memory partitioning and scheduling co-optimization in behavioral synthesis. ICCAD 2012: 488-495 - [c230]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Chunyue Liu, Glenn Reinman:
BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs. ISLPED 2012: 225-230 - [c229]Yu-Ting Chen, Jason Cong, Hui Huang, Chunyue Liu, Raghu Prabhakar, Glenn Reinman:
Static and dynamic co-optimizations for blocks mapping in hybrid caches. ISLPED 2012: 237-242 - [c228]Jason Cong, Bo Yuan:
Energy-efficient scheduling on heterogeneous multi-core architectures. ISLPED 2012: 345-350 - [c227]Jason Cong, Mohammad Ali Ghodrat, Michael Gill, Beayna Grigorian, Glenn Reinman:
CHARM: a composable heterogeneous accelerator-rich microprocessor. ISLPED 2012: 379-384 - [c226]Jason Cong:
Transformation from ad hoc EDA to algorithmic EDA. ISPD 2012: 57-62 - [c225]Jason Cong, Bin Liu, Guojie Luo, Raghu Prabhakar:
Towards layout-friendly high-level synthesis. ISPD 2012: 165-172 - [c224]Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong:
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. ISQED 2012: 129-136 - [c223]Yanghyo Kim, Gyungsu Byun, Adrian Tang, Chewnpu Jou, Hsieh-Hung Hsieh, Glenn Reinman, Jason Cong, Mau-Chung Frank Chang:
An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression. ISSCC 2012: 50-52 - [c222]Jason Cong, Bin Liu, Raghu Prabhakar, Peng Zhang:
A Study on the Impact of Compiler Optimizations on High-Level Synthesis. LCPC 2012: 143-157 - [c221]Alina Simion Sbîrlea, Yi Zou, Zoran Budimlic, Jason Cong, Vivek Sarkar:
Mapping a data-flow programming model onto heterogeneous platforms. LCTES 2012: 61-70 - 2011
- [j87]Jason Cong, Glenn Reinman, Alex A. T. Bui, Vivek Sarkar:
Customizable Domain-Specific Computing. IEEE Des. Test Comput. 28(2): 6-15 (2011) - [j86]Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong:
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2490-2498 (2011) - [j85]Jason Cong:
Overview of Center for Domain-Specific Computing. J. Comput. Sci. Technol. 26(4): 632-635 (2011) - [j84]Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang:
High-Level Synthesis for FPGAs: From Prototyping to Deployment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 473-491 (2011) - [j83]Jason Cong, Hui Huang, Wei Jiang:
Pattern-Mining for Behavioral Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 939-944 (2011) - [j82]Jason Cong, Wei Jiang, Bin Liu, Yi Zou:
Automatic memory partitioning and scheduling for throughput and power optimization. ACM Trans. Design Autom. Electr. Syst. 16(2): 15:1-15:25 (2011) - [j81]Jeonghun Kim, Hanjun Choi, Sungyeal Yoon, Taesik Bang, Jongchan Park, Chaehyun Jung, Jason Cong:
An 8M Polygons/s 3-D Graphics SoC With Full Hardware Geometric and Rendering Engine for Mobile Applications. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1490-1495 (2011) - [c220]Jason Cong:
Era of customization and specialization. ASAP 2011: 3 - [c219]Jason Cong, Beayna Grigorian, Glenn Reinman, Marco Vitanza:
Accelerating vision and navigation applications on a customizable platform. ASAP 2011: 25-32 - [c218]Jason Cong, Karthik Gururaj, Muhuan Huang, Sen Li, Bingjun Xiao, Yi Zou:
Domain-specific processor with 3D integration for medical image processing. ASAP 2011: 247-250 - [c217]Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong:
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. ASP-DAC 2011: 261-266 - [c216]Yu-Ting Chen, Jason Cong, Glenn Reinman:
HC-Sim: a fast and exact l1 cache simulator with scratchpad memory co-simulation support. CODES+ISSS 2011: 295-304 - [c215]Jason Cong, Guojie Luo, Yiyu Shi:
Thermal-aware cell and through-silicon-via co-placement for 3D ICs. DAC 2011: 670-675 - [c214]Jason Cong, Hui Huang, Chunyue Liu, Yi Zou:
A reuse-aware prefetching scheme for scratchpad memory. DAC 2011: 960-965 - [c213]Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-mei W. Hwu, Jason Cong:
Multilevel Granularity Parallelism Synthesis on FPGAs. FCCM 2011: 178-185 - [c212]Jason Cong, Yi Zou:
Resolving implicit barrier synchronizations in FPGA HLS (abstract only). FPGA 2011: 278 - [c211]Jason Cong, Muhuan Huang, Yi Zou:
Accelerating Fluid Registration Algorithm on Multi-FPGA Platforms. FPL 2011: 50-57 - [c210]Jason Cong, Karthik Gururaj:
Assuring application-level correctness against soft errors. ICCAD 2011: 150-157 - [c209]Jason Cong, Peng Zhang, Yi Zou:
Combined loop transformation and hierarchy allocation for data reuse optimization. ICCAD 2011: 185-192 - [c208]Jason Cong, Yuhui Huang, Bo Yuan:
ATree-based topology synthesis for on-chip network. ICCAD 2011: 651-658 - [c207]Kanit Therdsteerasukdi, Gyungsu Byun, Jeremy Ir, Glenn Reinman, Jason Cong, M. Frank Chang:
The DIMM tree architecture: A high bandwidth and scalable memory system. ICCD 2011: 388-395 - [c206]Jason Cong, John Lee, Guojie Luo:
A unified optimization framework for simultaneous gate sizing and placement under density constraints. ISCAS 2011: 1207-1210 - [c205]Jason Cong, Karthik Gururaj, Hui Huang, Chunyue Liu, Glenn Reinman, Yi Zou:
An energy-efficient adaptive hybrid cache. ISLPED 2011: 67-72 - [c204]Gyungsu Byun, Yanghyo Kim, Jongsun Kim, Sai-Wang Tam, Hsieh-Hung Hsieh, P.-Y. Wu, Chewnpu Jou, Jason Cong, Glenn Reinman, Mau-Chung Frank Chang:
An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling. ISSCC 2011: 488-490 - [c203]Ming Yan, Jianwen Chen, Luminita A. Vese, John D. Villasenor, Alex A. T. Bui, Jason Cong:
EM+TV Based Reconstruction for Cone-Beam CT with Reduced Radiation. ISVC (1) 2011: 1-10 - [c202]Jason Cong, Bingjun Xiao:
mrFPGA: A novel FPGA architecture with memristor-based reconfiguration. NANOARCH 2011: 1-8 - [c201]Jason Cong, Muhuan Huang, Yi Zou:
3D recursive Gaussian IIR on GPU and FPGAs - A case for accelerating bandwidth-bounded applications. SASP 2011: 70-73 - [p2]Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman:
RF-Interconnect for Future Network-On-Chip. Low Power Networks-on-Chip 2011: 255-280 - 2010
- [j80]Robert K. Brayton, Jason Cong:
NSF Workshop on EDA: Past, Present, and Future (Part 1). IEEE Des. Test Comput. 27(2): 68-74 (2010) - [j79]Robert K. Brayton, Jason Cong:
NSF Workshop on EDA: Past, Present, and Future (Part 2). IEEE Des. Test Comput. 27(3): 62-74 (2010) - [j78]Jason Cong, Guojie Luo:
Advances and Challenges in 3D Physical Design. Inf. Media Technol. 5(2): 321-337 (2010) - [j77]Jason Cong, Guojie Luo:
Advances and Challenges in 3D Physical Design. IPSJ Trans. Syst. LSI Des. Methodol. 3: 2-18 (2010) - [j76]Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li, Chi-Chen Peng:
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1709-1722 (2010) - [j75]Jason Cong, Puneet Gupta, John Lee:
Evaluating Statistical Power Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1750-1762 (2010) - [j74]Jason Cong, Bin Liu, Rupak Majumdar, Zhiru Zhang:
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis. ACM Trans. Design Autom. Electr. Syst. 16(1): 4:1-4:29 (2010) - [j73]Deming Chen, Jason Cong, Yiping Fan, Lu Wan:
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization. IEEE Trans. Very Large Scale Integr. Syst. 18(4): 564-577 (2010) - [c200]Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon:
Logic-on-logic 3D integration and placement. 3DIC 2010: 1-4 - [c199]Jason Cong, Chunyue Liu, Glenn Reinman:
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. DAC 2010: 443-448 - [c198]Jason Cong, Kirill Minkovich:
LUT-based FPGA technology mapping for reliability. DAC 2010: 517-522 - [c197]Jason Cong, Hui Huang, Wei Jiang:
A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis. DATE 2010: 1255-1260 - [c196]Jason Cong, Bin Liu, Junjuan Xu:
Coordinated resource optimization in behavioral synthesis. DATE 2010: 1267-1272 - [c195]Jason Cong, Yi Zou:
A Comparative Study on the Architecture Templates for Dynamic Nested Loops. FCCM 2010: 251-254 - [c194]Jiyu Zhang, Zhiru Zhang, Sheng Zhou, Mingxing Tan, Xianhua Liu, Xu Cheng, Jason Cong:
Bit-level optimization for high-level synthesis and FPGA-based acceleration. FPGA 2010: 59-68 - [c193]Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou:
Accelerating Monte Carlo based SSTA using FPGA. FPGA 2010: 111-114 - [c192]Jason Cong, Kirill Minkovich:
LUT-based FPGA technology mapping for reliability (abstract only). FPGA 2010: 288 - [c191]Jason Cong, Guojie Luo:
An analytical placer for mixed-size 3D placement. ISPD 2010: 61-66
2000 – 2009
- 2009
- [j72]Jason Cong, Wolfgang Rosenstiel:
The Last Byte: The HLS tipping point. IEEE Des. Test Comput. 26(4): 104 (2009) - [j71]Jason Cong, Yiping Fan, Junjuan Xu:
Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture. ACM Trans. Design Autom. Electr. Syst. 14(3): 35:1-35:31 (2009) - [j70]Jason Cong, Yi Zou:
FPGA-Based Hardware Acceleration of Lithographic Aerial Image Simulation. ACM Trans. Reconfigurable Technol. Syst. 2(3): 17:1-17:29 (2009) - [j69]Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang:
Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1318-1329 (2009) - [c190]Jason Cong, Puneet Gupta, John Lee:
On the futility of statistical power optimization. ASP-DAC 2009: 167-172 - [c189]Jason Cong, Guojie Luo:
A multilevel analytical placement for 3D ICs. ASP-DAC 2009: 361-366 - [c188]Jason Cong, Albert Liu, Bin Liu:
A variation-tolerant scheduler for better than worst-case behavioral synthesis. CODES+ISSS 2009: 221-228 - [c187]Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork:
Moore's Law: another casualty of the financial meltdown? DAC 2009: 202-203 - [c186]Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach:
From milliwatts to megawatts: system level power challenge. DAC 2009: 750-751 - [c185]Jason Cong, Karthik Gururaj:
Energy efficient multiprocessor task scheduling under input-dependent variation. DATE 2009: 411-416 - [c184]Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Zhiru Zhang, Sheng Zhou, Yi Zou:
Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. FCCM 2009: 231-234 - [c183]Jason Cong, Karthik Gururaj, Guoling Han:
Synthesis of reconfigurable high-performance multicore systems. FPGA 2009: 201-208 - [c182]Jason Cong, Karthik Gururaj, Bin Liu, Chunyue Liu, Yi Zou, Zhiru Zhang, Sheng Zhou:
Revisiting bitwidth optimizations. FPGA 2009: 278 - [c181]Jason Cong:
Customizable domain-specific computing. FPL 2009: 1 - [c180]Jason Cong, Bin Liu, Zhiru Zhang:
Scheduling with soft constraints. ICCAD 2009: 47-54 - [c179]Tony F. Chan, Jason Cong, Eric Radke:
A rigorous framework for convergent net weighting schemes in timing-driven placement. ICCAD 2009: 288-294 - [c178]Jason Cong, Yi Zou:
Parallel multi-level analytical global placement on graphics processing units. ICCAD 2009: 681-688 - [c177]Jason Cong, Wei Jiang, Bin Liu, Yi Zou:
Automatic memory partitioning and scheduling for throughput and power optimization. ICCAD 2009: 697-704 - [c176]Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
High-performance CUDA kernel execution on FPGAs. ICS 2009: 515-516 - [c175]Jason Cong, Bin Liu, Zhiru Zhang:
Behavior-level observability don't-cares and application to low-power behavioral synthesis. ISLPED 2009: 139-144 - [c174]Suk-Bok Lee, Sai-Wang Tam, Ioannis Pefkianakis, Songwu Lu, M. Frank Chang, Chuanxiong Guo, Glenn Reinman, Chunyi Peng, Mishali Naik, Lixia Zhang, Jason Cong:
A scalable micro wireless interconnect structure for CMPs. MobiCom 2009: 217-228 - [c173]Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs. SASP 2009: 35-42 - [c172]Jason Cong, Mau-Chung Frank Chang, Glenn Reinman, Sai-Wang Tam:
Multiband RF-interconnect for reconfigurable network-on-chip communications. SLIP 2009: 107-108 - 2008
- [j68]Yuan Xie, Jason Cong, Paul D. Franzon:
Editorial: Special issue on 3D integrated circuits and microarchitectures. ACM J. Emerg. Technol. Comput. Syst. 4(4): 15:1-15:2 (2008) - [j67]Yuchun Ma, Yongxiang Liu, Eren Kursun, Glenn Reinman, Jason Cong:
Investigating the effects of fine-grain three-dimensional integration on microarchitecture design. ACM J. Emerg. Technol. Comput. Syst. 4(4): 17:1-17:30 (2008) - [j66]Jason Cong, Min Xie:
A Robust Mixed-Size Legalization and Detailed Placement Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1349-1362 (2008) - [j65]Jason Cong, Guojie Luo, Eric Radke:
Highly Efficient Gradient Computation for Density-Constrained Analytical Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(12): 2133-2144 (2008) - [c171]Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. ASP-DAC 2008: 10-15 - [c170]Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong:
Scheduling with integer time budgeting for low-power optimization. ASP-DAC 2008: 22-27 - [c169]Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. ASP-DAC 2008: 209-212 - [c168]Jason Cong, Junjuan Xu:
Simultaneous FU and Register Binding Based on Network Flow Method. DATE 2008: 1057-1062 - [c167]Kirill Minkovich, Jason Cong:
Mapping for better than worst-case delays in LUT-based FPGA designs. FPGA 2008: 56-64 - [c166]Jason Cong, Yi Zou:
Lithographic aerial image simulation with FPGA-based hardwareacceleration. FPGA 2008: 67-76 - [c165]Jason Cong, Wei Jiang:
Pattern-based behavior synthesis for FPGA resource reduction. FPGA 2008: 107-116 - [c164]M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam:
CMP network-on-chip overlaid with multi-band RF-interconnect. HPCA 2008: 191-202 - [c163]Jason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman:
MC-Sim: an efficient simulation tool for MPSoC designs. ICCAD 2008: 364-371 - [c162]Amit Agarwal, Jason Cong, Brian Tagiku:
Fault tolerant placement and defect reconfiguration for nano-FPGAs. ICCAD 2008: 714-721 - [c161]Jason Cong, John Lee, Lieven Vandenberghe:
Robust gate sizing via mean excess delay minimization. ISPD 2008: 10-14 - [c160]Jason Cong, Guojie Luo:
Highly efficient gradient computation for density-constrained analytical placement methods. ISPD 2008: 39-46 - [c159]M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman:
RF interconnects for communications on-chip. ISPD 2008: 78-83 - [c158]M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam:
Power reduction of CMP communication networks via RF-interconnects. MICRO 2008: 376-387 - [c157]Jason Cong:
A new generation of C-base synthesis tool and domain-specific computing. SoCC 2008: 386 - [r3]Jason Cong, Yuzheng Ding:
FPGA Technology Mapping. Encyclopedia of Algorithms 2008 - [r2]Jason Cong, Joseph R. Shinnerl:
Enhancing Placement with Multilevel Techniques. Handbook of Algorithms for Physical Design Automation 2008 - 2007
- [j64]Jason Cong, Kirill Minkovich:
Optimality Study of Logic Synthesis for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 230-239 (2007) - [j63]Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-Driven Placement and White Space Allocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 858-871 (2007) - [j62]Jason Cong, Guoling Han, Ashok Jagannathan, Glenn Reinman, Krzysztof Rutkowski:
Accelerating Sequential Applications on CMPs Using Core Spilling. IEEE Trans. Parallel Distributed Syst. 18(8): 1094-1107 (2007) - [c156]Deming Chen, Jason Cong, Yiping Fan, Zhiru Zhang:
High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs. ASP-DAC 2007: 529-534 - [c155]Jason Cong, Guojie Luo, Jie Wei, Yan Zhang:
Thermal-Aware 3D IC Placement Via Transformation. ASP-DAC 2007: 780-785 - [c154]Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou:
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. ASP-DAC 2007: 920-925 - [c153]Jason Cong, Guoling Han, Wei Jiang:
Synthesis of an application-specific soft multiprocessor system. FPGA 2007: 99-107 - [c152]Jason Cong, Kirill Minkovich:
Improved SAT-based Boolean matching using implicants for LUT-based FPGAs. FPGA 2007: 139-147 - [c151]Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinman, Jason Cong:
Fine grain 3D integration for microarchitecture design through cube packing exploration. ICCD 2007: 259-266 - [p1]Jason Cong, Michalis Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie:
Locality and Utilization in Placement Suboptimality. Modern Circuit Placement 2007: 13-36 - [e3]Gi-Joon Nam, Jason Cong:
Modern Circuit Placement, Best Practices and Results. Springer 2007, ISBN 978-0-387-36837-5 [contents] - [r1]Joseph R. Shinnerl, Jason Cong:
Large-Scale Global Placement. Handbook of Approximation Algorithms and Metaheuristics 2007 - 2006
- [j61]Deming Chen, Jason Cong, Peichen Pan:
FPGA Design Automation: A Survey. Found. Trends Electron. Des. Autom. 1(3) (2006) - [j60]Jason Cong, Michail Romesis, Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(9): 1719-1732 (2006) - [j59]Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong:
Protecting Combinational Logic Synthesis Solutions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2687-2696 (2006) - [j58]Deming Chen, Jason Cong, Junjuan Xu:
Optimal simultaneous module and multivoltage assignment for low power. ACM Trans. Design Autom. Electr. Syst. 11(2): 362-386 (2006) - [j57]Gang Chen, Jason Cong:
Simultaneous placement with clustering and duplication. ACM Trans. Design Autom. Electr. Syst. 11(3): 740-772 (2006) - [j56]Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and Compiler Optimizations for Data Bandwidth Improvement in Configurable Processors. IEEE Trans. Very Large Scale Integr. Syst. 14(9): 986-997 (2006) - [c150]Jason Cong, Min Xie:
A robust detailed placement for mixed-size IC designs. ASP-DAC 2006: 188-194 - [c149]Jason Cong, Ashok Jagannathan, Yuchun Ma, Glenn Reinman, Jie Wei, Yan Zhang:
An automated design flow for 3D microarchitecture evaluation. ASP-DAC 2006: 384-389 - [c148]Jason Cong, Zhiru Zhang:
An efficient and versatile scheduling algorithm based on SDC formulation. DAC 2006: 433-438 - [c147]Joey Y. Lin, Deming Chen, Jason Cong:
Optimal simultaneous mapping and clustering for FPGA delay optimization. DAC 2006: 472-477 - [c146]Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu:
Optimality study of resource binding with multi-Vdds. DAC 2006: 580-585 - [c145]Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang:
Behavior and communication co-optimization for systems with sequential communication media. DAC 2006: 675-678 - [c144]Jason Cong, Kirill Minkovich:
Optimality study of logic synthesis for LUT-based FPGAs. FPGA 2006: 33-40 - [c143]Jason Cong, Yiping Fan, Wei Jiang:
Platform-based resource binding using a distributed register-file microarchitecture. ICCAD 2006: 709-715 - [c142]Tony F. Chan, Jason Cong, Joseph R. Shinnerl, Kenton Sze, Min Xie:
mPL6: enhanced multilevel mixed-size placement. ISPD 2006: 212-214 - [c141]Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang:
Platform-Based Behavior-Level and System-Level Synthesis. SoCC 2006: 199-202 - 2005
- [j55]Jason Cong, Jie Fang, Min Xie, Yan Zhang:
MARS-a multilevel full-chip gridless routing system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(3): 382-394 (2005) - [j54]Fei Li, Yizhou Lin, Lei He, Deming Chen, Jason Cong:
Power modeling and characteristics of field programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(11): 1712-1724 (2005) - [j53]Jason Cong, Hui Huang, Xin Yuan:
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 10(1): 3-23 (2005) - [j52]Jason Cong, Joseph R. Shinnerl, Min Xie, Tim Kong, Xin Yuan:
Large-scale circuit placement. ACM Trans. Design Autom. Electr. Syst. 10(2): 389-430 (2005) - [c140]Jason Cong, Tony Ma, Ivo Bolsens, Phil Moorby, Jan M. Rabaey, John Sanguinetti, Kazutoshi Wakabayashi, Yoshi Watanabe:
Are we ready for system-level synthesis? ASP-DAC 2005 - [c139]Ashok Jagannathan, Hannah Honghua Yang, Kris Konigsfeld, Dan Milliron, Mosur Mohan, Michail Romesis, Glenn Reinman, Jason Cong:
Microarchitecture evaluation with floorplanning and interconnect pipelining. ASP-DAC 2005: 8-15 - [c138]Jason Cong, Yan Zhang:
Thermal-driven multilevel routing for 3-D ICs. ASP-DAC 2005: 121-126 - [c137]Deming Chen, Jason Cong, Junjuan Xu:
Optimal module and voltage assignment for low-power. ASP-DAC 2005: 850-855 - [c136]Jason Cong, Yiping Fan, Guoling Han, Yizhou Lin, Junjuan Xu, Zhiru Zhang, Xu Cheng:
Bitwidth-aware scheduling and binding in high-level synthesis. ASP-DAC 2005: 856-861 - [c135]Jason Cong, Michail Romesis, Joseph R. Shinnerl:
Fast floorplanning by look-ahead enabled recursive bipartitioning. ASP-DAC 2005: 1119-1122 - [c134]Gang Chen, Jason Cong:
Simultaneous timing-driven placement and duplication. FPGA 2005: 51-59 - [c133]Jason Cong, Yiping Fan, Guoling Han, Ashok Jagannathan, Glenn Reinman, Zhiru Zhang:
Instruction set extension with shadow registers for configurable processors. FPGA 2005: 99-106 - [c132]Jason Cong, Michail Romesis, Joseph R. Shinnerl:
Robust mixed-size placement under tight white-space constraints. ICCAD 2005: 165-172 - [c131]Jason Cong, Guoling Han, Zhiru Zhang:
Architecture and compilation for data bandwidth improvement in configurable embedded processors. ICCAD 2005: 263-270 - [c130]Jason Cong, Yan Zhang:
Thermal via planning for 3-D ICs. ICCAD 2005: 745-752 - [c129]Junjuan Xu, Jason Cong, Xu Cheng:
Lower-bound estimation for multi-bitwidth scheduling. ISCAS (1) 2005: 696-699 - [c128]Jason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir:
Understanding the energy efficiency of SMT and CMP with multiclustering. ISLPED 2005: 48-53 - [c127]Tony F. Chan, Jason Cong, Kenton Sze:
Multilevel generalized force-directed method for circuit placement. ISPD 2005: 185-192 - [c126]Tony F. Chan, Jason Cong, Michail Romesis, Joseph R. Shinnerl, Kenton Sze, Min Xie:
mPL6: a robust multilevel mixed-size placement engine. ISPD 2005: 227-229 - 2004
- [j51]Jason Cong, Sung Kyu Lim:
Edge separability-based circuit clustering with application to multilevel circuit partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 346-357 (2004) - [j50]Chin-Chih Chang, Jason Cong, Michail Romesis, Min Xie:
Optimality and scalability study of existing placement algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 537-549 (2004) - [j49]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for on-chip multicycle communication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(4): 550-564 (2004) - [j48]Jason Cong, Sung Kyu Lim:
Retiming-based timing analysis with an application to mincut-based global placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1684-1692 (2004) - [c125]Deming Chen, Jason Cong:
Register binding and port assignment for multiplexer optimization. ASP-DAC 2004: 68-73 - [c124]Nitin Deo, Behrooz Zahiri, Ivo Bolsens, Jason Cong, Bhusan Gupta, Philip Lopresti, Christopher B. Reynolds, Chris Rowen, Ray Simar:
What happened to ASIC?: Go (recon)figure? DAC 2004: 185 - [c123]Jason Cong, Yiping Fan, Zhiru Zhang:
Architecture-level synthesis for automatic interconnect pipelining. DAC 2004: 602-607 - [c122]Fei Li, Yan Lin, Lei He, Jason Cong:
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. FPGA 2004: 42-50 - [c121]Deming Chen, Jason Cong, Fei Li, Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 - [c120]Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang:
Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189 - [c119]Gang Chen, Jason Cong:
Simultaneous Timing Driven Clustering and Placement for FPGAs. FPL 2004: 158-167 - [c118]Jason Cong, Jie Wei, Yan Zhang:
A thermal-driven floorplanning algorithm for 3D ICs. ICCAD 2004: 306-313 - [c117]Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-driven placement and white space allocation. ICCAD 2004: 394-401 - [c116]Deming Chen, Jason Cong:
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs. ICCAD 2004: 752-759 - [c115]Deming Chen, Jason Cong:
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. ISLPED 2004: 70-73 - [c114]Jason Cong, Gabriele Nataneli, Michail Romesis, Joseph R. Shinnerl:
An area-optimality study of floorplanning. ISPD 2004: 78-83 - 2003
- [j47]Chin-Chih Chang, Jason Cong, David Zhigang Pan, Xin Yuan:
Multilevel global placement with congestion control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4): 395-409 (2003) - [j46]Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1424-1431 (2003) - [c113]Chin-Chih Chang, Jason Cong, Xin Yuan:
Multi-level placement for large-scale mixed-size IC designs. ASP-DAC 2003: 325-330 - [c112]Chin-Chih Chang, Jason Cong, Min Xie:
Optimality and scalability study of existing placement algorithms. ASP-DAC 2003: 621-627 - [c111]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle on-chip communication. CODES+ISSS 2003: 77-78 - [c110]Jason Cong, Ashok Jagannathan, Glenn Reinman, Michail Romesis:
Microarchitecture evaluation with physical planning. DAC 2003: 32-35 - [c109]Jason Cong, Xin Yuan:
Multilevel global placement with retiming. DAC 2003: 208-213 - [c108]Fei Li, Deming Chen, Lei He, Jason Cong:
Architecture evaluation for power-efficient FPGAs. FPGA 2003: 175-184 - [c107]Tony F. Chan, Jason Cong, Tim Kong, Joseph R. Shinnerl, Kenton Sze:
An Enhanced Multilevel Algorithm for Circuit Placement. ICCAD 2003: 299-306 - [c106]Jason Cong, Michail Romesis, Min Xie:
Optimality and Stability Study of Timing-Driven Placement Algorithms. ICCAD 2003: 472-479 - [c105]Zhiru Zhang, Yiping Fan, Miodrag Potkonjak, Jason Cong:
Gradual Relaxation Techniques with Applications to Behavioral Synthesis. ICCAD 2003: 529-535 - [c104]Jason Cong, Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang:
Architectural Synthesis Integrated with Global Placement for Multi-Cycle Communication. ICCAD 2003: 536-543 - [c103]Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie, Xin Yuan:
Large-Scale Circuit Placement: Gap and Promise. ICCAD 2003: 883-890 - [c102]Deming Chen, Jason Cong, Yiping Fan:
Low-power high-level synthesis for FPGA architectures. ISLPED 2003: 134-139 - [c101]Jason Cong, Michail Romesis, Min Xie:
Optimality, scalability and stability study of partitioning and placement algorithms. ISPD 2003: 88-94 - [c100]Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang:
Architecture and synthesis for multi-cycle communication. ISPD 2003: 190-196 - 2002
- [j45]Jason Cong, David Zhigang Pan:
Wire width planning for interconnect performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 319-329 (2002) - [j44]Taku Uchino, Jason Cong:
An interconnect energy model considering coupling effects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 763-776 (2002) - [c99]Jason Cong, Yizhou Lin, Wangning Long:
SPFD-based global rewiring. FPGA 2002: 77-84 - [c98]Jason Cong, Min Xie, Yan Zhang:
An enhanced multilevel routing system. ICCAD 2002: 51-58 - [c97]Jason Cong, Joey Y. Lin, Wangning Long:
A new enhanced SPFD rewiring algorithm. ICCAD 2002: 672-678 - [c96]Chin-Chih Chang, Jason Cong, David Zhigang Pan:
Physical hierarchy generation with routing congestion control. ISPD 2002: 36-41 - [c95]Jason Cong, Chang Wu:
Global clustering-based performance-driven circuit partitioning. ISPD 2002: 149-154 - [c94]Jason Cong:
Timing closure based on physical hierarchy. ISPD 2002: 170-174 - [c93]Jason Cong, Joey Y. Lin, Wangning Long:
Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS 2002: 91-96 - 2001
- [j43]Jason Cong:
An interconnect-centric design flow for nanometer technologies. Proc. IEEE 89(4): 505-528 (2001) - [j42]Chin-Chih Chang, Jason Cong:
Pseudopin assignment with crosstalk noise control. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 598-611 (2001) - [j41]Jason Cong, Jie Fang, Kei-Yong Khoo:
DUNE-a multilayer gridless routing system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(5): 633-647 (2001) - [j40]Jason Cong, David Zhigang Pan:
Interconnect performance estimation models for design planning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 739-752 (2001) - [j39]Jason Cong, Yean-Yow Hwang:
Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1077-1090 (2001) - [j38]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Interconnect sizing and spacing with consideration of couplingcapacitance. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9): 1164-1169 (2001) - [j37]Jason Cong, Cheng-Kok Koh, Patrick H. Madden:
Interconnect layout optimization under higher order RLC model forMCM designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1455-1463 (2001) - [j36]Jason Cong, Tianming Kong, Z. D. Pan:
Buffer block planning for interconnect planning and prediction. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 929-937 (2001) - [c92]Jason Cong, David Zhigang Pan, Prasanna V. Srinivas:
Improved crosstalk modeling for noise constrained interconnect optimization. ASP-DAC 2001: 373-378 - [c91]Jason Cong, Michail Romesis:
Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping. DAC 2001: 389-394 - [c90]Taku Uchino, Jason Cong:
An Interconnect Energy Model Considering Coupling Effects. DAC 2001: 555-558 - [c89]Deming Chen, Jason Cong, Milos D. Ercegovac, Zhijun Huang:
Performance-driven mapping for CPLD architectures. FPGA 2001: 39-47 - [c88]Gang Chen, Jason Cong:
Simultaneous logic decomposition with technology mapping in FPGA designs. FPGA 2001: 48-55 - [c87]Jason Cong, Jie Fang, Yan Zhang VI:
Multilevel Approach to Full-Chip Gridless Routing. ICCAD 2001: 396-403 - 2000
- [j35]Jason Cong, Jie Fang, Kei-Yong Khoo:
Via design rule consideration in multilayer maze routing algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 215-223 (2000) - [j34]Jason Cong, Songjie Xu:
Performance-driven technology mapping for heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1268-1281 (2000) - [j33]Jason Cong, Yean-Yow Hwang:
Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA designs. ACM Trans. Design Autom. Electr. Syst. 5(2): 193-225 (2000) - [c86]Jason Cong, Songjie Xu:
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs. ASP-DAC 2000: 157-162 - [c85]Jason Cong, Tianming Kong, Faming Liang, Jun S. Liu, Wing Hung Wong, Dongmin Xu:
Dynamic weighting Monte Carlo for constrained floorplan designs in mixed signal application. ASP-DAC 2000: 277-282 - [c84]Jason Cong, Sung Kyu Lim:
Edge separability based circuit clustering with application to circuit partitioning. ASP-DAC 2000: 429-434 - [c83]Jason Cong, Sung Kyu Lim:
Performance driven multiway partitioning. ASP-DAC 2000: 441-446 - [c82]Maogang Wang, Sung Kyu Lim, Jason Cong, Majid Sarrafzadeh:
Multi-way partitioning using bi-partition heuristics. ASP-DAC 2000: 667-672 - [c81]Jason Cong, Sung Kyu Lim, Chang Wu:
Performance driven multi-level and multiway partitioning with retiming. DAC 2000: 274-279 - [c80]Jason Cong, Hui Huang:
Depth optimal incremental mapping for field programmable gate arrays. DAC 2000: 290-293 - [c79]Jason Cong, Xin Yuan:
Routing tree construction under fixed buffer locations. DAC 2000: 379-384 - [c78]Jason Cong, Hui Huang, Xin Yuan:
Technology mapping for k/m-macrocell based FPGAs. FPGA 2000: 51-59 - [c77]Jason Cong, Kenneth Yan:
Synthesis for FPGAs with embedded memory blocks. FPGA 2000: 75-82 - [c76]Jason Cong, Sung Kyu Lim:
Physical Planning with Retiming. ICCAD 2000: 2-7 - [c75]Tony F. Chan, Jason Cong, Tianming Kong, Joseph R. Shinnerl:
Multilevel Optimization for Large-Scale Circuit Placement. ICCAD 2000: 171-176 - [c74]Olivier Coudert, Jason Cong, Sharad Malik, Majid Sarrafzadeh:
Incremental CAD. ICCAD 2000: 236-243 - [c73]Jason Cong, Jie Fang, Kei-Yong Khoo:
DUNE: a multi-layer gridless routing system with wire planning. ISPD 2000: 12-18 - [c72]Chin-Chih Chang, Jason Cong:
Pseudo pin assignment with crosstalk noise control. ISPD 2000: 41-47 - [c71]Jason Cong, Majid Sarrafzadeh:
Incremental physical design. ISPD 2000: 84-92
1990 – 1999
- 1999
- [j32]Jason Cong, Lei He:
Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(4): 406-420 (1999) - [j31]Chin-Chih Chang, Jason Cong:
An efficient approach to multilayer layer assignment with anapplication to via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 608-620 (1999) - [j30]Jason Cong, Chang Wu:
Optimal FPGA mapping and retiming with efficient initial state computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(11): 1595-1607 (1999) - [c70]Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong:
Relaxed Simulated Tempering for VLSI Floorplan Designs. ASP-DAC 1999: 13-16 - [c69]Jason Cong, David Zhigang Pan:
Interconnect Delay Estimation Models for Synthesis and Design Planning. ASP-DAC 1999: 97-100 - [c68]Jason Cong, Yean-Yow Hwang, Songjie Xu:
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections. DAC 1999: 373-378 - [c67]Jason Cong, Honching Li, Chang Wu:
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization. DAC 1999: 460-465 - [c66]Jason Cong, David Zhigang Pan:
Interconnect Estimation and Dlanning for Deep Submicron Designs. DAC 1999: 507-510 - [c65]Jason Cong, Chang Wu, Yuzheng Ding:
Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution. FPGA 1999: 29-35 - [c64]Jason Cong, Jie Fang, Kei-Yong Khoo:
An implicit connection graph maze routing algorithm for ECO routing. ICCAD 1999: 163-167 - [c63]Jason Cong, Tianming Kong, David Zhigang Pan:
Buffer block planning for interconnect-driven floorplanning. ICCAD 1999: 358-363 - [c62]Jason Cong, Jie Fang, Kei-Yong Khoo:
VIA design rule consideration in multi-layer maze routing algorithms. ISPD 1999: 214-220 - [e2]Farid N. Najm, Jason Cong, David T. Blaauw:
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999, San Diego, California, USA, August 16-17, 1999. ACM 1999, ISBN 1-58113-133-X [contents] - 1998
- [j29]Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
Efficient algorithms for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 24-39 (1998) - [j28]Jason Cong, Chang Wu:
An efficient algorithm for performance-optimal FPGA technology mapping with retiming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(9): 738-748 (1998) - [j27]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing. ACM Trans. Design Autom. Electr. Syst. 3(3): 341-388 (1998) - [c61]Jason Cong, Chang Wu:
Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. DAC 1998: 330-335 - [c60]Jason Cong, Patrick H. Madden:
Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. DAC 1998: 356-361 - [c59]Jason Cong, Songjie Xu:
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. DAC 1998: 704-707 - [c58]Jason Cong, Yean-Yow Hwang:
Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation. FPGA 1998: 27-34 - [c57]Jason Cong, Songjie Xu:
Technology Mapping for FPGAs with Embedded Memory Blocks. FPGA 1998: 179-188 - [c56]Robert C. Aitken, Jason Cong, Randy Harr, Kenneth L. Shepard, Wayne H. Wolf:
How will CAD handle billion-transistor systems? (panel). ICCAD 1998: 5 - [c55]Jason Cong, Songjie Xu:
Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources. ICCAD 1998: 40-44 - [c54]Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak, Jason Cong:
Intellectual property protection by watermarking combinational logic synthesis solutions. ICCAD 1998: 194-198 - [c53]Jason Cong, Sung Kyu Lim:
Multiway partitioning with pairwise movement. ICCAD 1998: 512-516 - [c52]Jason Cong, Lei He:
An efficient technique for device and interconnect optimization in deep submicron designs. ISPD 1998: 45-51 - [e1]Jason Cong, Sinan Kaptanoglu:
Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998. ACM 1998, ISBN 0-89791-978-5 [contents] - 1997
- [j26]Jason Cong, Patrick H. Madden:
Performance-driven routing with multiple sources. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(4): 410-419 (1997) - [c51]Chin-Chih Chang, Jason Cong:
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. DAC 1997: 600-603 - [c50]Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632 - [c49]Jason Cong, Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC 1997: 644-649 - [c48]Jason Cong, John Peck:
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessor. FCCM 1997: 246-248 - [c47]Jason Cong, Yean-Yow Hwang:
Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping. FPGA 1997: 35-42 - [c46]Jason Cong, Honching Peter Li, Sung Kyu Lim, Toshiyuki Shibuya, Dongmin Xu:
Large scale circuit partitioning with loose/stable net removal and signal flow based clustering. ICCAD 1997: 441-446 - [c45]Jason Cong, David Zhigang Pan, Lei He, Cheng-Kok Koh, Kei-Yong Khoo:
Interconnect design for deep submicron ICs. ICCAD 1997: 478-485 - [c44]Jason Cong, Lei He, Cheng-Kok Koh, David Zhigang Pan:
Global interconnect sizing and spacing with consideration of coupling capacitance. ICCAD 1997: 628-633 - [c43]Jason Cong, Cheng-Kok Koh:
Interconnect layout optimization under higher-order RLC model. ICCAD 1997: 713-720 - [c42]Jason Cong, Patrick H. Madden:
Performance driven global routing for standard cell design. ISPD 1997: 73-80 - [c41]Jason Cong, Andrew B. Kahng, Kwok-Shing Leung:
Efficient heuristics for the minimum shortest path Steiner arborescence problem with applications to VLSI physical design. ISPD 1997: 88-95 - 1996
- [j25]Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden:
Performance optimization of VLSI interconnect layout. Integr. 21(1-2): 1-94 (1996) - [j24]Jason Cong, Wilburt Labio, Narayanan Shivakumar:
Multiway VLSI circuit partitioning based on dual net representation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(4): 396-409 (1996) - [j23]Jason Cong, Yuzheng Ding:
Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Design Autom. Electr. Syst. 1(2): 145-204 (1996) - [j22]Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources. ACM Trans. Design Autom. Electr. Syst. 1(4): 478-511 (1996) - [c40]Jason Cong, Yean-Yow Hwang:
Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. DAC 1996: 726-729 - [c39]Jason Cong, John Peck, Yuzheng Ding:
RASP: A General Logic Synthesis System for SRAM-Based FPGAs. FPGA 1996: 137-143 - [c38]Takumi Okamoto, Jason Cong:
Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ICCAD 1996: 44-49 - [c37]Jason Cong, Lei He:
An efficient approach to simultaneous transistor and interconnect sizing. ICCAD 1996: 181-186 - [c36]Jason Cong, Chang Wu:
An Improved Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Desig. ICCD 1996: 572-578 - [c35]Jason Cong, Cheng-Kok Koh, Kwok-Shing Leung:
Simultaneous buffer and wire sizing for performance and power optimization. ISLPED 1996: 271-276 - 1995
- [j21]Leonard Kleinrock, Mario Gerla, Nicholas Bambos, Jason Cong, Eli Gafni, Larry Bergman, Joseph A. Bannister:
The Supercomputer Supernet: A Scalable Distributed Terabit Network. J. High Speed Networks 4(4): 407-424 (1995) - [j20]Jason Cong, Kwok-Shing Leung:
Optimal wiresizing under Elmore delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 321-336 (1995) - [j19]Kei-Yong Khoo, Jason Cong:
An efficient multilayer MCM router based on four-via routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1277-1290 (1995) - [c34]Jason Cong, Dongmin Xu:
Exploitation signal flow and logic dependency in standard cell placement. ASP-DAC 1995 - [c33]Jason Cong, Yean-Yow Hwang:
Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping. FPGA 1995: 68-74 - [c32]Jason Cong, Yuzheng Ding:
On Nominal Delay Minimization in LUT-based FPGA Technology Mapping. FPGA 1995: 82-88 - [c31]Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing under Elmore delay. ICCAD 1995: 66-71 - [c30]Jason Cong, Lei He:
Optimal wiresizing for interconnects with multiple sources. ICCAD 1995: 568-574 - [c29]Jason Cong, Patrick H. Madden:
Performance Driven Routing with Mulitiple Sources. ISCAS 1995: 203-206 - [c28]Jason Cong, Cheng-Kok Koh:
Minimum-Cost Bounded-Skew Clock Routing. ISCAS 1995: 215-218 - 1994
- [j18]Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen:
LUT-based FPGA technology mapping under arbitrary net-delay models. Comput. Graph. 18(4): 507-516 (1994) - [j17]Jason Cong, Yuzheng Ding:
On nominal delay minimization in LUT-based FPGA technology mapping. Integr. 18(1): 73-94 (1994) - [j16]Jason Cong, Yuzheng Ding:
FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(1): 1-12 (1994) - [j15]Jason Cong, Yuzheng Ding:
On area/depth trade-off in LUT-based FPGA technology mapping. IEEE Trans. Very Large Scale Integr. Syst. 2(2): 137-148 (1994) - [j14]Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. IEEE Trans. Very Large Scale Integr. Syst. 2(4): 408-425 (1994) - [j13]Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
On the Minimum Density Interconnection Tree Problem. VLSI Design 2(2): 157-169 (1994) - [j12]Yang Cai, D. F. Wong, Jason Cong:
Channel Density Minimization by Pin Permutation. VLSI Design 2(2): 171-183 (1994) - [c27]Jason Cong, Zheng Li, Rajive L. Bagrodia:
Acyclic Multi-Way Partitioning of Boolean Networks. DAC 1994: 670-675 - [c26]Jason Cong, Wilburt Labio, Narayanan Shivakumar:
Multi-way VLSI circuit partitioning based on dual net representation. ICCAD 1994: 56-62 - [c25]Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization. ICCAD 1994: 206-212 - [c24]Rajive L. Bagrodia, Zheng Li, Vikas Jha, Yuan Chen, Jason Cong:
Parallel logic level simulation of VLSI circuits. WSC 1994: 1354-1361 - 1993
- [j11]Jason Cong, Moazzem Hossain, Naveed A. Sherwani:
A provably good multilayer topological planar routing algorithm in IC layout designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1): 70-78 (1993) - [j10]Jason Cong, Bryan Preas, C. L. Liu:
Physical models and efficient algorithms for over-the-cell routing in standard cell design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 723-734 (1993) - [j9]Jason Cong, Andrew B. Kahng, Gabriel Robins:
Matching-based methods for high-performance clock routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(8): 1157-1169 (1993) - [c23]Jason Cong, Yuzheng Ding:
On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping. DAC 1993: 213-218 - [c22]Kei-Yong Khoo, Jason Cong:
An Efficient Multilayer MCM Router Based on Four-Via Routing. DAC 1993: 590-595 - [c21]Jason Cong, Kwok-Shing Leung, Dian Zhou:
Performance-Driven Interconnect Design Based on Distributed RC Delay Model. DAC 1993: 606-611 - [c20]Jason Cong, M'Lissa Smith:
A Parallel Bottom-Up Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design. DAC 1993: 755-760 - [c19]Jason Cong, Yuzheng Ding:
Beyond the combinatorial limit in depth minimization for LUT-based FPGA designs. ICCAD 1993: 110-114 - [c18]Jason Cong, Kwok-Shing Leung:
Optimal wiresizing under the distributed Elmore delay model. ICCAD 1993: 634-639 - [c17]Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh:
Minimum Density Interconneciton Trees. ISCAS 1993: 1865-1868 - [c16]Dian Zhou, S. Su, F. Tsui, D. S. Gao, Jason Cong:
A Two-pole Circuit Model for VLSI High-speed Interconnection. ISCAS 1993: 2129-2132 - [c15]Jason Cong, Moazzem Hossain, Naveed A. Sherwani:
A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. VLSI Design 1993: 113 - 1992
- [j8]Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar:
DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. IEEE Des. Test Comput. 9(3): 7-20 (1992) - [j7]Jason Cong, Bryan Preas:
A new algorithm for standard cell global routing. Integr. 14(1): 49-65 (1992) - [j6]Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, Chak-Kuen Wong:
Provably good performance-driven global routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(6): 739-752 (1992) - [c14]Jason Cong, Lars W. Hagen, Andrew B. Kahng:
Net Partitions Yield Better Module Partitions. DAC 1992: 47-52 - [c13]Kuang-Chien Chen, Jason Cong:
Maximal reduction of lookup-table based FPGAs. EURO-DAC 1992: 224-229 - [c12]Kei-Yong Khoo, Jason Cong:
A fast multilayer general area router for MCM designs. EURO-DAC 1992: 292-297 - [c11]Jason Cong, Yuzheng Ding:
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. ICCAD 1992: 48-53 - [c10]Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen:
An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. ICCD 1992: 154-158 - 1991
- [j5]Khe-Sing The, Martin D. F. Wong, Jason Cong:
A layout modification approach to via minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(4): 536-541 (1991) - [j4]Jason Cong, C. L. Liu:
On the k-layer planar subset and topological via minimization problems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 972-981 (1991) - [j3]Jason Cong:
Pin assignment with global routing for general cell designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(11): 1401-1412 (1991) - [c9]Andrew B. Kahng, Jason Cong, Gabriel Robins:
High-Performance Clock Routing Based on Recursive Geometric Aatching. DAC 1991: 322-327 - [c8]Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh, C. K. Wong:
Performance-Driven Global Routing for Cell Based ICs. ICCD 1991: 170-173 - [c7]Jason Cong, Kei-Yong Khoo:
A Provable Near-Optimal Algorithm for the Channel Pin Assignment Problem. ICCD 1991: 319-322 - 1990
- [j2]Jason Cong, C. L. Liu:
Over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 408-418 (1990) - [c6]Jason Cong, Bryan Preas, C. L. Liu:
General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design. DAC 1990: 709-715 - [c5]Jason Cong, C. L. Liu:
On the k-layer planar subset and via minimization problems. EURO-DAC 1990: 459-463
1980 – 1989
- 1989
- [c4]Khe-Sing The, D. F. Wong, Jason Cong:
VIA Minimization by Layout Modification. DAC 1989: 799-802 - [c3]Jason Cong:
Pin assignment with global routing. ICCAD 1989: 302-305 - [c2]Sai-keung Dong, Jason Cong, C. L. Liu:
Constrained floorplan design for flexible blocks. ICCAD 1989: 488-491 - 1988
- [j1]Jason Cong, Martin D. F. Wong, C. L. Liu:
A new approach to three- or four-layer channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(10): 1094-1104 (1988) - [c1]Nany Hasan, Jason Cong, C. L. Liu:
A new formulation of yield enhancement problems for reconfigurable chips. ICCAD 1988: 520-523
Coauthor Index
Young-kyu Choi
aka: Young Kyu Choi
aka: Young Kyu Choi
David Z. Pan
aka: David Zhigang Pan
aka: David Zhigang Pan
Glenn Reinman
aka: Glenn D. Reinman
aka: Glenn D. Reinman
[j110] [c357] [c313] [c308] [c304] [b1] [c292] [c283] [j99] [c276] [j96] [c243] [j92] [j91] [j88] [c240] [c239] [c238] [c235] [c230] [c229] [c227] [c223] [j87] [c219] [c216] [c207] [c205] [c204] [p2] [c199] [c174] [c172] [j67] [c164] [c163] [c159] [c158] [j62] [c154] [c151] [c149] [c139] [c133] [c128] [c110]
Michail Romesis
aka: Michalis Romesis
aka: Michalis Romesis
Bochen Tan
aka: Daniel Bochen Tan
aka: Daniel Bochen Tan
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