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ORCIDNan Sun 0001
Person information
- affiliation: Tsinghua University, Beijing, China
Other persons with the same name
- Nan Sun — disambiguation page
- Nan Sun 0002
![[0000-0001-9123-9022]](https://dblp1.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-9123-9022")
— University of New South Wales, Canberra, ACT, Australia (and 1 more) - Nan Sun 0003 — University of Texas, Austin, Department of Electrical and Computer Engineering, Austin, TX, USA
- Nan Sun 0004 — Ocean University of China, Qingdao, China
- Nan Sun 0005 — Nanjing University of Science and Technology, Nanjing, China
- Nan Sun 0006 — Yunnan University, Kunming, China
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2020 – today
- 2024
[j57]Jinshan Yue, Yongpan Liu, Xiaoyu Feng, Yifan He, Jingyu Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hong, Meng-Fan Chang, Nan Sun, Chunmeng Dou, Xueqing Li, Ming Liu, Huazhong Yang:
An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. IEEE J. Solid State Circuits 59(5): 1612-1627 (2024)- [j56]Mingtao Zhan, Lu Jie, Xiyuan Tang, Yi Zhong, Nan Sun:
A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp. IEEE J. Solid State Circuits 59(7): 2209-2218 (2024) - [j55]Chang Liu, Jiaxin Liu, Nan Sun:
Mitigating Sampling Noise for Energy-Efficient ADCs: A Tutorial Brief. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1638-1643 (2024) - [c98]Chengyu Huang, Kezhuo Ma, Sihao Chen, Jiaxuan Fan, Nan Sun, Huazhong Yang, Xueqing Li:
A 16-bit 10-GS/s Calibration-Free DAC Achieving <-77dBc IM3 up to 4.95GHz in 28nm CMOS. CICC 2024: 1-2 - [c97]Yunsong Tao, Yi Zhong, Jin Shao, Changyou Men, Lu Jie, Nan Sun:
A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs. ISCAS 2024: 1-5 - [c96]Xiyu He, Mingyang Gu, Hanjun Jiang, Yi Zhong, Nan Sun, Lu Jie:
9.3 A 71dB SNDR 200MHz BW Interleaved Pipe-SAR ADC with a Shared Residue Integrating Amplifier Achieving 173dB FoMs. ISSCC 2024: 172-174 - [c95]Yunsong Tao, Mingyang Gu, Baoyong Chi, Yi Zhong, Lu Jie, Nan Sun:
22.4 A 4.8GS/s 7-ENoB Time-Interleaved SAR ADC with Dither-Based Background Timing-Skew Calibration and Bit-Distribution-Based Background Ping-Pong Comparator Offset Calibration. ISSCC 2024: 394-396 - 2023
- [j54]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. IEEE J. Solid State Circuits 58(5): 1450-1461 (2023) - [j53]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun:
A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits 58(9): 2564-2574 (2023) - [j52]Xiangxing Yang, Nan Sun:
A 4-Bit Mixed-Signal MAC Macro With One-Shot ADC Conversion. IEEE J. Solid State Circuits 58(9): 2648-2658 (2023) - [j51]Mingtao Zhan, Lu Jie, Yi Zhong, Nan Sun:
A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. IEEE J. Solid State Circuits 58(12): 3576-3585 (2023) - [j50]Yushen Fu, Chengyu Huang, Longqiang Lai, Nan Sun, Xueqing Li, Huazhong Yang:
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging. IEEE Trans. Circuits Syst. I Regul. Pap. 70(5): 1856-1867 (2023) - [j49]Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Xingyuan Tong, Nan Sun:
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2293-2305 (2023) - [c94]Zhishuai Zhang, Zijie Gao, Siyu Huang, Nan Sun, Lu Jie:
A 1GS/s6-Core Programmable A/D Converter Array Supporting Architecture Restructuring and Multitasking. CICC 2023: 1-2 - [c93]Yi Zhong, Mingtao Zhan, Wei Wang, Xiyuan Tang, Lu Jie, Nan Sun:
An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. CICC 2023: 1-2 - [c92]Haoyu Zhuang, Nan Sun, Yirui Cao, Linzhi Tao, Qiang Li:
A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. CICC 2023: 1-2 - [c91]Haoyu Zhuang, Nan Sun, Linzhi Tao, Yizhan Li, Oiang Li:
A Fully-Dynamic kT/C-Noise-Canceled SAR ADC with Trimming-Free Dynamic Amplifier. CICC 2023: 1-2 - [c90]Mingyang Gu, Yunsong Tao, Xiyu He, Yi Zhong, Lu Jie, Nan Sun:
A 3.7mW 11b 1GS/s Time-Interleaved SAR ADC with Robust One-Stage Correlation-Based Background Timing-Skew Calibration. ESSCIRC 2023: 145-148 - [c89]Chaoyang Xing, Yi Zhong, Nan Sun, Lu Jie:
A 0.021mm2 92dB-SNDR 88kHz-BW Incremental Zoom ADC with 2nd-order RT-DEM and Quiet Chopping. ESSCIRC 2023: 293-296 - [c88]Mingyang Gu, Yi Zhong, Lu Jie, Nan Sun:
A 12b 1GS/s Pipelined ADC with Digital Background Calibration of Inter-stage Gain, Capacitor Mismatch, and Kick-back Errors. ESSCIRC 2023: 329-332 - [c87]Tianrui Ma, Adith Jagadish Boloor, Xiangxing Yang, Weidong Cao, Patrick Williams, Nan Sun, Ayan Chakrabarti, Xuan Zhang:
LeCA: In-Sensor Learned Compressive Acquisition for Efficient Machine Vision on the Edge. ISCA 2023: 54:1-54:14 - [c86]Mingtao Zhan, Lu Jie, Nan Sun:
A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. ISSCC 2023: 272-273 - [c85]Yu-Cheng Lin, Chanmin Park, Wenda Zhao, Nan Sun, Youngcheol Chae, Chia-Hsiang Yang:
A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing. VLSI Technology and Circuits 2023: 1-2 - [c84]Jinshan Yue, Mingtao Zhan, Zi Wang, Yifan He, Yaolei Li, Songming Yu, Wenyu Sun, Lu Jie, Chunmeng Dou, Xueqing Li, Nan Sun, Huazhong Yang, Ming Liu, Yongpan Liu:
A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j48]Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu:
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1209-1221 (2022) - [j47]Xiyuan Tang, Jiaxin Liu, Yi Shen, Shaolan Li, Linxiao Shen, Arindam Sanyal, Kareem Ragab, Nan Sun:
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2249-2262 (2022) - [j46]Yi Shen, Xiyuan Tang, Xin Xin, Shubin Liu, Zhangming Zhu, Nan Sun:
A 10-bit 100-MS/s SAR ADC With Always-On Reference Ripple Cancellation. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3965-3975 (2022) - [c83]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan:
Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC 2022: 519-525 - [c82]Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun:
A 0.37mm2 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2nd-order Vector-Quantizer DEM. CICC 2022: 1-2 - [c81]Yunsong Tao, Kareem Ragab, Jin Shao, Pengpeng Chen, Yi Zhong, Lu Jie, Nan Sun:
A Fast Converging Correlation-Based Background Timing Skew Calibration Technique by Digital Windowing for Time-Interleaved ADCs. ISCAS 2022: 21-25 - [c80]Chaoyang Xing, Yi Zhong, Jin Shao, Pengpeng Chen, Lu Jie, Nan Sun:
A Second-Order VCO-Based ΔΣ ADC with Fully Digital Feedback Summation. ISCAS 2022: 3215-3218 - [c79]Lu Jie, Mingtao Zhan, Xiyuan Tang, Nan Sun:
A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. ISSCC 2022: 1-3 - [c78]Mingtao Zhan, Lu Jie, Xiyuan Tang, Nan Sun:
A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. ISSCC 2022: 164-166 - [c77]Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun:
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. MLCAD 2022: 35-41 - [i3]Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun:
RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. CoRR abs/2207.06412 (2022) - 2021
- [j45]Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan:
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [j44]Abhishek Mukherjee, Miguel Gandara, Xiangxing Yang, Linxiao Shen, Xiyuan Tang, Chen-Kai Hsu, Nan Sun:
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits 56(2): 476-487 (2021) - [j43]Chen-Kai Hsu, Xiyuan Tang, Jiaxin Liu, Rui Xu, Wenda Zhao, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun:
A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping. IEEE J. Solid State Circuits 56(3): 739-749 (2021) - [j42]Chanmin Park, Wenda Zhao, Injun Park, Nan Sun, Youngcheol Chae:
A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing. IEEE J. Solid State Circuits 56(8): 2503-2515 (2021) - [j41]Haoyu Zhuang, Jiaxin Liu, He Tang, Xizhu Peng, Nan Sun:
A Fully Dynamic Low-Power Wideband Time-Interleaved Noise-Shaping SAR ADC. IEEE J. Solid State Circuits 56(9): 2680-2690 (2021) - [j40]Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Chen-Kai Hsu, Nan Sun:
A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. IEEE J. Solid State Circuits 56(11): 3412-3423 (2021) - [j39]Chuang Wang, Yan Lu, Nan Sun, Rui Paulo Martins:
A 3-Phase Resonant Switched-Capacitor Converter for Data Center 48-V Rack Power Distribution. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2714-2724 (2021) - [j38]Sungjin Hong, Nan Sun:
Portable CMOS NMR System With 50-kHz IF, 10-μs Dead Time, and Frequency Tracking. IEEE Trans. Circuits Syst. I Regul. Pap. 68(11): 4576-4588 (2021) - [j37]Vivek Varier, Nan Sun:
High-Precision ADC Testing With Relaxed Reference Voltage Stationarity. IEEE Trans. Instrum. Meas. 70: 1-9 (2021) - [c76]Hao Chen, Mingjie Liu, Xiyuan Tang, Keren Zhu, Abhishek Mukherjee, Nan Sun, David Z. Pan:
MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC. CICC 2021: 1-2 - [c75]Xiangxing Yang, Keren Zhu, Xiyuan Tang, Meizhi Wang, Mingtao Zhan, Nanshu Lu, Jaydeep P. Kulkarni, David Z. Pan, Yongpan Liu, Nan Sun:
An In-Memory-Computing Charge-Domain Ternary CNN Classifier. CICC 2021: 1-2 - [c74]Yi Zhong, Xiyuan Tang, Jiaxin Liu, Wenda Zhao, Shaolan Li, Nan Sun:
An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer. CICC 2021: 1-2 - [c73]Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap:
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. DAC 2021: 1219-1224 - [c72]Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks. DAC 2021: 1243-1248 - [c71]Chengyu Huang, Yushen Fu, Zekun Yang, Yang Liu, Nan Sun, Xueqing Li, Huazhong Yang:
A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching. ESSCIRC 2021: 495-498 - [c70]Mingjie Liu, Xiyuan Tang, Keren Zhu, Hao Chen, Nan Sun, David Z. Pan:
OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler. ICCAD 2021: 1-9 - [c69]Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun:
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC 2021: 170-172 - [c68]Jinshan Yue, Xiaoyu Feng, Yifan He, Yuxuan Huang, Yipeng Wang, Zhe Yuan, Mingtao Zhan, Jiaxin Liu, Jian-Wei Su, Yen-Lin Chung, Ping-Chun Wu, Li-Yang Hung, Meng-Fan Chang, Nan Sun, Xueqing Li, Huazhong Yang, Yongpan Liu:
A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. ISSCC 2021: 238-240 - [c67]Jiaxin Liu, Dengquan Li, Yi Zhong, Xiyuan Tang, Nan Sun:
27.1 A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering. ISSCC 2021: 369-371 - [c66]Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun:
A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC 2021: 376-378 - [c65]Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun:
A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. ISSCC 2021: 382-384 - [i2]Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap:
DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. CoRR abs/2110.00211 (2021) - 2020
- [j36]Nan Sun, Rui Dong, Shaojun Pei, Changchuan Yin, Stephen S.-T. Yau:
A New Method Based on Coding Sequence Density to Cluster Bacteria. J. Comput. Biol. 27(12): 1688-1698 (2020) - [j35]Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun:
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits 55(2): 356-368 (2020) - [j34]Nan Sun, Qun Jane Gu:
Guest Editorial 2019 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 55(3): 523-524 (2020) - [j33]Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun:
A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction. IEEE J. Solid State Circuits 55(3): 602-614 (2020) - [j32]Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55(3): 666-679 (2020) - [j31]Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits 55(3): 680-692 (2020) - [j30]Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun:
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits 55(4): 1011-1022 (2020) - [j29]Chen-Kai Hsu, Timothy R. Andeen, Nan Sun:
A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping. IEEE J. Solid State Circuits 55(4): 1032-1042 (2020) - [j28]Shaolan Li, David Z. Pan, Nan Sun:
An OTA-Less Second-Order VCO-Based CT $\Delta\Sigma$ Modulator Using an Inherent Passive Integrator and Capacitive Feedback. IEEE J. Solid State Circuits 55(5): 1337-1350 (2020) - [j27]Dengquan Li, Zhangming Zhu, Jiaxin Liu, Haoyu Zhuang, Yintang Yang, Nan Sun:
A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration. IEEE J. Solid State Circuits 55(11): 3051-3063 (2020) - [j26]Xiyuan Tang, Shaolan Li, Xiangxing Yang, Linxiao Shen, Wenda Zhao, Randall P. Williams, Jiaxin Liu, Zhichao Tan, Neal A. Hall, David Z. Pan, Nan Sun:
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(11): 3064-3075 (2020) - [j25]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun:
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55(12): 3248-3259 (2020) - [j24]Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun:
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation. IEEE J. Solid State Circuits 55(12): 3260-3270 (2020) - [j23]Haoyu Zhuang, Xiaodan Xi, Nan Sun, Michael Orshansky:
A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 135-144 (2020) - [c64]Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c63]Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun:
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC 2020: 1-4 - [c62]Chen-Kai Hsu, Xiyuan Tang, Wenda Zhao, Rui Xu, Abhishek Mukherjee, Timothy R. Andeen, Nan Sun:
A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping. CICC 2020: 1-4 - [c61]Haoyu Zhuang, Jiaxin Liu, Nan Sun:
A Fully-Dynamic Time-Interleaved Noise-Shaping SAR ADC Based on CIFF Architecture. CICC 2020: 1-4 - [c60]Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han:
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC 2020: 1-6 - [c59]Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan:
Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC 2020: 1-6 - [c58]Mingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE 2020: 496-501 - [c57]Hao Chen, Keren Zhu, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits. ICCAD 2020: 18:1-18:8 - [c56]Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan:
Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow. ICCAD 2020: 133:1-133:9 - [c55]Yuxuan Huang, Qinghang Zhao, Xiyuan Tang, Fang Su, Nan Sun, Huazhong Yang, Yongpan Liu:
An Energy-Efficient Flexible Capacitive Pressure Sensing System. ISCAS 2020: 1-5 - [c54]Jiaxin Liu, Xing Wang, Zijie Gao, Mingtao Zhan, Xiyuan Tang, Nan Sun:
9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. ISSCC 2020: 158-160 - [c53]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC 2020: 162-164 - [c52]Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun:
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. ISSCC 2020: 258-260 - [c51]Sungjin Hong, Nan Sun:
A Portable NMR System with 50-kHz IF, 10-us Dead Time, and Frequency Tracking. VLSI Circuits 2020: 1-2 - [c50]Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun:
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. VLSI Circuits 2020: 1-2 - [c49]Xiyuan Tang, Yi Shen, Xin Xin, Shubin Liu, Jueping Cai, Zhangming Zhu, Nan Sun:
A 10-Bit 100-MS/s SAR ADC with Always-on Reference Ripple Cancellation. VLSI Circuits 2020: 1-2 - [c48]Wenda Zhao, Chanmin Park, Injun Park, Nan Sun, Youngcheol Chae:
An Always-on 4× Compressive VGA CMOS Imager with 51pJ/Pixel and >32dB PSNR. VLSI Circuits 2020: 1-2 - [i1]Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han:
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR abs/2005.00406 (2020)
2010 – 2019
- 2019
- [j22]Shaolan Li, Arindam Sanyal, Kyoungtae Lee, Yeonam Yoon, Xiyuan Tang, Yi Zhong, Kareem Ragab, Nan Sun:
Advances in Voltage-Controlled-Oscillator-Based ΔΣ ADCs. IEICE Trans. Electron. 102-C(7): 509-519 (2019) - [j21]Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun:
A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT ΔΣ ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer. IEEE J. Solid State Circuits 54(2): 428-440 (2019) - [j20]Haoyu Zhuang, Wenjuan Guo, Jiaxin Liu, He Tang, Zhangming Zhu, Long Chen, Nan Sun:
A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting. IEEE J. Solid State Circuits 54(6): 1636-1647 (2019) - [j19]Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu:
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54(12): 3375-3385 (2019) - [j18]Dengquan Li, Zhangming Zhu, Ruixue Ding, Maliang Liu, Yintang Yang, Nan Sun:
A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs 66-II(1): 16-20 (2019) - [j17]Jiaxin Liu, Chen-Kai Hsu, Xiyuan Tang, Shaolan Li, Guangjun Wen, Nan Sun:
Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1342-1354 (2019) - [j16]Jeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun:
A 10-b 600-MS/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2876-2887 (2019) - [c47]Dengquan Li, Jiaxin Liu, Haoyu Zhuang, Zhangming Zhu, Yintang Yang, Nan Sun:
A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration. CICC 2019: 1-4 - [c46]Shaolan Li, Biying Xu, David Z. Pan, Nan Sun:
A 60-fJ/step 11-ENOB VCO-based CTDSM Synthesized from Digital Standard Cell Library. CICC 2019: 1-4 - [c45]Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC 2019: 1-3 - [c44]Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC 2019: 1-4 - [c43]Yanlong Zhang, Arindam Sanyal, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun:
A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction. CICC 2019: 1-4 - [c42]