Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIEEE Transactions on Very Large Scale Integration Systems, Volume 28
Volume 28, Number 1, January 2020
- Massimo Alioto
:
Editorial on the Opening of the New Editorial Year - The State of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 1-2 - Jan M. Rabaey:
Human-Centric Computing. 3-11 - Xiaoran Wang, Tianwei Liu, Shita Guo, Mitchell A. Thornton, Ping Gui:
A 2.56-Gb/s Serial Wireline Transceiver That Supports an Auxiliary Channel in 65-nm CMOS. 12-22 - Yu-Chuan Lin, Hen-Wai Tsao:
A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS. 23-34 - Yunxuan Yu, Chen Wu, Tiandong Zhao, Kun Wang, Lei He:
OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks. 35-47 - Shihui Yin, Zhewei Jiang, Minkyu Kim, Tushar Gupta, Mingoo Seok, Jae-Sun Seo:
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks. 48-61 - Kangjun Bai, Qiyuan An, Lingjia Liu, Yang Yi:
A Training-Efficient Hybrid-Structured Deep Neural Network With Reconfigurable Memristive Synapses. 62-75 - Adarsha Balaji, Francky Catthoor, Anup Das, Yuefeng Wu, Khanh Huynh, Francesco Dell'Anna, Giacomo Indiveri, Jeffrey L. Krichmar, Nikil D. Dutt, Siebren Schaafsma:
Mapping Spiking Neural Networks to Neuromorphic Hardware. 76-86 - Jaehyeong Sim, Somin Lee, Lee-Sup Kim:
An Energy-Efficient Deep Convolutional Neural Network Inference Processor With Enhanced Output Stationary Dataflow in 65-nm CMOS. 87-100 - Jin Woo Park, Hyokeun Lee, Boyeal Kim, Dong-Goo Kang, Seung Oh Jin, Hyun Kim, Hyuk-Jae Lee:
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement. 101-114 - Julian Faraone, Martin Kumm, Martin Hardieck, Peter Zipf, Xueyuan Liu, David Boland, Philip H. W. Leong:
AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. 115-128 - Muhammad Asif, Xiangzhou Guo, Anyong Hu, Jungang Miao:
An FPGA-Based 1-GHz, 128 × 128 Cross-Correlator for Aperture Synthesis Imaging. 129-141 - Adewale Adetomi, Godwin Enemali, Tughrul Arslan:
Enabling Dynamic Communication for Runtime Circuit Relocation. 142-155 - Irith Pomeranz:
Selection of Primary Output Vectors to Observe Under Multicycle Tests. 156-162 - Pavan Kumar Javvaji, Spyros Tragoudas:
Test Pattern Generation and Critical Path Selection in the Presence of Statistical Delays. 163-173 - Yizhong Liu, Tian Song, Yiqi Zhuang:
A High-Throughput Subspace Pursuit Processor for ECG Recovery in Compressed Sensing Using Square-Root-Free MGS QR Decomposition. 174-187 - Ranendra Kumar Sarma, Mohd. Tasleem Khan, Rafi Ahamed Shaik, Jinti Hazarika:
A Novel Time-Shared and LUT-Less Pipelined Architecture for LMS Adaptive Filter. 188-197 - Zichen Fan, Zheyu Liu, Zheng Qu, Fei Qiao, Qi Wei, Xinjun Liu, Yinan Sun, Shuzheng Xu, Huazhong Yang:
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm. 198-211 - A. R. Aravinth Kumar, Ashudeb Dutta, Bibhu Datta Sahoo:
A Low-Power Reconfigurable Narrowband/Wideband LNA for Cognitive Radio-Wireless Sensor Network. 212-223 - Tomasz Kulej, Fabian Khateb:
A Compact 0.3-V Class AB Bulk-Driven OTA. 224-232 - Huan Yu, Tim Michalka, Mourad Larbi, Madhavan Swaminathan:
Behavioral Modeling of Tunable I/O Drivers With Preemphasis Including Power Supply Noise. 233-242 - Dashan Pan, Chao Ma, Lanqi Cheng, Hao Min:
A Highly Efficient Conditional Feedthrough Pulsed Flip-Flop for High-Speed Applications. 243-251 - Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi:
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. 252-262 - Samir Ben Dodo, Rajendra Bishnoi, Mehdi Baradaran Tahoori:
Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks. 263-272 - Roohollah Yarmand, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
DART: A Framework for Determining Approximation Levels in an Approximable Memory Hierarchy. 273-286 - Morteza Soltani, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
RandShift: An Energy-Efficient Fault-Tolerant Method in Secure Nonvolatile Main Memory. 287-291 - Chia-Hung Chang, Wei-Hsien Chen:
Vital-Sign Processing Receiver With Clutter Elimination Using Servo Feedback Loop for UWB Pulse Radar System. 292-296 - Shokat Ganjeheizadeh Rohani, Nima Taherinejad, David Radakovits:
A Semiparallel Full-Adder in IMPLY Logic. 297-301 - Dimitrios Konstantinou, Anastasios Psarras, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
The Mesochronous Dual-Clock FIFO Buffer. 302-306
Volume 28, Number 2, February 2020
- Jonathon Edstrom, Hritom Das, Yiwen Xu, Na Gong:
Memory Optimization for Energy-Efficient Differentially Private Deep Learning. 307-316 - Mohammad Saeed Ansari, Vojtech Mrazek, Bruce F. Cockburn, Lukás Sekanina, Zdenek Vasícek, Jie Han:
Improving the Accuracy and Hardware Efficiency of Neural Networks Using Approximate Multipliers. 317-328 - Krishna Praveen Yalamarthy, Saurabh Dhall, Mohd. Tasleem Khan, Rafi Ahamed Shaik:
Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network. 329-338 - Liting Yu, Xiaoxiao Wang, Fahim Rahman, Mark M. Tehranipoor:
Interconnect-Based PUF With Signature Uniqueness Enhancement. 339-352 - Ahmet Can Mert, Erdinç Öztürk, Erkay Savas:
Design and Implementation of Encryption/Decryption Architectures for BFV Homomorphic Encryption Scheme. 353-362 - Andrew Stern, Ulbert Botero, Fahim Rahman, Domenic Forte, Mark M. Tehranipoor:
EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification. 363-375 - Thorben Moos, Amir Moradi, Bastian Richter:
Static Power Side-Channel Analysis - An Investigation of Measurement Factors. 376-389 - Dong Wang, Pak Kwong Chan:
A Sub-1-V 100-mA OCL-LDO Regulator With Process-Temperature-Aware Design for Transient Sustainability. 390-402 - Kan Li, Xiao Xiao, Xiangliang Jin, Yuanjin Zheng:
A 600-mA, Fast-Transient Low-Dropout Regulator With Pseudo-ESR Technique in 0.18- m CMOS Process. 403-413 - Albert Ciprut, Eby G. Friedman:
Distributed Pass Gates in Power Delivery Systems With Digital Low-Dropout Regulators. 414-420 - Liang Chen, Sheldon X.-D. Tan, Zeyu Sun, Shaoyi Peng, Min Tang, Junfa Mao:
Fast Analytic Electromigration Analysis for General Multisegment Interconnect Wires. 421-432 - Iraj Moghaddasi, Mostafa E. Salehi, Mehdi Kargahi:
Aging-Aware Instruction-Level Statistical Dynamic Timing Analysis for Embedded Processors. 433-442 - Mohammad Saber Golanbari, Saman Kiamehr, Fabian Oboril, Anteneh Gebregiorgis, Mehdi Baradaran Tahoori:
Achieving Energy Efficiency for Near-Threshold Circuits Through Postfabrication Calibration and Adaptation. 443-455 - Sourav Sanyal, Prabal Basu, Aatreyi Bal, Sanghamitra Roy, Koushik Chakraborty:
Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. 456-466 - Guanghui He, Xiaoyu Zhang, Zhuojun Liang:
Algorithm and Architecture of an Efficient MIMO Detector With Cross-Level Parallel Tree-Search. 467-479 - Diwei Li, Dixian Zhao:
High-Throughput Low-Power Area-Efficient Outphasing Modulator Based on Unrolled and Pipelined Radix-2 CORDIC. 480-491 - Duo Sheng, Jun-Wei Lin, Yi-Hsiang Wang, Chih-Chung Huang:
High-Resolution All-Digital Transmit Beamformer for High-Frequency and Wearable Ultrasound Imaging Systems. 492-502 - James R. Hoff:
Conflux - An Asynchronous Two-to-One Multiplexor for Time-Division Multiplexing and Clockless, Tokenless Readout. 503-515 - He Li, James J. Davis, John Wickerson, George A. Constantinides:
architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute. 516-529 - Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini:
Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. 530-543 - Irith Pomeranz:
Extra Clocking of LFSR Seeds for Improved Path Delay Fault Coverage. 544-552 - Stavros Hadjitheophanous, Stelios N. Neophytou, Maria K. Michael:
Maintaining Scalability of Test Generation Using Multicore Shared Memory Systems. 553-564 - Rongdi Sun, Jiuchao Qian, José Romero Hung, Zheng Gong, Ruihang Miao, Wuyang Xue, Peilin Liu:
A Flexible and Efficient Real-Time ORB-Based Full-HD Image Feature Extraction Accelerator. 565-575 - Farah Fahim, Siddhartha Joshi, Seda Ogrenci-Memik, Hooman Mohseni:
A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree. 576-584 - Mehmet Meric Isgenc, Mayler G. A. Martins, V. Mohammed Zackriya, Samuel N. Pagliarini, Lawrence T. Pileggi:
Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. 585-595 - Li Tan, Zhongcai Li, Gang Su, Desheng Wang:
Asymptotically Linear Analysis and Gate Probability Allocation Schemes in Probabilistic Circuits. 596-606
Volume 28, Number 3, March 2020
- Zhiting Lin, Yong Wang, Chunyu Peng, Xiulong Wu, Xuan Li, Junning Chen:
Multiple Sharing 7T1R Nonvolatile SRAM With an Improved Read/Write Margin and Reliable Restore Yield. 607-619 - Rui Zhang, Taizhi Liu, Kexin Yang, Chang-Chih Chen, Linda Milor:
SRAM Stability Analysis and Performance-Reliability Tradeoff for Different Cache Configurations. 620-633 - Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi:
Fault-Aware Dependability Enhancement Techniques for Flash Memories. 634-645 - Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg:
Gain-Cell Embedded DRAMs: Modeling and Design Space. 646-659 - Bo-Cheng Lai, Bo-Ya Chen, Bo-En Chen, Yi-Da Hsin:
REMAP+: An Efficient Banking Architecture for Multiple Writes of Algorithmic Memory. 660-671 - Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran:
TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems. 672-685 - Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Partha Pratim Pande:
Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration. 686-699 - Nandini Vitee, Harikrishnan Ramiah, Pui-In Mak, Jun Yin, Rui Paulo Martins:
A 3.15-mW +16.0-dBm IIP3 22-dB CG Inductively Source Degenerated Balun-LNA Mixer With Integrated Transformer-Based Gate Inductor and IM2 Injection Technique. 700-713 - Pallavi Paliwal, Vivek Yadav, Zeeshan Ali, Shalabh Gupta:
A Fast Settling Fractional-N DPLL With Loop-Order Switching. 714-725 - Yusuke Kanno, Tadanobu Toba, Kotaro Shimamura, Nobuyasu Kanekawa:
Design Method for Online Totally Self-Checking Comparators Implementable on FPGAs. 726-735 - Jin-Tai Yan:
Single-Layer Delay-Driven GNR Nontree Routing Under Resource Constraint for Yield Improvement. 736-749 - Trevor E. Pogue, Nicola Nicolici:
Incremental Fault Analysis: Relaxing the Fault Model of Differential Fault Attacks. 750-763 - Omar Al-Terkawi Hasib, Yvon Savaria, Claude Thibeault:
Optimization of Small-Delay Defects Test Quality by Clock Speed Selection and Proper Masking Based on the Weighted Slack Percentage. 764-776 - Saurabh Jain, Longyang Lin, Massimo Alioto:
Automated Design of Reconfigurable Microarchitectures for Accelerators Under Wide-Voltage Scaling. 777-790 - Yu-Sheng Lin, Wei-Chao Chen, Shao-Yi Chien:
MERIT: Tensor Transform for Memory-Efficient Vision Processing on Parallel Architectures. 791-804 - Tae Hyun Kim, Hayoung Lee, Sungho Kang:
GPU-Based Redundancy Analysis Using Concurrent Evaluation. 805-817 - Jaeyoung Seo, Jaehyun Ko, Kyunghyun Lim, Sooeun Lee, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels. 818-822 - Mohammad Bavandpour, Shubham Sahay, Mohammad Reza Mahmoodi, Dmitri B. Strukov:
Efficient Mixed-Signal Neurocomputing Via Successive Integration and Rescaling. 823-827 - Mao Ye, Xiaoxiao Zheng, Yao Li, Yiqiang Zhao:
A Low-Complexity Hybrid Readout Circuit for Lidar Receiver. 828-832 - Meera Kumari, S. M. Rezaul Hasan:
A Low Duty Cycle Burst-Mode Telemeter Signal Generation Technique for VHF Insect Tracking and Its CMOS Implementation. 833-837 - Erfan Bank-Tavakoli, Seyed Abolfazl Ghasemzadeh, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
POLAR: A Pipelined/Overlapped FPGA-Based LSTM Accelerator. 838-842 - Shizhong Li, Kamal El-Sankary, Alireza Karami, Dmitri V. Truhachev:
Area- and Power-Efficient Staircase Encoder Implementation for High-Throughput Fiber-Optical Communications. 843-847 - Qiang Zhao, Chunyu Peng, Junning Chen, Zhiting Lin, Xiulong Wu:
Novel Write-Enhanced and Highly Reliable RHPD-12T SRAM Cells for Space Applications. 848-852
Volume 28, Number 4, April 2020
- Juan Yepez, Seok-Bum Ko:
Stride 2 1-D, 2-D, and 3-D Winograd for Convolutional Neural Networks. 853-863 - Yuxuan Wang, Yuanyong Luo, Zhongfeng Wang, Qinghong Shen, Hongbing Pan:
GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number. 864-875 - Avishek Sinha Roy, Rajdeep Biswas, Anindya Sundar Dhar:
On Fast and Exact Computation of Error Metrics in Approximate LSB Adders. 876-889 - Ibrahim Ahmed, Linda L. Shen, Vaughn Betz:
Optimizing FPGA Logic Circuitry for Variable Voltage Supplies. 890-903 - Poki Chen, Jian-Ting Lan, Ruei-Ting Wang, Nguyen My Qui, John Carl Joel S. Marquez, Seiji Kajihara, Yousuke Miyake:
High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters. 904-913 - Oscar Garnica, Juan Lanchares, José Ignacio Hidalgo:
Optimal Runtime Algorithm to Improve Fault Tolerance of Bus-Based Reconfigurable Designs. 914-925 - Henry Lopez Davila, Hsun-Wei Chan, Kang-Lun Chiu, Pei-Yun Tsai, Shyh-Jye Jou:
A 75-Gb/s/mm2 and Energy-Efficient LDPC Decoder Based on a Reduced Complexity Second Minimum Approximation Min-Sum Algorithm. 926-939 - Dong-Yuan Shi, Woon-Seng Gan, Jianjun He, Bhan Lam:
Practical Implementation of Multichannel Filtered-x Least Mean Square Algorithm Based on the Multiple-Parallel-Branch With Folding Architecture for Large-Scale Active Noise Control. 940-953 - Shervin Roshanisefat, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan:
SAT-Hard Cyclic Logic Obfuscation for Protecting the IP in the Manufacturing Supply Chain. 954-967 - Asmit De, Mohammad Nasim Imtiaz Khan, Karthikeyan Nagarajan, Swaroop Ghosh:
HarTBleed: Using Hardware Trojans for Data Leakage Exploits. 968-979 - Ashish Ranjan, Arnab Raha, Vijay Raghunathan, Anand Raghunathan:
Approximate Memory Compression. 980-991 - Sayed Ahmad Salehi:
Low-Cost Stochastic Number Generators for Stochastic Computing. 992-1001 - Binod Kumar, Jay Adhaduk, Kanad Basu, Masahiro Fujita, Virendra Singh:
A Methodology to Capture Fine-Grained Internal Visibility During Multisession Silicon Debug. 1002-1015 - Surajit Das, Chandan Karfa, Santosh Biswas:
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock. 1016-1029 - Dave Y.-W. Lin, Charles H.-P. Wen:
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction. 1030-1042 - Haoyu Zhuang, Xiaoxian Liu, Hao Wang:
Voltage Reference With Linear-Temperature-Dependent Power Consumption. 1043-1049 - Niranjan Raj, Rajeev Kumar Ranjan, Fabian Khateb:
Flux-Controlled Memristor Emulator and Its Experimental Results. 1050-1061 - Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, Puneet Gupta:
Design Space Exploration for Chiplet-Assembly-Based Processors. 1062-1073 - Jie Sun, Minglei Zhang, Lei Qiu, Jianhui Wu, Weiqiang Liu:
Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators. 1074-1078 - Juhyun Park, Tae Woo Oh, Seong-Ook Jung:
pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{\mathrm{SS}}$ for Near-Threshold Operation. 1079-1083 - Inayat Ullah, Joon-Sung Yang, Jaeyong Chung:
ER-TCAM: A Soft-Error-Resilient SRAM-Based Ternary Content-Addressable Memory for FPGAs. 1084-1088 - Yuanyuan Han, Xu Cheng, Jun Han, Xiaoyang Zeng:
Radiation-Hardened 0.3-0.9-V Voltage-Scalable 14T SRAM and Peripheral Circuit in 28-nm Technology for Space Applications. 1089-1093 - Chun-Chi Chen, Chorng-Sii Hwang, Kai-Hsiang Chang:
All-Digital Cost-Efficient CMOS Digital-to-Time Converter Using Binary-Weighted Pulse Expansion. 1094-1098
Volume 28, Number 5, May 2020
- Chan-Ho Kye, Han-Gon Ko, Jinhyung Lee, Deog-Kyoon Jeong:
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. 1099-1106 - Hyochang Kim, Changsik Yoo:
A 6-Gb/s Wireline Receiver With Intrapair Skew Compensation and Three-Tap Decision-Feedback Equalizer in 28-nm CMOS. 1107-1117 - Dimitris Theodoropoulos, Nektarios Kranitis, Antonis Tsigkanos, Antonis M. Paschalis:
Efficient Architectures for Multigigabit CCSDS LDPC Encoders. 1118-1127 - Zhongyuan Tian, Jiang Xu, Haoran Li, Rafael Kioji Vivas Maeda:
Multidevice Collaborative Power Management Through Decentralized Knowledge Sharing. 1128-1140 - Chung-Hsun Huang, Wei-Chen Liao:
A High-Performance LDO Regulator Enabling Low-Power SoC With Voltage Scaling Approaches. 1141-1149 - Haoran Li, Zhongyuan Tian, Jiang Xu, Rafael K. V. Maeda, Zhehui Wang, Zhifei Wang:
Chip-Specific Power Delivery and Consumption Co-Management for Process-Variation-Aware Manycore Systems Using Reinforcement Learning. 1150-1163 - Nandini Vitee, Harikrishnan Ramiah, Pui-In Mak, Jun Yin, Rui Paulo Martins:
A 1-V 4-mW Differential-Folded Mixer With Common-Gate Transconductor Using Multiple Feedback Achieving 18.4-dB Conversion Gain, +12.5-dBm IIP3, and 8.5-dB NF. 1164-1174 - Yang Azevedo Tavares, Kang-Yoon Lee, Minjae Lee:
All-Digital Bandwidth Mismatch Calibration of TI-ADCs Based on Optimally Induced Minimization. 1175-1184 - Alireza Mosalmani, Mehdi Khoee, Omid Shoaei:
A 9-Bit 70-MS/s Two-Stage SAR ADC With Passive Residue Transfer. 1185-1194 - Aili Wang, Chuanjin Richard Shi:
Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. 1195-1206 - Hassan Afzali-Kusha, Marzieh Vaeztourshizi, Mehdi Kamal, Massoud Pedram:
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling. 1207-1220 - Basant Kumar Mohanty, Pramod Kumar Meher:
An Efficient Parallel DA-Based Fixed-Width Design for Approximate Inner-Product Computation. 1221-1229 - Karri Manikantta Reddy, M. H. Vasantha, Nithin Y. B. Kumar, Devesh Dwivedi:
Design of Approximate Booth Squarer for Error-Tolerant Computing. 1230-1241 - Prashansa Mukim, Aditya Dalakoti, David McCarthy, Carrie Segal, Merritt Miller, James F. Buckwalter, Forrest Brewer:
Design and Analysis of Collective Pulse Oscillators. 1242-1255 - Taehyun Kwon, Muhammad Imran, David Z. Pan, Joon-Sung Yang:
Virtual-Tile-Based Flip-Flop Alignment Methodology for Clock Network Power Optimization. 1256-1268 - Tung-Che Liang, Krishnendu Chakrabarty, Ramesh Karri:
Programmable Daisychaining of Microelectrodes to Secure Bioassay IP in MEDA Biochips. 1269-1282 - Shantharam Kalipatnapu, Indrajit Chakrabarti:
Low-Complexity Interval Passing Algorithm and VLSI Architecture for Binary Compressed Sensing. 1283-1291 - Marco Silva Pereira, Mário Assunção, João Caldinhas Vaz:
Analysis and Design of Current Mode Class-D Power Amplifiers With Finite Feeding Inductors. 1292-1301 - Yiran Du, Wei Li, Zibin Dai, Longmei Nan:
PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping. 1302-1315 - Zhiting Lin, Honglan Zhan, Xuan Li, Chunyu Peng, Wenjuan Lu, Xiulong Wu, Junning Chen:
In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands. 1316-1320 - Dwaipayan Ray, Nithin V. George, Pramod Kumar Meher:
Analysis and Design of Unified Architectures for Zero-Attraction-Based Sparse Adaptive Filters. 1321-1325 - Boyang Chen, Kai Liu, Evgeny Belyaev:
An Efficient Hardware Implementation of Multialphabet Adaptive Arithmetic Encoder Based on Generalized Virtual Sliding Window. 1326-1330 - Maliang Liu, Jinhai Xiao, Peng Luo, Zhangming Zhu, Yintang Yang:
Ultrawideband Power-Switchable Transmitter With 17.7-dBm Output Power for See-Through-Wall Radar. 1331-1335 - Luis Alberto Aranda, Alfonso Sánchez-Macián, Juan Antonio Maestro:
An Algorithmic-Based Fault Detection Technique for the 1-D Discrete Cosine Transform. 1336-1340 - Randy W. Mann, Meixiong Zhao, Oh Sung Kwon, Xi Cao, Sanjay Parihar, Muhammed Ahosan Ul Karim, Jack M. Higman, Joseph Versaggi, Rick Carter:
Bias-Dependent Variation in FinFET SRAM. 1341-1344
Volume 28, Number 6, June 2020
- Lu Lu, Taegeun Yoo, Van Loi Le, Tony Tae-Hyoung Kim:
A 0.506-pJ 16-kb 8T SRAM With Vertical Read Wordlines and Selective Dual Split Power Lines. 1345-1356 - Muhammad Avais Qureshi, Jungwoo Park, Soontae Kim:
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches. 1357-1370 - Albert Lee, Raahul Jagannathan, Di Wu, Kang L. Wang:
A 2-D Calibration Scheme for Resistive Nonvolatile Memories. 1371-1377 - Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
Optimizing FPGA Logic Block Architectures for Arithmetic. 1378-1391 - Lenos Ioannou, Abdullah Al-Dujaili, Suhaib A. Fahmy:
High Throughput Spatial Convolution Filters on FPGAs. 1392-1402 - Amir Fathi, Behbood Mashoufi, Sarkis Azizian:
Very Fast, High-Performance 5-2 and 7-2 Compressors in CMOS Process for Rapid Parallel Accumulations. 1403-1412 - Jyoti Kandpal, Abhishek Tomar, Mayur Agarwal, Kamal Kumar Sharma:
High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR-XNOR Cell. 1413-1422 - Jianwei Yang, Jun Han, Fan Dai, Weizhen Wang, Xiaoyang Zeng:
A Power Analysis Attack Resistant Multicore Platform With Effective Randomization Techniques. 1423-1434 - Samaneh Ghandali, Thorben Moos, Amir Moradi, Christof Paar:
Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations. 1435-1448 - Qiang Zhao, Yiheng Wu, Xiaojin Zhao, Yuan Cao, Chip-Hong Chang:
A 1036-F2/Bit High Reliability Temperature Compensated Cross-Coupled Comparator-Based PUF. 1449-1460 - Mohammad Nasim Imtiaz Khan, Asmit De, Swaroop Ghosh:
Cache-Out: Leaking Cache Memory Using Hardware Trojan. 1461-1470 - Jungmin Park, Seongjoon Cho, Taejin Lim, Mark M. Tehranipoor:
QEC: A Quantum Entropy Chip and Its Applications. 1471-1484 - Ahmet Turan Erozan, Guan Ying Wang, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology. 1485-1495 - Ahmet Turan Erozan, Dennis D. Weller, Farhan Rasheed, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori:
A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit. 1496-1504 - Abdelrahman G. Qoutb, Eby G. Friedman:
Distributed Spintronic/CMOS Sensor Network for Thermal-Aware Systems. 1505-1512 - Sanmitra Banerjee, Arjun Chaudhuri, Krishnendu Chakrabarty:
Analysis of the Impact of Process Variations and Manufacturing Defects on the Performance of Carbon-Nanotube FETs. 1513-1526 - Alessandro de Gennaro, Danil Sokolov, Andrey Mokhov:
Design and Implementation of Reconfigurable Asynchronous Pipelines. 1527-1539 - Qinyu Chen, Yan Huang, Rui Sun, Wenqing Song, Zhonghai Lu, Yuxiang Fu, Li Li:
An Efficient Accelerator for Multiple Convolutions From the Sparsity Perspective. 1540-1544
Volume 28, Number 7, July 2020
- Yunxuan Yu, Tiandong Zhao, Mingyu Wang, Kun Wang, Lei He:
Uni-OPU: An FPGA-Based Uniform Accelerator for Convolutional and Transposed Convolutional Networks. 1545-1556 - Pramesh Pandey, Prabal Basu, Koushik Chakraborty, Sanghamitra Roy:
GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit. 1557-1566 - Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan:
TiM-DNN: Ternary In-Memory Accelerator for Deep Neural Networks. 1567-1577 - Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram:
Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications. 1578-1588 - Xiaoyan Gui, Bingjun Tang, Renjie Tang, Dan Li, Li Geng:
Low-Supply Sensitivity LC VCOs With Complementary Varactors. 1589-1599 - Yupeng Fu, Lianming Li, Yilong Liao, Xuan Wang, Yongjian Shi, Dongming Wang:
A 32-GHz Nested-PLL-Based FMCW Modulator With 2.16-GHz Bandwidth in a 65-nm CMOS Process. 1600-1609 - George Floros, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
Frequency-Limited Reduction of Regular and Singular Circuit Models Via Extended Krylov Subspace Method. 1610-1620 - Samuel Annor Fordjour, Joseph Riad, Edgar Sánchez-Sinencio:
A 175.2-mW 4-Stage OTA With Wide Load Range (400 pF-12 nF) Using Active Parallel Compensation. 1621-1629 - Huan Yu, Madhavan Swaminathan:
A Bit-Time-Dependent Model of I/O Drivers for Overclocking Analysis. 1630-1637 - Ramanuj Chouksey, Chandan Karfa:
Verification of Scheduling of Conditional Behaviors in High-Level Synthesis. 1638-1651 - Chenchen Xie, Xi Li, Yu Lei, Houpeng Chen, Qian Wang, Jiashu Guo, Jie Miao, Yi Lv, Zhitang Song:
BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm. 1652-1664 - Mallika Rathore, Peter A. Milder, Emre Salman:
Error Probability Models for Voltage-Scaled Multiply-Accumulate Units. 1665-1675 - Jian Wang, Songting Li, Xianbin Li:
Scheduling of Data Access for the Radix-2k FFT Processor Using Single-Port Memory. 1676-1689 - Wei Song, Yifei Shen, Liping Li, Kai Niu, Chuan Zhang:
A General Construction and Encoder Implementation of Polar Codes. 1690-1702 - Chao Ji, Yifei Shen, Zaichen Zhang, Xiaohu You, Chuan Zhang:
Autogeneration of Pipelined Belief Propagation Polar Decoders. 1703-1716 - Sung-Joon Jang, Chong-Min Kyung:
Resource-Efficient and High-Throughput VLSI Design of Global Optical Flow Method for Mobile Systems. 1717-1725 - Kuan-Lin Fu, Shen-Iuan Liu:
A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration. 1726-1735 - Tianming Ni, Dongsheng Liu, Qi Xu, Zhengfeng Huang, Huaguo Liang, Aibin Yan:
Architecture of Cobweb-Based Redundant TSV for Clustered Faults. 1736-1739 - Srisubha Kalanadhabhatta, Deepak Kumar, Kiran Kumar Anumandla, S. Ashish Reddy, Amit Acharyya:
PUF-Based Secure Chaotic Random Number Generator Design Methodology. 1740-1744
Volume 28, Number 8, August 2020
- Sudipa Mandal, Pallab Dasgupta, Aritra Hazra, Chunduri Rama Mohan:
Assertions for Protecting Mixed-Signal Latency Contracts in Power Management. 1745-1756 - Fernando Lavalle-Aviles, Edgar Sánchez-Sinencio:
A 0.6-V Power-Efficient Active-RC Analog Low-Pass Filter With Cutoff Frequency Selection. 1757-1769 - Hyungyu Ju, Minjae Lee:
A Hybrid Miller-Cascode Compensation for Fast Settling in Two-Stage Operational Amplifiers. 1770-1781 - Mahdi Yektaei, M. B. Ghaznavi-Ghoushchi:
PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications. 1782-1795 - Yan Wang, Jinhui Liu, Jingtong Hu:
Communication-Aware Task Scheduling for Energy-Harvesting Nonvolatile Processors. 1796-1806 - Siva Nishok Dhanuskodi, Samuel Allen, Daniel E. Holcomb:
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET. 1807-1820 - Zhiheng Wang, Devan Larso, Morgen Barker, Soheil Mohajer, Kia Bazargan:
Deterministic Shuffling Networks to Implement Stochastic Circuits in Parallel. 1821-1832 - Ahish Shylendra, Priyesh Shukla, Saibal Mukhopadhyay, Swarup Bhunia, Amit Ranjan Trivedi:
Low Power Unsupervised Anomaly Detection by Nonparametric Modeling of Sensor Statistics. 1833-1843 - Susmita Dey Manasi, Farhana Sharmin Snigdha, Sachin S. Sapatnekar:
NeuPart: Using Analytical Models to Drive Energy-Efficient Partitioning of CNN Computations on Cloud-Connected Mobile Clients. 1844-1857 - Vahid Jamshidi:
A VLSI Majority-Logic Device Based on Spin Transfer Torque Mechanism for Brain-Inspired Computing Architecture. 1858-1866 - Wendong Mao, Jun Lin, Zhongfeng Wang:
F-DNA: Fast Convolution Architecture for Deconvolutional Network Acceleration. 1867-1880 - Yi-Hao Cheng, Tao-Chun Yu, Shao-Yun Fang:
Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources. 1881-1892 - Sungmin Jang, Jaeyoung Park:
HYFII: HYbrid Fault Injection Infrastructure for Accurate Runtime System Failure Analysis. 1893-1900 - Aleksandar Radonjic:
Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte. 1901-1908 - Van Loi Le, Taegeun Yoo, Ju Eon Kim, Ngoc Le Ba, Kwang-Hyun Baek, Tony Tae-Hyoung Kim:
A 137-μW 1.78-mm2 30-Frames/s Real-Time Gesture Recognition SoC for Smart Devices. 1909-1919 - Laxmeesha Somappa, Maryam Shojaei Baghini:
A 300-mV Auto Shutdown Comparator-Based Continuous Time Δ∑ Modulator. 1920-1924 - Muhammad Irfan, Zahid Ullah, Mehdi Hasan Chowdhury, Ray C. C. Cheung:
RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs. 1925-1929 - Irith Pomeranz:
RETRO: Reintroducing Tests for Improved Reverse Order Fault Simulation. 1930-1934 - Liang Wen, Yuejun Zhang, Pengjun Wang:
Radiation-Hardened, Read-Disturbance-Free New-Quatro-10T Memory Cell for Aerospace Applications. 1935-1939 - Irith Pomeranz:
Broad-Brush Compaction for Sequential Test Generation. 1940-1944
Volume 28, Number 9, September 2020
- Anni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu:
Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area Constraint. 1945-1952 - Chaoyang Zhu, Kejie Huang, Shuyuan Yang, Ziqi Zhu, Hejia Zhang, Haibin Shen:
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs. 1953-1965 - Shanlin Xiao, Yuhao Guo, Wenkang Liao, Huipeng Deng, Yi Luo, Huanliang Zheng, Jian Wang, Cheng Li, Gezi Li, Zhiyi Yu:
NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators. 1966-1978 - Anirban Sengupta, Mahendra Rathor:
Securing Hardware Accelerators for CE Systems Using Biometric Fingerprinting. 1979-1992 - Adrián Alcolea Morena, Javier Olivito, Javier Resano, Hortensia Mecha:
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems. 1993-2003 - Peilin Yang, Xiao Wang, Chengwei Wang, Fule Li, Hanjun Jiang, Zhihua Wang:
A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. 2004-2013 - Hongxi Dong, Manzhen Wang, Yuanyong Luo, Muhan Zheng, Mengyu An, Yajun Ha, Hongbing Pan:
PLAC: Piecewise Linear Approximation Computation for All Nonlinear Unary Functions. 2014-2027 - Anuradha Chathuranga Ranasinghe, Sabih H. Gerez:
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers. 2028-2041 - Qian Ding, Graham Knight, Terrence S. T. Mak:
An Active Silicon Interposer With Low-Power Hybrid Wireless-Wired Clock Distribution Network for Many-Core Systems. 2042-2054 - Anthony Agnesina, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim:
A COTS-Based Novel 3-D DRAM Memory Cube Architecture for Space Applications. 2055-2068 - Chua-Chin Wang, Kuan-Yu Chao, Sivaperumal Sampath, Ponnan Suresh:
Anti-PVT-Variation Low-Power Time-to-Digital Converter Design Using 90-nm CMOS Process. 2069-2073 - Libin K. Mathew, Shanker Shreejith, A. Prasad Vinod, A. S. Madhukumar:
A Power-Efficient Spectrum-Sensing Scheme Using 1-Bit Quantizer and Modified Filter Banks. 2074-2078 - Chun-Chi Chen, Chao-Lieh Chen, Wei Fang, Yen-Chan Chu:
All-Digital CMOS Time-to-Digital Converter With Temperature-Measuring Capability. 2079-2083 - Linus Witschen, Tobias Wiersema, Marco Platzner:
Proof-Carrying Approximate Circuits. 2084-2088
Volume 28, Number 10, October 2020
- Wei Deng, Rui Wu, Zhijie Chen, Manlai Ding, Haikun Jia, Baoyong Chi:
A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology. 2089-2098 - Quan Pan, Li Wang, Xiongshi Luo, C. Patrick Yue:
A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder. 2099-2108 - Immanuel Raja, Gaurab Banerjee:
A 0.75-2.5-GHz All-Digital RF Transmitter With Integrated Class-E Power Amplifier for Spectrum Sharing Applications in 5G Radios. 2109-2121 - Loris Duch, Miguel Peón Quirós, Pieter Weckx, Alexandre Levisse, Rubén Braojos, Francky Catthoor, David Atienza:
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors. 2122-2133 - Guanghui He, Sijie Zheng, Naifeng Jing:
A Hierarchical Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. 2134-2145 - Abdullah Guler, Niraj K. Jha:
McPAT-Monolithic: An Area/Power/Timing Architecture Modeling Framework for 3-D Hybrid Monolithic Multicore Systems. 2146-2156 - Nithyashankari Gummidipoondi Jayasankaran, Adriana C. Sanabria-Borbon, Amr Abuellil, Edgar Sánchez-Sinencio, Jiang Hu, Jeyavijayan Rajendran:
Breaking Analog Locking Techniques. 2157-2170 - Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter. 2171-2181 - Milad Bahadori, Kimmo Järvinen:
A Programmable SoC-Based Accelerator for Privacy-Enhancing Technologies and Functional Encryption. 2182-2195 - Wei Yan, Ning Zhang, Laurent L. Njilla, Xuan Zhang:
PCBChain: Lightweight Reconfigurable Blockchain Primitives for Secure IoT Applications. 2196-2209 - Somayeh Rahimipour, Wameedh Nazar Flayyih, Noor Ain Kamsani, Shaiful Jahari Hashim, Mircea R. Stan, Fakhrul Zaman Rokhani:
Low-Power, Highly Reliable Dynamic Thermal Management by Exploiting Approximate Computing. 2210-2222 - Even Låte, Trond Ytterdal, Snorre Aunet:
Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. 2223-2227 - Bo Zhou, Yeran Jin, Fuyuan Zhao:
Sub-1-V BGR and POR Hybrid Circuit With 2.25-μA Current Dissipation and Low Complexity. 2228-2232
Volume 28, Number 11, November 2020
- Poki Chen, Yung-Hsuan Chen, John Carl Joel S. Marquez, Ruei-Ting Wang, Jiann-Jong Chen, Yuh-Shyan Hwang:
Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching. 2233-2242 - Zhiqun Li, Guoxiao Cheng, Tingting Han, Zhennan Li, Mi Tian:
A 23-36.8-GHz Low-Noise Frequency Synthesizer With a Fundamental Colpitts VCO Array in SiGe BiCMOS for 5G Applications. 2243-2256 - Kyungho Ryu, Kil-Hoon Lee, Jung-Pil Lim, Jinho Kim, Han Su Pae, Junho Park, Hyun-Wook Lim, Jae-Youl Lee:
An Analytical Jitter Tolerance Model for DLL-Based Clock and Data Recovery Circuits. 2257-2267 - Ashish Joshi, Hitesh Shrimali, Satinder K. Sharma:
A Discrete-Time MOS Parametric Amplifier-Based Chopped Signal Demodulator. 2268-2279 - Mohammadhadi Danesh, Aishwarya Bahudhanam Venkatasubramaniyan, Gaurav Kapoor, Naveen Ramesh, Sudarsan Sadasivuni, Sanjeev Tannirkulam Chandrasekaran, Arindam Sanyal:
Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO. 2280-2289 - Gang Li, Pengjun Wang, Xuejiao Ma, Jiana Lian, Junpeng Shu, Yuejun Zhang:
A 215-F² Bistable Physically Unclonable Function With an ACF of <0.005 and a Native Bit Instability of 2.05% in 65-nm CMOS Process. 2290-2299 - Dayane Reis, Jonathan Takeshita, Taeho Jung, Michael T. Niemier, Xiaobo Sharon Hu:
Computing-in-Memory for Performance and Energy-Efficient Homomorphic Encryption. 2300-2313 - Xiang Wang, Zongmin Zhao, Dongdong Xu, Zhun Zhang, Qiang Hao, Mengchen Liu:
An M-Cache-Based Security Monitoring and Fault Recovery Architecture for Embedded Processor. 2314-2327 - Xin Li, Zhi Li, Wei Zhou, Zhemin Duan:
Accurate On-Chip Temperature Sensing for Multicore Processors Using Embedded Thermal Sensors. 2328-2341 - Hameedah Sultan, Smruti R. Sarangi:
A Fast Leakage-Aware Green's-Function-Based Thermal Simulator for 3-D Chips. 2342-2355 - Jin-Tai Yan:
Delay-Constrained GNR Routing for Layer Minimization. 2356-2369 - Khaled Alhaj Ali, Mostafa Rizk, Amer Baghdadi, Jean-Philippe Diguet, Jalal Jomaah, Naoya Onizawa, Takahiro Hanyu:
Memristive Computational Memory Using Memristor Overwrite Logic (MOL). 2370-2382 - Takuya Kojima, Nguyen Anh Vu Doan, Hideharu Amano:
GenMap: A Genetic Algorithmic Approach for Optimizing Spatial Mapping of Coarse-Grained Reconfigurable Architectures. 2383-2396 - Antonis Tsigkanos, Nektarios Kranitis, Dimitris Theodoropoulos, Antonis M. Paschalis:
High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression With CCSDS-123.0-B-1. 2397-2409 - Tony Bailey, Andrew Ford, Siddharth Barve, Jacob Wells, Rashmi Jha:
Development of a Short-Term to Long-Term Supervised Spiking Neural Network Processor. 2410-2423 - Jinwoo Kim, Gauthaman Murali, Heechun Park, Eric Qin, Hyoukjun Kwon, Venkata Chaitanya Krishna Chekuri, Nael Mizanur Rahman, Nihar Dasari, Arvind Singh, Minah Lee, Hakki Mert Torun, Kallol Roy, Madhavan Swaminathan, Saibal Mukhopadhyay, Tushar Krishna, Sung Kyu Lim:
Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse. 2424-2437 - Gleb Krylov, Eby G. Friedman:
Design Methodology for Distributed Large-Scale ERSFQ Bias Networks. 2438-2447 - Ahmet Turan Erozan, Dennis D. Weller, Yijing Feng, Gabriel Cadilha Marques, Jasmin Aghassi-Hagmann, Mehdi B. Tahoori:
A Printed Camouflaged Cell Against Reverse Engineering of Printed Electronics Circuits. 2448-2458 - Yin Li, Yu Zhang, Wei He:
Fast Hybrid Karatsuba Multiplier for Type II Pentanomials. 2459-2463 - Hangxuan Cui, Jun Lin, Zhongfeng Wang:
Information Storage Bit-Flipping Decoder for LDPC Codes. 2464-2468 - Chao Liu, Jianguo Yang, Pengfei Jiang, Qiao Wang, Donglin Zhang, Tiancheng Gong, Qingting Ding, Yuling Zhao, Qing Luo, Xiaoyong Xue, Hangbing Lv, Ming Liu:
A Low Power 4T2C nvSRAM With Dynamic Current Compensation Operation Scheme. 2469-2473 - Ming-Han Chou, Shen-Iuan Liu:
A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL. 2474-2478
Volume 28, Number 12, December 2020
- Massimo Alioto:
Editorial on the Conclusion of the 2020 Editorial Year - The Climactic Finale of a Peculiar Year. 2479-2480 - Amogh Agrawal, Indranil Chakraborty, Deboleena Roy, Utkarsh Saxena, Saima Sharmin, Minsuk Koo, Yong Shim, Gopalakrishnan Srinivasan, Chamika M. Liyanagedera, Abhronil Sengupta, Kaushik Roy:
Revisiting Stochastic Computing in the Era of Nanoscale Nonvolatile Technologies. 2481-2494 - Xin Fan, Shutao Zhang, Tobias Gemmeke:
Approximation of Transcendental Functions With Guaranteed Algorithmic QoS by Multilayer Pareto Optimization. 2495-2508 - Ali A. D. Farahani, Hakem Beitollahi, Mahmood Fathi:
A Dynamic General Accelerator for Integer and Fixed-Point Processing. 2509-2517 - Bapi Kar, Pradeep Kumar Gopalakrishnan, Sumon Kumar Bose, Mohendra Roy, Arindam Basu:
ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing. 2518-2529 - Ali Newaz Bahar, Khan A. Wahid:
Design and Implementation of Approximate DCT Architecture in Quantum-Dot Cellular Automata. 2530-2539 - Yusheng Xie, Alex Noel Joseph Raj, Zhendong Hu, Shaohaohan Huang, Zhun Fan, Miroslav Joler:
A Twofold Lookup Table Architecture for Efficient Approximation of Activation Functions. 2540-2550 - Eleni Maragkoudaki, Vasilis F. Pavlidis:
Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication. 2551-2562 - Zhen Gao, Lingling Zhang, Tong Yan, Kangkang Guo, Zhan Xu, Pedro Reviriego:
Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs. 2563-2572 - Grzegorz Pastuszak:
Multisymbol Architecture of the Entropy Coder for H.265/HEVC Video Encoders. 2573-2583 - Piyali Datta, Arpan Chakraborty, Rajat Kumar Pal:
A Predictive Model for Fluid-Control Codesign of Paper-Based Digital Biochips Following a Machine Learning Approach. 2584-2597 - Ardhendu Sarkar, Som Banerjee, Surajeet Ghosh:
An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment. 2598-2611 - Hao-Yu Cheng, Chen-Wei Chen, Chung-An Shen, Yuan-Hao Huang:
The Configurable Hybrid Precoding Processor for Bit-Stream-Based mmWave MIMO Systems. 2612-2622 - Tso-Wei Li, Jong Seok Park, Hua Wang:
A 2-24-GHz 360° Full-Span Differential Vector Modulator Phase Rotator With Transformer-Based Poly-Phase Quadrature Network. 2623-2635 - Yuzong Chen, Lu Lu, Bongjin Kim, Tony Tae-Hyoung Kim:
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory. 2636-2649 - Hyun Kook Park, Hong Keun Ahn, Seong-Ook Jung:
A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM. 2650-2657 - Yi-Da Wu, Kexin Yang, Shu-Han Hsu, Linda Milor:
Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation. 2658-2671 - Jun-Hoe Phoon, Wai-Kong Lee, Denis Chee-Keong Wong, Wun-She Yap, Bok-Min Goi:
Area-Time-Efficient Code-Based Postquantum Key Encapsulation Mechanism on FPGA. 2672-2684 - George Provelengios, Daniel E. Holcomb, Russell Tessier:
Power Distribution Attacks in Multitenant FPGAs. 2685-2698 - Haoyu Zhuang, Can Tong, Xizhu Peng, He Tang:
Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs. 2699-2707 - Hye-Yoon Joo, Jinhyung Lee, Haram Ju, Han-Gon Ko, Jungmin Yoon, Byungjun Kang, Deog-Kyoon Jeong:
A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. 2708-2720 - John Charles Wright, Colin Schmidt, Ben Keller, Daniel Palmer Dabbelt, Jaehwa Kwak, Vighnesh Iyer, Nandish Mehta, Pi-Feng Chiu, Stevo Bailey, Krste Asanovic, Borivoje Nikolic:
A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. 2721-2725 - Ali Zahir, Shadan Khan Khattak, Anees Ullah, Pedro Reviriego, Fahad Bin Muslim, Waleed Ahmad:
FracTCAM: Fracturable LUTRAM-Based TCAM Emulation on Xilinx FPGAs. 2726-2730
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-22 20:57 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
