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2020 – today
- 2025
[j55]Zhuomin Chai
, Wei Liu, Yibo Lin, Runsheng Wang:
Fast and Accurate Cross-PVT Full-Chip Leakage Power Estimation With Multi-Task Learning. IEEE Access 13: 79646-79654 (2025)- [j54]Weiqiang Yao, Yibo Lin, Lin Li:
Learning placement order for constructive floorplanning. Integr. 100: 102293 (2025) - [j53]Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu:
Analytical Heterogeneous Die-to-Die 3-D Placement With Macros. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(2): 402-415 (2025) - [j52]Xun Jiang, Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin:
A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(3): 1003-1016 (2025) - [j51]Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Sign-Off Timing Considerations via Concurrent Routing Topology Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(5): 1942-1953 (2025) - [j50]Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang:
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(6): 2253-2263 (2025) - [c117]Kairong Guo, Xiaohan Gao, Haoyi Zhang, Runsheng Wang, Ru Huang, Yibo Lin:
Exploring Better Intra-Cell Routability for Layout Synthesis of Multi-Row Standard Cells. ASP-DAC 2025: 392 - [c116]Boyang Zhang, Che Chang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yang Sui, Chih-Chun Chang, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang:
iTAP: An Incremental Task Graph Partitioner for Task-parallel Static Timing Analysis. ASP-DAC 2025: 407-415 - [c115]Che Chang, Boyang Zhang, Cheng-Hsiang Chiu, Dian-Lun Lin, Yi-Hua Chung, Wan-Luan Lee, Zizheng Guo, Yibo Lin, Tsung-Wei Huang:
PathGen: An Efficient Parallel Critical Path Generation Algorithm. ASP-DAC 2025: 416-424 - [c114]Haikang Diao, Haoyi Zhang, Jiahao Song, Haoyang Luo, Yibo Lin, Runsheng Wang, Yuan Wang, Xiyuan Tang:
SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. DATE 2025: 1-7 - [c113]Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-Sided Signals. DATE 2025: 1-7 - [c112]Xizhe Shi, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
Handling Latch Loops in Timing Analysis with Improved Complexity and Divergent Loop Detection. DATE 2025: 1-7 - [c111]Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang:
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC. DATE 2025: 1-7 - [c110]Jing Mai, Chunyuan Zhao, Zuodong Zhang, Zhixiong Di, Yibo Lin, Runsheng Wang, Ru Huang:
LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method. ISPD 2025: 22-30 - [i30]Haoran Lu, Xun Jiang, Yanbang Chu, Ziqiao Xu, Rui Guo, Wanyue Peng, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals. CoRR abs/2501.15275 (2025) - [i29]Xun Jiang, Haoran Lu, Yuxuan Zhao, Jiarui Wang, Zizheng Guo, Heng Wu, Bei Yu, Sung Kyu Lim, Runsheng Wang, Ru Huang, Yibo Lin:
A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis. CoRR abs/2503.12512 (2025) - [i28]Chenhao Xue, Yi Ren, Jinwei Zhou, Kezhi Li, Chen Zhang, Yibo Lin, Lining Zhang, Qiang Xu, Guangyu Sun:
DOMAC: Differentiable Optimization for High-Speed Multipliers and Multiply-Accumulators. CoRR abs/2503.23943 (2025) - [i27]Yi Ren, Chenhao Xue, Jiaxing Zhang, Chen Zhang, Qiang Xu, Yibo Lin, Lining Zhang, Guangyu Sun:
DiffuSE: Cross-Layer Design Space Exploration of DNN Accelerator via Diffusion-Driven Optimization. CoRR abs/2503.23945 (2025) - [i26]Xufeng Yao, Jiaxi Jiang, Yuxuan Zhao, Peiyu Liao, Yibo Lin, Bei Yu:
Evolution of Optimization Algorithms for Global Placement via Large Language Models. CoRR abs/2504.17801 (2025) - 2024
- [j49]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. 67(4) (2024) - [j48]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
Large circuit models: opportunities and challenges. Sci. China Inf. Sci. 67(10) (2024) - [j47]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
Erratum to: Large circuit models: opportunities and challenges. Sci. China Inf. Sci. 67(11) (2024) - [j46]Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin:
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 641-653 (2024) - [j45]Yufei Chen, Zizheng Guo, Runsheng Wang, Ru Huang, Yibo Lin, Cheng Zhuo:
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1511-1524 (2024) - [j44]Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu:
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1624-1637 (2024) - [j43]Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin:
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1259-1272 (2024) - [j42]Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin:
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2034-2038 (2024) - [c109]Jiarui Wang, Xun Jiang, Yibo Lin:
Top-Level Routing for Multiply-Instantiated Blocks with Topology Hashing. DAC 2024: 17:1-17:6 - [c108]Chenhao Xue, Chen Zhang, Xun Jiang, Zhutianya Gao, Yibo Lin, Guangyu Sun:
Oltron: Algorithm-Hardware Co-design for Outlier-Aware Quantization of LLMs with Inter-/Intra-Layer Adaptation. DAC 2024: 31:1-31:6 - [c107]Yufan Du, Zizheng Guo, Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
PowPrediCT: Cross-Stage Power Prediction with Circuit-Transformation-Aware Learning. DAC 2024: 36:1-36:6 - [c106]Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang:
PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC 2024: 47:1-47:6 - [c105]Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. DAC 2024: 75:1-75:6 - [c104]Wan-Luan Lee, Dian-Lun Lin, Tsung-Wei Huang, Shui Jiang, Tsung-Yi Ho, Yibo Lin, Bei Yu:
G-kway: Multilevel GPU-Accelerated k-way Graph Partitioner. DAC 2024: 105:1-105:6 - [c103]Yuan Pu, Fangzhou Liu, Yu Zhang, Zhuolun He, Yibo Lin, Kai-Yuan Chao, Bei Yu:
Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. DAC 2024: 116:1-116:6 - [c102]Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang:
Heterogeneous Static Timing Analysis with Advanced Delay Calculator. DATE 2024: 1-6 - [c101]Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. DATE 2024: 1-6 - [c100]Zixi Liu, Yibo Lin, Xiaojing Su, Xiaohuan Ling, Xin Hong, Bojie Ma, Yajuan Su, Yayi Wei:
Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage. ACM Great Lakes Symposium on VLSI 2024: 592-598 - [c99]Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
An Efficient Task-Parallel Pipeline Programming Framework. HPC Asia 2024: 95-106 - [c98]Yufan Du, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
Fusion of Global Placement and Gate Sizing with Differentiable Optimization. ICCAD 2024: 19:1-19:9 - [c97]Qipan Wang, Xueqing Li, Tianyu Jia, Yibo Lin, Runsheng Wang, Ru Huang:
ATPlace2.5D: Analytical Thermal-Aware Chiplet Placement Framework for Large-Scale 2.5D-IC. ICCAD 2024: 39:1-39:9 - [c96]Jing Mai, Zuodong Zhang, Yibo Lin, Runsheng Wang, Ru Huang:
MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management. ICCAD 2024: 49:1-49:9 - [c95]Zizheng Guo, Zuodong Zhang, Wuxi Li, Tsung-Wei Huang, Xizhe Shi, Yufan Du, Yibo Lin, Runsheng Wang, Ru Huang:
HeteroExcept: A CPU-GPU Heterogeneous Algorithm to Accelerate Exception-aware Static Timing Analysis. ICCAD 2024: 65:1-65:9 - [c94]Xiaohan Gao, Haoyi Zhang, Bingyang Liu, Yibo Lin, Runsheng Wang, Ru Huang:
Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits. ICCAD 2024: 139:1-139:9 - [c93]Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang:
FaStTherm: Fast and Stable Full-Chip Transient Thermal Predictor Considering Nonlinear Effects. ICCAD 2024: 144:1-144:9 - [c92]Chunyuan Zhao, Zizheng Guo, Rui Wang, Zaiwen Wen, Yun Liang, Yibo Lin:
HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method. ICCAD 2024: 147:1-147:9 - [c91]Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. ICLR 2024 - [c90]Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. ISPD 2024: 75-82 - [c89]Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu:
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD 2024: 161-168 - [c88]Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu:
IncreMacro: Incremental Macro Placement Refinement. ISPD 2024: 169-176 - [c87]Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang:
Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis. MICRO 2024: 765-779 - [c86]Yangfan Jiang, Jianfei Song, Xunzhao Yin, Xiao Dong, Songyu Sun, Yibo Lin, Zhou Jin, Xiaoyu Yang, Cheng Zhuo:
A Parallel Simulation Framework Incorporating Machine Learning-Based Hotspot Detection for Accelerated Power Grid Analysis. MLCAD 2024: 9:1-9:7 - [c85]Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. VLSI Technology and Circuits 2024: 1-2 - [e1]Hussam Amrouch, Jiang Hu, Siddharth Garg, Yibo Lin:
Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, MLCAD 2024, Salt Lake City, UT, USA, September 9-11, 2024. ACM 2024, ISBN 979-8-4007-0699-8 [contents] - [i25]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i24]Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu:
Analytical Heterogeneous Die-to-Die 3D Placement with Macros. CoRR abs/2403.09070 (2024) - [i23]Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang:
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. CoRR abs/2403.18569 (2024) - [i22]Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. CoRR abs/2404.13062 (2024) - [i21]Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. CoRR abs/2406.18873 (2024) - [i20]Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Ru Huang:
MORE-Stress: Model Order Reduction based Efficient Numerical Algorithm for Thermal Stress Simulation of TSV Arrays in 2.5D/3D IC. CoRR abs/2411.12690 (2024) - [i19]Haoyi Zhang, Shizhao Sun, Yibo Lin, Runsheng Wang, Jiang Bian:
AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models. CoRR abs/2412.19824 (2024) - 2023
- [j41]Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang:
Interactive Analog Layout Editing With Instant Placement and Routing Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 698-711 (2023) - [j40]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2317-2330 (2023) - [j39]Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, Bei Yu:
DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3374-3387 (2023) - [j38]Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li, Runsheng Wang, Ru Huang:
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4139-4151 (2023) - [j37]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin D. F. Wong:
A GPU-Accelerated Framework for Path-Based Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4219-4232 (2023) - [j36]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4973-4984 (2023) - [j35]Zhuomin Chai, Yuxiang Zhao, Wei Liu, Yibo Lin, Runsheng Wang, Ru Huang:
CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5034-5047 (2023) - [j34]Xinfa Zhang, Zuodong Zhang, Yibo Lin, Zhigang Ji, Runsheng Wang, Ru Huang:
Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 721-725 (2023) - [j33]Yibo Lin, Avi Ziv, Haoxing Ren:
Introduction to the Special Issue on Machine Learning for CAD/EDA. ACM Trans. Design Autom. Electr. Syst. 28(2): 14:1-14:2 (2023) - [j32]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. ACM Trans. Design Autom. Electr. Syst. 28(5): 80:1-80:18 (2023) - [c84]Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. ASICON 2023: 1-4 - [c83]Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin:
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy. ASP-DAC 2023: 258-263 - [c82]Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin:
A Robust FPGA Router with Concurrent Intra-CLB Rerouting. ASP-DAC 2023: 529-534 - [c81]Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang:
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. DAC 2023: 1-6 - [c80]Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
On a Moreau Envelope Wirelength Model for Analytical Global Placement. DAC 2023: 1-6 - [c79]Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. DAC 2023: 1-6 - [c78]Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, Ru Huang:
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line. DAC 2023: 1-6 - [c77]Yu Zhang, Yifan Chen, Zhonglin Xie, Hong Xu, Zaiwen Wen, Yibo Lin, Bei Yu:
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition. DAC 2023: 1-6 - [c76]Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Mitigating Distribution Shift for Congestion Optimization in Global Placement. DAC 2023: 1-6 - [c75]Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang:
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. DATE 2023: 1-6 - [c74]Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. DATE 2023: 1-2 - [c73]Yifan Chen, Zaiwen Wen, Yun Liang, Yibo Lin:
Stronger Mixed-Size Placement Backbone Considering Second-Order Information. ICCAD 2023: 1-9 - [c72]Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. ICCAD 2023: 1-9 - [c71]Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction. ICCAD 2023: 1-9 - [c70]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). IJCAI 2023: 6458-6462 - [c69]Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang:
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation. MICRO 2023: 180-193 - [i18]Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin:
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. CoRR abs/2303.09305 (2023) - [i17]Yuxiang Zhao, Zhuomin Chai, Yibo Lin, Runsheng Wang, Ru Huang:
HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction. CoRR abs/2305.05374 (2023) - [i16]Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. CoRR abs/2306.16665 (2023) - [i15]Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin:
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. CoRR abs/2308.03231 (2023) - [i14]Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin:
LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization. CoRR abs/2308.03233 (2023) - [i13]Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. CoRR abs/2308.15698 (2023) - [i12]Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu:
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration. CoRR abs/2310.07424 (2023) - [i11]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-Layout Simulation Driven Analog Circuit Sizing. CoRR abs/2310.14049 (2023) - 2022
- [j31]Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, Ru Huang:
CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA). Sci. China Inf. Sci. 65(12) (2022) - [j30]Yibai Meng, Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 155-168 (2022) - [j29]Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin:
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1448-1452 (2022) - [j28]Yibo Lin, Tong Qu, Zongqing Lu, Yajuan Su, Yayi Wei:
Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3132-3142 (2022) - [j27]Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel:
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3162-3181 (2022) - [j26]Zizheng Guo, Mingwei Yang, Tsung-Wei Huang, Yibo Lin:
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3466-3478 (2022) - [j25]Wei Li, Yuzhe Ma, Yibo Lin, Bei Yu:
Adaptive Layout Decomposition With Graph Embedding Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5030-5042 (2022) - [j24]Tsung-Wei Huang, Dian-Lun Lin, Chun-Xun Lin, Yibo Lin:
Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System. IEEE Trans. Parallel Distributed Syst. 33(6): 1303-1320 (2022) - [c68]Kexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
Efficient Critical Paths Search Algorithm using Mergeable Heap. ASP-DAC 2022: 190-195 - [c67]Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang:
FPGA-Accelerated Maze Routing Kernel for VLSI Designs. ASP-DAC 2022: 592-597 - [c66]Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin:
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility. DAC 2022: 649-654 - [c65]Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS. DAC 2022: 841-846 - [c64]Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin:
A timing engine inspired graph neural network model for pre-routing slack prediction. DAC 2022: 1207-1212 - [c63]Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng:
LHNN: lattice hypergraph neural network for VLSI congestion prediction. DAC 2022: 1297-1302 - [c62]Zizheng Guo, Yibo Lin:
Differentiable-timing-driven global placement. DAC 2022: 1315-1320 - [c61]Siting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler. DATE 2022: 760-765 - [c60]Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu:
Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems. DATE 2022: 784-789 - [c59]Peiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting. DATE 2022: 939-944 - [c58]Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis. DATE 2022: 945-950 - [c57]Zizheng Guo, Feng Gu, Yibo Lin:
GPU-Accelerated Rectilinear Steiner Tree Generation. ICCAD 2022: 53:1-53:9 - [c56]Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang:
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography. ICCAD 2022: 122:1-122:9 - [c55]Tsung-Wei Huang, Yibo Lin:
Concurrent CPU-GPU Task Programming using Modern C++. IPDPS Workshops 2022: 588-597 - [c54]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Efficient Design Rule Checking Script Generation via Key Information Extraction. MLCAD 2022: 77-82 - [c53]Zixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, David Z. Pan:
A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation. MLCAD 2022: 135-141 - [i10]Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo, Yibo Lin:
Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++. CoRR abs/2202.00717 (2022) - [i9]Junchi Yan, Xianglong Liu, Ruoyu Cheng, Yibo Lin:
Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview. CoRR abs/2202.13564 (2022) - [i8]Tsung-Wei Huang, Yibo Lin:
Concurrent CPU-GPU Task Programming using Modern C++. CoRR abs/2203.08395 (2022) - [i7]Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng:
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction. CoRR abs/2203.12831 (2022) - [i6]Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, Ru Huang:
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA). CoRR abs/2208.01040 (2022) - 2021
- [j23]Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan:
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [j22]Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan:
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 373-385 (2021) - [j21]Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 603-607 (2021) - [j20]Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan:
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 748-761 (2021) - [j19]Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1687-1700 (2021) - [j18]Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2331-2344 (2021) - [c52]Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin:
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. ASP-DAC 2021: 152-157 - [c51]Yibo Lin:
Deep Learning for Mask Synthesis and Verification: A Survey. ASP-DAC 2021: 825-832 - [c50]Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu:
Physical Synthesis for Advanced Neural Network Processors. ASP-DAC 2021: 833-840 - [c49]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. DAC 2021: 715-720 - [c48]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Path-based Timing Analysis. DAC 2021: 721-726 - [c47]Zizheng Guo, Jing Mai, Yibo Lin:
Ultrafast CPU/GPU Kernels for Density Accumulation in Placement. DAC 2021: 1123-1128 - [c46]Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin:
Interactive Analog Layout Editing with Instant Placement Legalization. DAC 2021: 1249-1254 - [c45]Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin:
Towards AQFP-Capable Physical Design Automation. DATE 2021: 954-959 - [c44]Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, Yayi Wei:
Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing. DATE 2021: 1815-1820 - [c43]Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu:
Global Placement with Deep Learning-Enabled Explicit Routability Optimization. DATE 2021: 1821-1824 - [c42]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism. ICCAD 2021: 1-9 - [c41]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Critical Path Generation with Path Constraints. ICCAD 2021: 1-9 - [c40]Xuhua Ju, Konglin Zhu, Yibo Lin, Lin Zhang:
Asynchronous Multi-Nets Detailed Routing in VLSI using Multi-Agent Reinforcement Learning. IC-NIDC 2021: 250-254 - 2020
- [j17]Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo, David Z. Pan:
Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks. IEEE Access 8: 25372-25382 (2020) - [j16]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semisupervised Hotspot Detection With Self-Paced Multitask Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1511-1523 (2020) - [j15]Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan:
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5083-5096 (2020) - [c39]Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan:
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC 2020: 26-31 - [c38]Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan:
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c37]Wei Li, Jialu Xia, Yuzhe Ma, Jialu Li, Yibo Lin, Bei Yu:
Adaptive Layout Decomposition with Graph Embedding Neural Networks. DAC 2020: 1-6 - [c36]Rachel Selina Rajarathnam, Yibo Lin, Yier Jin, David Z. Pan:
ReGDS: A Reverse Engineering Framework from GDSII to Gate-level Netlist. HOST 2020: 154-163 - [c35]Jiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan:
DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region Constraints. ICCAD 2020: 143:1-143:9 - [c34]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
GPU-Accelerated Static Timing Analysis. ICCAD 2020: 147:1-147:9 - [c33]Yibo Lin:
GPU Acceleration in VLSI Back-end Design: Overview and Case Studies. ICCAD 2020: 168:1-168:4 - [c32]Wei Ye, Mohamed Baker Alawieh, Yuki Watanabe, Shigeki Nojima, Yibo Lin, David Z. Pan:
TEMPO: Fast Mask Topography Effect Modeling with Deep Learning. ISPD 2020: 127-134 - [i5]Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin:
Cpp-Taskflow v2: A General-purpose Parallel and Heterogeneous Task Programming System at Scale. CoRR abs/2004.10908 (2020)
2010 – 2019
- 2019
- [j14]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(9): 1585-1598 (2019) - [j13]Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan:
Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(10): 1900-1913 (2019) - [c31]Yibo Lin, Zhao Song, Lin F. Yang:
Towards a Theoretical Understanding of Hashing-Based Neural Nets. AISTATS 2019: 127-137 - [c30]Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer: Invited Paper. ASICON 2019: 1-4 - [c29]Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
Tackling signal electromigration with learning-based detection and multistage mitigation. ASP-DAC 2019: 167-172 - [c28]Wei Ye, Yibo Lin, Meng Li, Qiang Liu, David Z. Pan:
LithoROC: lithography hotspot detection with explicit ROC optimization. ASP-DAC 2019: 292-298 - [c27]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semi-supervised hotspot detection with self-paced multi-task learning. ASP-DAC 2019: 420-425 - [c26]Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan:
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC 2019: 66 - [c25]Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan:
LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks. DAC 2019: 107 - [c24]Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan:
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. DAC 2019: 117 - [c23]Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan:
GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial Networks. DAC 2019: 149 - [c22]Wei Ye, Mohamed Baker Alawieh, Meng Li, Yibo Lin, David Z. Pan:
Litho-GPA: Gaussian Process Assurance for Lithography Hotspot Detection. DATE 2019: 54-59 - [c21]ChengYue Gong, Zixuan Jiang, Dilin Wang, Yibo Lin, Qiang Liu, David Z. Pan:
Mixed Precision Neural Architecture Search for Energy Efficient Deep Learning. ICCAD 2019: 1-7 - [c20]Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs. ICCAD 2019: 1-8 - [c19]Biying Xu, Keren Zhu, Mingjie Liu, Yibo Lin, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper. ICCAD 2019: 1-8 - [c18]Keren Zhu, Mingjie Liu, Yibo Lin, Biying Xu, Shaolan Li, Xiyuan Tang, Nan Sun, David Z. Pan:
GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance. ICCAD 2019: 1-8 - [c17]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - 2018
- [j12]Xiaoqing Xu, Yibo Lin, Meng Li, Tetsuaki Matsunawa, Shigeki Nojima, Chikaaki Kodama, Toshiya Kotani, David Z. Pan:
Subresolution Assist Feature Generation With Supervised Data Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1225-1236 (2018) - [j11]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(6): 1237-1250 (2018) - [j10]Yibo Lin, Bei Yu, Meng Li, David Z. Pan:
Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(8): 1574-1587 (2018) - [j9]Wuxi Li, Yibo Lin, Meng Li, Shounak Dhar, David Z. Pan:
UTPlaceF 2.0: A High-Performance Clock-Aware FPGA Placement Engine. ACM Trans. Design Autom. Electr. Syst. 23(4): 42:1-42:23 (2018) - [c16]Che-Lun Hsu, Shaofeng Guo, Yibo Lin, Xiaoqing Xu, Meng Li, Runsheng Wang, Ru Huang, David Z. Pan:
Layout-dependent aging mitigation for critical path timing. ASP-DAC 2018: 153-158 - [c15]Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan:
A practical split manufacturing framework for Trojan prevention via simultaneous wire lifting and cell insertion. ASP-DAC 2018: 265-270 - [c14]Jiong Zhang, Yibo Lin, Zhao Song, Inderjit S. Dhillon:
Learning Long Term Dependencies via Fourier Recurrent Units. ICML 2018: 5810-5818 - [c13]Yibo Lin, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, Meng Li, David Z. Pan:
Data Efficient Lithography Modeling with Residual Neural Networks and Transfer Learning. ISPD 2018: 82-89 - [c12]Yibo Lin, Mohamed Baker Alawieh, Wei Ye, David Z. Pan:
Machine Learning for Yield Learning and Optimization. ITC 2018: 1-10 - [i4]Jiong Zhang, Yibo Lin, Zhao Song, Inderjit S. Dhillon:
Learning Long Term Dependencies via Fourier Recurrent Units. CoRR abs/1803.06585 (2018) - [i3]Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan:
Data Efficient Lithography Modeling with Transfer Learning and Active Data Selection. CoRR abs/1807.03257 (2018) - [i2]Qi Sun, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open Source Layout Decomposer. CoRR abs/1809.07554 (2018) - [i1]Yibo Lin, Zhao Song, Lin F. Yang:
Towards a Theoretical Understanding of Hashing-Based Neural Nets. CoRR abs/1812.10244 (2018) - 2017
- [j8]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple E-beam lithography. Integr. 58: 47-54 (2017) - [j7]Xiaoqing Xu, Yibo Lin, Meng Li, Jiaojiao Ou, Brian Cline, David Z. Pan:
Redundant Local-Loop Insertion for Unidirectional Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1113-1125 (2017) - [j6]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7): 1140-1152 (2017) - [j5]Yibo Lin, Bei Yu, David Z. Pan:
High Performance Dummy Fill Insertion With Coupling and Uniformity Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1532-1544 (2017) - [c11]Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan:
Concurrent Pin Access Optimization for Unidirectional Routing. DAC 2017: 20:1-20:6 - [c10]Yibo Lin, Peter Debacker, Darko Trivkovic, Ryoung-Han Kim, Praveen Raghavan, David Z. Pan:
Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. ICCD 2017: 415-418 - [c9]Wei Ye, Yibo Lin, Xiaoqing Xu, Wuxi Li, Yiwei Fu, Yongsheng Sun, Canhui Zhan, David Z. Pan:
Placement mitigation techniques for power grid electromigration. ISLPED 2017: 1-6 - [c8]Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan:
DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment. ISPD 2017: 91-98 - 2016
- [j4]Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan:
Design for manufacturability and reliability in extreme-scaling VLSI. Sci. China Inf. Sci. 59(6): 061406:1-061406:23 (2016) - [c7]Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple e-beam lithography. ASP-DAC 2016: 186-191 - [c6]Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan:
MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD 2016: 7 - [c5]Yudong Tao, Changhao Yan, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A novel unified dummy fill insertion framework with SQP-based optimization method. ICCAD 2016: 88 - 2015
- [j3]Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles J. Alpert, David Z. Pan:
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 726-739 (2015) - [c4]Yibo Lin, Bei Yu, David Z. Pan:
High performance dummy fill insertion with coupling and uniformity constraints. DAC 2015: 71:1-71:6 - [c3]David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin:
Pushing multiple patterning in sub-10nm: are we ready? DAC 2015: 197:1-197:6 - [c2]Yibo Lin, Bei Yu, Biying Xu, David Z. Pan:
Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict. ICCAD 2015: 396-403 - 2010
- [j2]Louise Nielsen, Claire Heffernan, Yibo Lin, Jun Yu:
The Daktari: An interactive, multi-media tool for knowledge transfer among poor livestock keepers in Kenya. Comput. Educ. 54(4): 1241-1247 (2010)
2000 – 2009
- 2009
- [j1]Yibo Lin, Claire Heffernan:
Addressing Animal Health Knowledge Gaps in Southern Countries: The Creation of a 2D Animal Health Resource Room. Electron. J. Inf. Syst. Dev. Ctries. 39(1): 1-27 (2009) - [c1]Yibo Lin, Claire Heffernan:
Creating a mobile-phone based geographic surveillance system for avian influenza. ICTD 2009: 480
Coauthor Index
[j50] [c117] [c113] [c112] [c111] [c110] [i30] [i29] [j49] [j48] [j47] [j45] [c107] [c105] [c102] [c101] [c98] [c97] [c96] [c95] [c94] [c93] [c91] [c87] [c85] [i23] [i22] [i21] [i20] [j41] [j38] [j35] [j34] [c81] [c78] [c75] [c74] [c72] [c71] [c69] [i17] [i13] [i11] [j31] [c65] [c58] [c56] [i6] [c16]
[j49] [j41] [i11] [j30] [j27] [c64] [c53] [j23] [j22] [j21] [j20] [j18] [c52] [c46] [j17] [j16] [j15] [c39] [c38] [c36] [c35] [c32] [j14] [j13] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [j12] [j11] [j10] [j9] [c16] [c15] [c13] [c12] [i3] [i2] [j8] [j7] [j6] [j5] [c11] [c10] [c9] [c8] [j4] [c7] [c6] [c5] [j3] [c4] [c3] [c2]
[j55] [j50] [c117] [c114] [c113] [c112] [c111] [c110] [i30] [i29] [j49] [j48] [j47] [j45] [c107] [c105] [c102] [c101] [c98] [c97] [c96] [c95] [c94] [c93] [c91] [c87] [c85] [i25] [i23] [i22] [i21] [i20] [i19] [j41] [j38] [j35] [j34] [c81] [c78] [c75] [c74] [c72] [c71] [c69] [i17] [i13] [i11] [j31] [c65] [c58] [c56] [i6] [c16]
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