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2020 – today
- 2024
[j47]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. 67(4) (2024)- [j46]Jing Mai
, Jiarui Wang, Zhixiong Di, Yibo Lin:
Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 641-653 (2024) - [j45]Yufei Chen, Zizheng Guo, Runsheng Wang, Ru Huang, Yibo Lin, Cheng Zhuo:
Dynamic Supply Noise Aware Timing Analysis With JIT Machine Learning Integration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(5): 1511-1524 (2024) - [j44]Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu:
Analytical Die-to-Die 3-D Placement With Bistratal Wirelength Model and GPU Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1624-1637 (2024) - [j43]Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin:
LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization. IEEE Trans. Circuits Syst. I Regul. Pap. 71(3): 1259-1272 (2024) - [j42]Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin:
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. IEEE Trans. Circuits Syst. II Express Briefs 71(4): 2034-2038 (2024) - [c92]Zizheng Guo, Tsung-Wei Huang, Zhou Jin, Cheng Zhuo, Yibo Lin, Runsheng Wang, Ru Huang:
Heterogeneous Static Timing Analysis with Advanced Delay Calculator. DATE 2024: 1-6 - [c91]Haoyi Zhang, Xiaohan Gao, Zilong Shen, Jiahao Song, Xiaoxu Cheng, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
SAGERoute 2.0: Hierarchical Analog and Mixed Signal Routing Considering Versatile Routing Scenarios. DATE 2024: 1-6 - [c90]Zixi Liu, Yibo Lin, Xiaojing Su, Xiaohuan Ling, Xin Hong, Bojie Ma, Yajuan Su, Yayi Wei:
Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage. ACM Great Lakes Symposium on VLSI 2024: 592-598 - [c89]Cheng-Hsiang Chiu, Zhicheng Xiong, Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
An Efficient Task-Parallel Pipeline Programming Framework. HPC Asia 2024: 95-106 - [c88]Xun Jiang, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
CircuitNet 2.0: An Advanced Dataset for Promoting Machine Learning Innovations in Realistic Chip Design Environment. ICLR 2024 - [c87]Siting Liu, Jiaxi Jiang, Zhuolun He, Ziyi Wang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. ISPD 2024: 75-82 - [c86]Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu:
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD 2024: 161-168 - [c85]Yuan Pu, Tinghuan Chen, Zhuolun He, Chen Bai, Haisheng Zheng, Yibo Lin, Bei Yu:
IncreMacro: Incremental Macro Placement Refinement. ISPD 2024: 169-176 - [i23]Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou:
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. CoRR abs/2403.07257 (2024) - [i22]Yuxuan Zhao, Peiyu Liao, Siting Liu, Jiaxi Jiang, Yibo Lin, Bei Yu:
Analytical Heterogeneous Die-to-Die 3D Placement with Macros. CoRR abs/2403.09070 (2024) - [i21]Yuxiang Zhao, Zhuomin Chai, Xun Jiang, Yibo Lin, Runsheng Wang, Ru Huang:
PDNNet: PDN-Aware GNN-CNN Heterogeneous Network for Dynamic IR Drop Prediction. CoRR abs/2403.18569 (2024) - [i20]Haoyi Zhang, Jiahao Song, Xiaohan Gao, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration. CoRR abs/2404.13062 (2024) - [i19]Bingyang Liu, Haoyi Zhang, Xiaohan Gao, Zichen Kong, Xiyuan Tang, Yibo Lin, Runsheng Wang, Ru Huang:
LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. CoRR abs/2406.18873 (2024) - 2023
- [j41]Xiaohan Gao, Haoyi Zhang, Mingjie Liu, Linxiao Shen, David Z. Pan, Yibo Lin, Runsheng Wang, Ru Huang:
Interactive Analog Layout Editing With Instant Placement and Routing Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 698-711 (2023) - [j40]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(7): 2317-2330 (2023) - [j39]Peiyu Liao, Dawei Guo, Zizheng Guo, Siting Liu, Yibo Lin, Bei Yu:
DREAMPlace 4.0: Timing-Driven Placement With Momentum-Based Net Weighting and Lagrangian-Based Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3374-3387 (2023) - [j38]Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li, Runsheng Wang, Ru Huang:
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4139-4151 (2023) - [j37]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Zizheng Guo, Sushma Yellapragada, Martin D. F. Wong:
A GPU-Accelerated Framework for Path-Based Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4219-4232 (2023) - [j36]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
Accelerating Static Timing Analysis Using CPU-GPU Heterogeneous Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 4973-4984 (2023) - [j35]Zhuomin Chai, Yuxiang Zhao, Wei Liu, Yibo Lin, Runsheng Wang, Ru Huang:
CircuitNet: An Open-Source Dataset for Machine Learning in VLSI CAD Applications With Improved Domain-Specific Evaluation Metric and Learning Strategies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(12): 5034-5047 (2023) - [j34]Xinfa Zhang, Zuodong Zhang, Yibo Lin, Zhigang Ji, Runsheng Wang, Ru Huang:
Efficient Aging-Aware Standard Cell Library Characterization Based on Sensitivity Analysis. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 721-725 (2023) - [j33]Yibo Lin, Avi Ziv, Haoxing Ren:
Introduction to the Special Issue on Machine Learning for CAD/EDA. ACM Trans. Design Autom. Electr. Syst. 28(2): 14:1-14:2 (2023) - [j32]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
DRC-SG 2.0: Efficient Design Rule Checking Script Generation via Key Information Extraction. ACM Trans. Design Autom. Electr. Syst. 28(5): 80:1-80:18 (2023) - [c84]Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. ASICON 2023: 1-4 - [c83]Yifan Chen, Jing Mai, Xiaohan Gao, Muhan Zhang, Yibo Lin:
MacroRank: Ranking Macro Placement Solutions Leveraging Translation Equivariancy. ASP-DAC 2023: 258-263 - [c82]Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin:
A Robust FPGA Router with Concurrent Intra-CLB Rerouting. ASP-DAC 2023: 529-534 - [c81]Zizheng Guo, Zuodong Zhang, Xun Jiang, Wuxi Li, Yibo Lin, Runsheng Wang, Ru Huang:
General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism. DAC 2023: 1-6 - [c80]Peiyu Liao, Hongduo Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
On a Moreau Envelope Wirelength Model for Analytical Global Placement. DAC 2023: 1-6 - [c79]Siting Liu, Ziyi Wang, Fangzhou Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. DAC 2023: 1-6 - [c78]Qipan Wang, Ping Liu, Liguo Jiang, Mingjie Liu, Yibo Lin, Runsheng Wang, Ru Huang:
MTL-Designer: An Integrated Flow for Analysis and Synthesis of Microstrip Transmission Line. DAC 2023: 1-6 - [c77]Yu Zhang, Yifan Chen, Zhonglin Xie, Hong Xu, Zaiwen Wen, Yibo Lin, Bei Yu:
LRSDP: Low-Rank SDP for Triple Patterning Lithography Layout Decomposition. DAC 2023: 1-6 - [c76]Su Zheng, Lancheng Zou, Siting Liu, Yibo Lin, Bei Yu, Martin D. F. Wong:
Mitigating Distribution Shift for Congestion Optimization in Global Placement. DAC 2023: 1-6 - [c75]Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang:
SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility. DATE 2023: 1-6 - [c74]Zuodong Zhang, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. DATE 2023: 1-2 - [c73]Yifan Chen, Zaiwen Wen, Yun Liang, Yibo Lin:
Stronger Mixed-Size Placement Backbone Considering Second-Order Information. ICCAD 2023: 1-9 - [c72]Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang:
Invited Paper: Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms. ICCAD 2023: 1-9 - [c71]Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization Using Critical Input Pattern Reduction. ICCAD 2023: 1-9 - [c70]Siting Liu, Yuan Pu, Peiyu Liao, Hongzhong Wu, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). IJCAI 2023: 6458-6462 - [c69]Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang:
Khronos: Fusing Memory Access for Improved Hardware RTL Simulation. MICRO 2023: 180-193 - [i18]Jing Mai, Jiarui Wang, Zhixiong Di, Yibo Lin:
Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. CoRR abs/2303.09305 (2023) - [i17]Yuxiang Zhao, Zhuomin Chai, Yibo Lin, Runsheng Wang, Ru Huang:
HybridNet: Dual-Branch Fusion of Geometrical and Topological Views for VLSI Congestion Prediction. CoRR abs/2305.05374 (2023) - [i16]Jing Mai, Jiarui Wang, Zhixiong Di, Guojie Luo, Yun Liang, Yibo Lin:
OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. CoRR abs/2306.16665 (2023) - [i15]Zhixiong Di, Runzhe Tao, Lin Chen, Qiang Wu, Yibo Lin:
Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. CoRR abs/2308.03231 (2023) - [i14]Zhixiong Di, Runzhe Tao, Jing Mai, Lin Chen, Yibo Lin:
LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization. CoRR abs/2308.03233 (2023) - [i13]Zuodong Zhang, Renjie Wei, Meng Li, Yibo Lin, Runsheng Wang, Ru Huang:
READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern Reduction. CoRR abs/2308.15698 (2023) - [i12]Peiyu Liao, Yuxuan Zhao, Dawei Guo, Yibo Lin, Bei Yu:
Analytical Die-to-Die 3D Placement with Bistratal Wirelength Model and GPU Acceleration. CoRR abs/2310.07424 (2023) - [i11]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-Layout Simulation Driven Analog Circuit Sizing. CoRR abs/2310.14049 (2023) - 2022
- [j31]Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, Ru Huang:
CircuitNet: an open-source dataset for machine learning applications in electronic design automation (EDA). Sci. China Inf. Sci. 65(12) (2022) - [j30]Yibai Meng, Wuxi Li, Yibo Lin, David Z. Pan:
elfPlace: Electrostatics-Based Placement for Large-Scale Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(1): 155-168 (2022) - [j29]Tsung-Wei Huang, Dian-Lun Lin, Yibo Lin, Chun-Xun Lin:
Taskflow: A General-Purpose Parallel and Heterogeneous Task Programming System. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1448-1452 (2022) - [j28]Yibo Lin, Tong Qu, Zongqing Lu, Yajuan Su, Yayi Wei:
Asynchronous Reinforcement Learning Framework and Knowledge Transfer for Net-Order Exploration in Detailed Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(9): 3132-3142 (2022) - [j27]Martin Rapp, Hussam Amrouch, Yibo Lin, Bei Yu, David Z. Pan, Marilyn Wolf, Jörg Henkel:
MLCAD: A Survey of Research in Machine Learning for CAD Keynote Paper. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3162-3181 (2022) - [j26]Zizheng Guo, Mingwei Yang, Tsung-Wei Huang, Yibo Lin:
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3466-3478 (2022) - [j25]Wei Li, Yuzhe Ma, Yibo Lin, Bei Yu:
Adaptive Layout Decomposition With Graph Embedding Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(11): 5030-5042 (2022) - [j24]Tsung-Wei Huang, Dian-Lun Lin, Chun-Xun Lin, Yibo Lin:
Taskflow: A Lightweight Parallel and Heterogeneous Task Graph Computing System. IEEE Trans. Parallel Distributed Syst. 33(6): 1303-1320 (2022) - [c68]Kexing Zhou, Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
Efficient Critical Paths Search Algorithm using Mergeable Heap. ASP-DAC 2022: 190-195 - [c67]Xun Jiang, Jiarui Wang, Yibo Lin, Zhongfeng Wang:
FPGA-Accelerated Maze Routing Kernel for VLSI Designs. ASP-DAC 2022: 592-597 - [c66]Jing Mai, Yibai Meng, Zhixiong Di, Yibo Lin:
Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility. DAC 2022: 649-654 - [c65]Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFS. DAC 2022: 841-846 - [c64]Zizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin:
A timing engine inspired graph neural network model for pre-routing slack prediction. DAC 2022: 1207-1212 - [c63]Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng:
LHNN: lattice hypergraph neural network for VLSI congestion prediction. DAC 2022: 1297-1302 - [c62]Zizheng Guo, Yibo Lin:
Differentiable-timing-driven global placement. DAC 2022: 1315-1320 - [c61]Siting Liu, Peiyu Liao, Rui Zhang, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler. DATE 2022: 760-765 - [c60]Haoyu Yang, Kit Fung, Yuxuan Zhao, Yibo Lin, Bei Yu:
Mixed-Cell-Height Legalization on CPU-GPU Heterogeneous Systems. DATE 2022: 784-789 - [c59]Peiyu Liao, Siting Liu, Zhitang Chen, Wenlong Lv, Yibo Lin, Bei Yu:
DREAMPlace 4.0: Timing-driven Global Placement with Momentum-based Net Weighting. DATE 2022: 939-944 - [c58]Zuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang:
EventTimer: Fast and Accurate Event-Based Dynamic Timing Analysis. DATE 2022: 945-950 - [c57]Zizheng Guo, Feng Gu, Yibo Lin:
GPU-Accelerated Rectilinear Steiner Tree Generation. ICCAD 2022: 53:1-53:9 - [c56]Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, Ru Huang:
DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography. ICCAD 2022: 122:1-122:9 - [c55]Tsung-Wei Huang, Yibo Lin:
Concurrent CPU-GPU Task Programming using Modern C++. IPDPS Workshops 2022: 588-597 - [c54]Binwu Zhu, Xinyun Zhang, Yibo Lin, Bei Yu, Martin D. F. Wong:
Efficient Design Rule Checking Script Generation via Key Information Extraction. MLCAD 2022: 77-82 - [c53]Zixuan Jiang, Mingjie Liu, Zizheng Guo, Shuhan Zhang, Yibo Lin, David Z. Pan:
A Tale of EDA's Long Tail: Long-Tailed Distribution Learning for Electronic Design Automation. MLCAD 2022: 135-141 - [i10]Cheng-Hsiang Chiu, Tsung-Wei Huang, Zizheng Guo, Yibo Lin:
Pipeflow: An Efficient Task-Parallel Pipeline Programming Framework using Modern C++. CoRR abs/2202.00717 (2022) - [i9]Junchi Yan, Xianglong Liu, Ruoyu Cheng, Yibo Lin:
Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview. CoRR abs/2202.13564 (2022) - [i8]Tsung-Wei Huang, Yibo Lin:
Concurrent CPU-GPU Task Programming using Modern C++. CoRR abs/2203.08395 (2022) - [i7]Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng:
LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction. CoRR abs/2203.12831 (2022) - [i6]Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Wei Liu, Runsheng Wang, Ru Huang:
CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA). CoRR abs/2208.01040 (2022) - 2021
- [j23]Hao Chen, Mingjie Liu, Biying Xu, Keren Zhu, Xiyuan Tang, Shaolan Li, Yibo Lin, Nan Sun, David Z. Pan:
MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII. IEEE Des. Test 38(2): 19-26 (2021) - [j22]Mohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li, Qixing Huang, David Z. Pan:
GAN-SRAF: Subresolution Assist Feature Generation Using Generative Adversarial Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(2): 373-385 (2021) - [j21]Junzhe Cai, Changhao Yan, Yudong Tao, Yibo Lin, Sheng-Guo Wang, David Z. Pan, Xuan Zeng:
A Novel and Unified Full-Chip CMP Model Aware Dummy Fill Insertion Framework With SQP-Based Optimization Method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(3): 603-607 (2021) - [j20]Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan:
DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 748-761 (2021) - [j19]Tsung-Wei Huang, Yibo Lin, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong:
Cpp-Taskflow: A General-Purpose Parallel Task Programming System at Scale. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1687-1700 (2021) - [j18]Wei Li, Yuzhe Ma, Qi Sun, Lu Zhang, Yibo Lin, Iris Hui-Ru Jiang, Bei Yu, David Z. Pan:
OpenMPL: An Open-Source Layout Decomposer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(11): 2331-2344 (2021) - [c52]Xiaohan Gao, Chenhui Deng, Mingjie Liu, Zhiru Zhang, David Z. Pan, Yibo Lin:
Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks. ASP-DAC 2021: 152-157 - [c51]Yibo Lin:
Deep Learning for Mask Synthesis and Verification: A Survey. ASP-DAC 2021: 825-832 - [c50]Zhuolun He, Peiyu Liao, Siting Liu, Yuzhe Ma, Yibo Lin, Bei Yu:
Physical Synthesis for Advanced Neural Network Processors. ASP-DAC 2021: 833-840 - [c49]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
A Provably Good and Practically Efficient Algorithm for Common Path Pessimism Removal in Large Designs. DAC 2021: 715-720 - [c48]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Path-based Timing Analysis. DAC 2021: 721-726 - [c47]Zizheng Guo, Jing Mai, Yibo Lin:
Ultrafast CPU/GPU Kernels for Density Accumulation in Placement. DAC 2021: 1123-1128 - [c46]Xiaohan Gao, Mingjie Liu, David Z. Pan, Yibo Lin:
Interactive Analog Layout Editing with Instant Placement Legalization. DAC 2021: 1249-1254 - [c45]Hongjia Li, Mengshu Sun, Tianyun Zhang, Olivia Chen, Nobuyuki Yoshikawa, Bei Yu, Yanzhi Wang, Yibo Lin:
Towards AQFP-Capable Physical Design Automation. DATE 2021: 954-959 - [c44]Tong Qu, Yibo Lin, Zongqing Lu, Yajuan Su, Yayi Wei:
Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing. DATE 2021: 1815-1820 - [c43]Siting Liu, Qi Sun, Peiyu Liao, Yibo Lin, Bei Yu:
Global Placement with Deep Learning-Enabled Explicit Routability Optimization. DATE 2021: 1821-1824 - [c42]Zizheng Guo, Tsung-Wei Huang, Yibo Lin:
HeteroCPPR: Accelerating Common Path Pessimism Removal with Heterogeneous CPU-GPU Parallelism. ICCAD 2021: 1-9 - [c41]Guannan Guo, Tsung-Wei Huang, Yibo Lin, Martin D. F. Wong:
GPU-accelerated Critical Path Generation with Path Constraints. ICCAD 2021: 1-9 - [c40]Xuhua Ju, Konglin Zhu, Yibo Lin, Lin Zhang:
Asynchronous Multi-Nets Detailed Routing in VLSI using Multi-Agent Reinforcement Learning. IC-NIDC 2021: 250-254 - 2020
- [j17]Jing Chen, Mohamed Baker Alawieh, Yibo Lin, Maolin Zhang, Jun Zhang, Yufeng Guo, David Z. Pan:
Powernet: SOI Lateral Power Device Breakdown Prediction With Deep Neural Networks. IEEE Access 8: 25372-25382 (2020) - [j16]Ying Chen, Yibo Lin, Tianyang Gai, Yajuan Su, Yayi Wei, David Z. Pan:
Semisupervised Hotspot Detection With Self-Paced Multitask Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(7): 1511-1523 (2020) - [j15]Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan:
ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 5083-5096 (2020) - [c39]Mohamed Baker Alawieh, Wuxi Li, Yibo Lin, Love Singhal, Mahesh A. Iyer, David Z. Pan:
High-Definition Routing Congestion Prediction for Large-Scale FPGAs. ASP-DAC 2020: 26-31 - [c38]Mingjie Liu, Wuxi Li, Keren Zhu, Biying Xu, Yibo Lin, Linxiao Shen,