default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDIntegration, Volume 58
Volume 58, June 2017
- Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi:
A routing framework for technology migration with bump encroachment. 1-8 - Taher Kourany, Maged Ghoneima, Emad Hegazi, Yehea Ismail:
PASSIOT: A Pareto-optimal multi-objective optimization approach for synthesis of analog circuits using Sobol' indices-based engine. 9-21 - Hadi Ghasemzadeh Momen, Metin Yazgi
, Ramazan Köprü, Ali Naderi Saatlo:
Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters. 22-26 - Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing:
A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. 27-34 - Ahmad T. Sheikh, Aiman H. El-Maleh:
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing. 35-46
- Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan:
Stitch aware detailed placement for multiple E-beam lithography. 47-54
- Jiajun Zhang, Haining Fan:
Low space complexity CRT-based bit-parallel GF(2n) polynomial basis multipliers for irreducible trinomials. 55-63 - Nguyen Cao Qui, Si-Rong He, Chien-Nan Jimmy Liu:
Cluster-based delta-QMC technique for fast yield analysis. 64-73 - Aaron Stillmaker, Bevan M. Baas:
Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm. 74-81 - Hengfei Zhong, Zhuoquan Huang, Dihu Chen, Tao Su, Zixin Wang:
A mechanism for detecting on-chip radio frequency interference of field-programmable gate array. 82-90 - Ioannis Koutras, Konstantinos Maragos, Dionysios Diamantopoulos, Kostas Siozios, Dimitrios Soudris:
On supporting rapid prototyping of embedded systems with reconfigurable architectures. 91-100 - Behnam Khodabandeloo, Ahmad Khonsari, Masoomeh Jasemi, Golnaz Taheri:
A fast temperature-aware fixed-outline floorplanning framework using convex optimization. 101-110 - H. C. Bandala-Hernandez, Alejandro Díaz-Sánchez, José Miguel Rocha-Pérez, Jaime Ramírez-Angulo, I. Y. López-Ortega, Javier Lemus-López, Jesús Ezequiel Molinar-Solís:
CMOS Analog Rank Order Filters using positive feedback comparators. 111-115 - Siraj Fulum Mossa, Syed Rafay Hasan, Omar S. Elkeelany:
Self-triggering hardware trojan: Due to NBTI related aging in 3-D ICs. 116-124 - Hyoungseok Moon, Taewhan Kim:
Loosely coupled multi-bit flip-flop allocation for power reduction. 125-133 - Durgesh Nandan, Jitendra Kanungo, Anurag Mahajan:
An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition. 134-141 - Yalçin Balcioglu, Günhan Dündar:
A standard cell phase locked loop design, analysis and high-level synthesis tool (CellPLL). 142-154 - Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin, Nor Hisham Hamid:
Bio-inspired fault tolerant network on chip. 155-166 - Priyajit Mukherjee, Santanu Chattopadhyay:
Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design. 167-188 - Keith A. Campbell, Wei Zuo, Deming Chen:
New advances of high-level synthesis for efficient and reliable hardware design. 189-214 - He Tang, Yong Peng, Xiang Lu, Albert Z. Wang, Hai Wang:
A quantitative design methodology for high-speed interpolation/averaging ADCs. 215-224
- Tsung-Yi Ho, Baris Taskin:
Special issue on IEEE/ACM System Level Interconnect Prediction (SLIP) Workshop 2016. 225 - Wei-Ting Jonas Chan, Andrew B. Kahng, Jiajia Li:
Revisiting 3DIC benefit with multiple tiers. 226-235 - Chih-Cheng Hsu, Masanori Hashimoto, Mark Po-Hung Lin:
Minimizing detection-to-boosting latency toward low-power error-resilient circuits. 236-244 - Jianli Chen, Yan Liu, Ziran Zhu, Wenxing Zhu:
An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning. 245-252 - Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen:
Giant Spin-Hall assisted STT-RAM and logic design. 253-261
- Saraju P. Mohanty, Ashok Srivastava, Shiyan Hu, Prasun Ghosal:
Guest editorial - Special issue on hardware assisted techniques for IoT and bigdata applications. 263-266 - Hala Hamadeh, Soma Chaudhuri, Akhilesh Tyagi:
Area, energy, and time assessment for a distributed TPM for distributed trust in IoT clusters. 267-273 - Niranjan Kumar Ray, Ashok Kumar Turuk:
A framework for post-disaster communication using wireless ad hoc networks. 274-285 - Jie He, Liyuan Xu, Peng Wang, Qin Wang:
A high precise E-nose for daily indoor air quality monitoring in living environment. 286-294 - Wazir Singh, Ankita Shukla, Sujay Deb, Angshul Majumdar:
Energy efficient EEG acquisition and reconstruction for a Wireless Body Area Network. 295-302 - Robert DiBiano, Supratik Mukhopadhyay:
Automated diagnostics for manufacturing machinery based on well-regularized deep neural networks. 303-310 - Varun Venkatesan, Swamy D. Ponpandi, Akhilesh Tyagi:
Shaping data for application performance and energy optimization in dynamic data view framework. 311-319 - Nalesh Sivanandan, Kavitha T. Madhu, Saptarsi Das, S. K. Nandy, Ranjani Narayan:
Energy aware synthesis of application kernels through composition of data-paths on a CGRA. 320-328 - Zhou Zhao, Ashok Srivastava, Lu Peng, Shaoming Chen, Saraju P. Mohanty:
A novel switchable pin method for regulating power in chip-multiprocessor. 329-338 - Gan Feng, Lan Yao, Song Chen:
AutoNFT: Architecture synthesis for hardware DFT of length-of-coprime-number products. 339-347 - Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya:
Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. 348-355 - Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya:
A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. 356-368 - S. Dinesh Kumar, Himanshu Thapliyal, Azhar Mohammad, Kalyan S. Perumalla:
Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware. 369-377 - Anirban Sengupta, Dipanjan Roy, Saumya Bhadauria:
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper). 378-389 - K. Sudeendra Kumar, G. Hanumanta Rao, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
Secure split test techniques to prevent IC piracy for IoT devices. 390-400 - Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra:
A novel current controlled configurable RO PUF with improved security metrics. 401-410
- Nuno Horta, Andrea Baschirotto, Francisco V. Fernández, Günhan Dündar, João Goes, Jorge Fernandes:
Introduction to the special issue on PRIME 2016 and SMACD 2016. 411-412 - Lorenzo Iotti, Matteo Bassi, Andrea Mazzanti, Francesco Svelto:
Design of low-power wideband frequency quadruplers based on transformer-coupled resonators for E-Band backhaul applications. 413-420 - Can Baltaci, Yusuf Leblebici:
Thermal aware design and comparative analysis of a high performance 64-bit adder in FD-SOI and bulk CMOS technologies. 421-429 - Héctor Gómez, Óscar Reyes, Elkim Roa:
A 65 nm CMOS key establishment core based on tree parity machines. 430-437 - Olufemi Akindele Olumodeji, Massimo Gottardi:
Arduino-controlled HP memristor emulator for memristor circuit applications. 438-445 - Maura Casciola, Micaela Liberti, Agnese Denzi, Alessandra Paffi, Caterina Merla, Francesca Apollonio:
A computational design of a versatile microchamber for in vitro nanosecond pulsed electric fields experiments. 446-453 - Jenny Klaus, Eric Schaefer, Roman Paris, Astrid Frank, Ralf Sommer:
A contribution towards model-based design of application-specific MEMS. 454-462 - Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández:
An inductor modeling and optimization toolbox for RF circuit design. 463-472 - Giulia Di Capua, Nicola Femia, Kateryna Stoyka:
A generalized numerical method for ferrite inductors analysis in high current ripple operation. 473-484 - Ricardo Martins, Nuno Lourenço, António Canelas, Nuno Horta:
Stochastic-based placement template generator for analog IC layout-aware synthesis. 485-495 - Engin Afacan, Günhan Dündar, Ali Emre Pusane, Mustafa Berke Yelten, I. Faik Baskaya:
Aging signature properties and an efficient signature determination tool for online monitoring. 496-503
- Yuan Xue, Chengmo Yang:
Path reuse-aware routing for non-volatile memory based FPGAs. 505-517 - Xin Huang, Valeriy Sukharev, Taeyoung Kim, Sheldon X.-D. Tan:
Dynamic electromigration modeling for transient stress evolution and recovery under time-dependent current and temperature stressing. 518-527 - Tiansong Cui, Shuang Chen, Yanzhi Wang, Qi Zhu, Shahin Nazarian, Massoud Pedram:
An optimal energy co-scheduling framework for smart buildings. 528-537 - Seyed Nematollah Ahmadyan, Suriyaprakash Natarajan, Shobha Vasudevan:
A novel test compression algorithm for analog circuits to decrease production costs. 538-548 - Dimitar Nikolov, Erik Larsson:
Clustered checkpointing: Maximizing the level of confidence for non-equidistant checkpointing. 549-562 - Travis Meade, Shaojie Zhang, Yier Jin:
IP protection through gate-level netlist security enhancement. 563-570 - Adam Kostrzewa, Selma Saidi, Leonardo Ecco, Rolf Ernst:
Ensuring safety and efficiency in networks-on-chip. 571-582 - Lu Wang, Sheng Ma, Chen Li, Wei Chen, Zhiying Wang:
A high performance reliable NoC router. 583-592
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-10-22 02:19 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
