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Chak-Wa Pui
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2020 – today
- 2023
- [c13]Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang, Yu Huang, Jianye Hao:
TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. DATE 2023: 1-5 - 2022
- [c12]Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng-Ann Heng:
Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration. ICCAD 2022: 57:1-57:9 - 2021
- [c11]Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young:
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment. ASP-DAC 2021: 176-182 - 2020
- [j4]Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young:
Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1245-1257 (2020) - [j3]Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young:
Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1902-1915 (2020) - [j2]Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ACM Trans. Design Autom. Electr. Syst. 25(2): 21:1-21:23 (2020) - [c10]Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young:
CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC 2020: 1-6
2010 – 2019
- 2019
- [c9]Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young:
Detailed routing by sparse grid graph and minimum-area-captured path search. ASP-DAC 2019: 754-760 - [c8]Chak-Wa Pui, Evangeline F. Y. Young:
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems. ICCAD 2019: 1-8 - [c7]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - [c6]Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young:
An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems. SLIP 2019: 1-8 - 2018
- [j1]Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2022-2035 (2018) - [c5]Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young:
A two-step search engine for large scale boolean matching under NP3 equivalence. ASP-DAC 2018: 592-598 - [c4]Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young:
Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration. ACM Great Lakes Symposium on VLSI 2018: 261-266 - 2017
- [c3]Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu:
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper). ICCAD 2017: 929-936 - 2016
- [c2]Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young:
Legalization algorithm for multiple-row height standard cell design. DAC 2016: 83:1-83:6 - [c1]Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs. ICCAD 2016: 67
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