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ORCIDIEEE Journal of Solid-State Circuits, Volume 55
Volume 55, Number 1, January 2020
- Tony Chan Carusone
, Mingoo Seok, Hsie-Chia Chang, Meng-Fan Chang:
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). 3-5 - Matteo Pisati, Alberto Minuti, Giacomino Bollati, Fabio Giunco, Roberto G. Massolini, Giovanni Cesura, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Nicola Ghittori, Enrico Pozzati, Marco Sosio, Marco Garampazzi, Antonio Milani:
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET. 6-18 - Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS. 19-26 - Aurangozeb, Carson R. Dick, Maruf Mohammad, Masum Hossain:
Sequence-Coded Multilevel Signaling for High-Speed Interface. 27-37 - Gain Kim, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf:
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET. 38-48 - Ningyuan Cao, Muya Chang, Arijit Raychowdhury:
A 65-nm 8-to-3-b 1.0-0.36-V 9.1-1.1-TOPS/W Hybrid-Digital-Mixed-Signal Computing Platform for Accelerating Swarm Robotics. 49-59 - Aseem Sayal, S. S. Teja Nibhanupudi, Shirin Fathima, Jaydeep P. Kulkarni:
A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing. 60-75 - Jingcheng Wang, Xiaowei Wang, Charles Eckert, Arun Subramaniyan, Reetuparna Das, David T. Blaauw, Dennis Sylvester:
A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing. 76-86 - Jeongsup Lee, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester, Yiqun Zhang, Qing Dong, Wootaek Lim, Mehdi Saligane, Yejoong Kim, Seokhyeon Jeong, Jongyup Lim, Makoto Yasuda:
A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation. 87-97 - Dai Li, Kaiyuan Yang:
A Self-Regulated and Reconfigurable CMOS Physically Unclonable Function Featuring Zero-Overhead Stabilization. 98-107 - Jeongwoo Park, Juyun Lee, Dongsuk Jeon:
A 65-nm Neuromorphic Image Classification Processor With Energy-Efficient Training Through Direct Spike-Only Feedback. 108-119 - Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda:
A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. 120-132 - Hiroyuki Kondo, Yasuhisa Shimazaki, Masao Ito, Minoru Uemura, Toshihiro Hattori, Noriaki Sakamoto, Sugako Otani, Norimasa Otsuki, Yasufumi Suzuki, Naoto Okumura, Shohei Maeda, Tomonori Yanagita, Takao Koike, Kosuke Yayama:
A 28-nm Automotive Flash Microcontroller With Virtualization-Assisted Processor Supporting ISO26262 ASIL D. 133-144 - Takashi Takemoto, Masato Hayashi, Chihiro Yoshimura, Masanao Yamaoka:
A 2× 30k-Spin Multi-Chip Scalable CMOS Annealing Processor Based on a Processing-in-Memory Approach for Solving Large-Scale Combinatorial Optimization Problems. 145-156 - Kyung-Soo Ha, Seungseob Lee, Youn-Sik Park, Hyuck-Joon Kwon, Tae-Young Oh, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Jung-Bae Lee, Chang-Kyo Lee, Dongkeon Lee, Daesik Moon, Hyong-Ryol Hwang, Dukha Park, Young-Hwa Kim, Young Hoon Son, Byongwook Na:
A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. 157-166 - Dongkyun Kim, Kibong Koo, Yongmi Kim, Dong-Uk Lee, Jaejin Lee, Ki Hun Kwon, Byeongchan Choi, Hongjung Kim, Sanghyun Ku, Jong-Sam Kim, Seungwook Oh, Minsu Park, Dain Im, Yongsung Lee, Mingyu Park, Jonghyuck Choi, Junhyun Chun, Kyowon Jin, Sungchun Jang, Jun-Yong Song, Hankyu Chi, Geunho Choi, Sunmyung Choi, Changhyun Kim, Minsik Han:
A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx. 167-177 - Noboru Shibata, Takahisa Kawabe, Taira Shibuya, Mario Sako, Kosuke Yanagidaira, Toshifumi Hashimoto, Hiroki Date, Manabu Sato, Tomoki Nakagawa, Junji Musha, Takatoshi Minamoto, Kazushige Kanda, Mizuki Uda, Dai Nakamura, Katsuaki Sakurai, Takahiro Yamashita, Jieyun Zhou, Ryoichi Tachibana, Teruo Takagiwa, Takahiro Sugimoto, Masatsugu Ogawa, Yusuke Ochi, Takahiro Shimizu, Kazuaki Kawaguchi, Masatsugu Kojima, Takeshi Ogawa, Tomoharu Hashiguchi, Ryo Fukuda, Masami Masuda, Koichi Kawakami, Tadashi Someya, Yasuyuki Kajitani, Yuuki Matsumoto, Jun Nakai, Jumpei Sato, Namasivayam Raghunathan, Yee Lih Koh, Shuo Chen, Juan Lee, Hiroaki Nasu, Hiroshi Sugawara, Koji Hosono, Toshiki Hisada, Hiroshi Nakamura, Osamu Nagao, Naoki Kobayashi, Makoto Miakashi, Yasushi Nagadomi, Tomoaki Nakano:
A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology. 178-188 - Xin Si, Rui Liu, Shimeng Yu, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Qiang Li, Meng-Fan Chang, Jia-Jing Chen, Yung-Ning Tu, Wei-Hsing Huang, Jing-Hong Wang, Yen-Cheng Chiu, Wei-Chen Wei, Ssu-Yen Wu, Xiaoyu Sun:
A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. 189-202 - Cheng-Xin Xue, Ting-Wei Chang, Tung-Cheng Chang, Hui-Yao Kao, Yen-Cheng Chiu, Chun-Ying Lee, Ya-Chin King, Chrong Jung Lin, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Wei-Hao Chen, Meng-Fan Chang, Je-Syu Liu, Jia-Fang Li, Wei-Yu Lin, Wei-En Lin, Jing-Hong Wang, Wei-Chen Wei, Tsung-Yuan Huang:
Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors. 203-215
Volume 55, Number 2, February 2020
- Haixin Song, Dang Liu, Yining Zhang, Woogeun Rhee, Zhihua Wang:
A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection. 219-232 - Taikun Ma, Wei Deng, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Yibo Liu, Baoyong Chi:
A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator. 233-248 - Bo Zhao, Nai-Chung Kuo, Benyuanyi Liu, Yi-An Li, Lorenzo Iotti, Ali M. Niknejad:
A Batteryless Padless Crystalless 116 µm × 116 µm "Dielet" Near-Field Radio With On-Chip Coil Antenna. 249-260 - Hussam AlShammary, Ahmed Hamza, Cameron Hill, James F. Buckwalter:
A Reconfigurable Spectrum-Compressing Receiver for Non-Contiguous Carrier Aggregation in CMOS SOI. 261-271 - M. V. Praveen, Nagendra Krishnapura:
High Linearity Transmit Power Mixers Using Baseband Current Feedback. 272-281 - Peyman Nazari, Saman Jafarlou, Payam Heydari:
A CMOS Two-Element 170-GHz Fundamental-Frequency Transmitter With Direct RF-8PSK Modulation. 282-297 - Hongying Wang, Filippo Schembari, Robert Bogdan Staszewski:
An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization. 298-311 - Yan Song, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins:
A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC. 312-321 - Wenning Jiang, Yan Zhu, Minglei Zhang, Chi-Hang Chan, Rui Paulo Martins:
A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. 322-332 - Song Ma, Liyuan Liu, Tong Fang, Jian Liu, Nanjian Wu:
A Discrete-Time Audio ΔΣ Modulator Using Dynamic Amplifier With Speed Enhancement and Flicker Noise Reduction Techniques. 333-343 - Liang Qi, Ankesh Jain, Dongyang Jiang, Sai-Weng Sin, Rui Paulo Martins, Maurits Ortmanns:
A 76.6-dB-SNDR 50-MHz-BW 29.2-mW Multi-Bit CT Sturdy MASH With DAC Non-Linearity Tolerance. 344-355 - Yi Zhong, Shaolan Li, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Siliang Wu, Nan Sun:
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. 356-368 - Bahman Yousefzadeh, Kofi A. A. Makinwa:
A BJT-Based Temperature-to-Digital Converter With a ±0.25 °C 3 σ-Inaccuracy From -40 °C to +180 °C Using Heater-Assisted Voltage Calibration. 369-377 - Cyuyeol Rhee, Junyoung Park, Suhwan Kim:
A 0.3 lx-1.4 Mlx Monolithic Silicon Nanowire Light-to-Digital Converter With Temperature-Independent Offset Cancellation. 378-391 - Hyunkyu Ouh, Boyu Shen, Matthew L. Johnston:
Combined In-Pixel Linear and Single-Photon Avalanche Diode Operation With Integrated Biasing for Wide-Dynamic-Range Optical Sensing. 392-403 - Nicola Adorni, Stefano Stanzione, Andrea Boni:
A 10-mA LDO With 16-nA IQ and Operating From 800-mV Supply. 404-413 - Somok Mondal, Drew A. Hall:
A 13.9-nA ECG Amplifier Achieving 0.86/0.99 NEF/PEF Using AC-Coupled OTA-Stacking. 414-425 - Hyuk Sun, Kazuki Sobue, Koichi Hamashita, Tejasvi Anand, Un-Ku Moon:
A 951-fsrms Period Jitter 3.2% Modulation Range in-Band Modulation Spread-Spectrum Clock Generator. 426-438 - Yang-Hang Fan, Ankur Kumar, Takayuki Iwai, Ashkan Roshan-Zamir, Shengchang Cai, Bo Sun, Samuel Palermo:
A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques. 439-451 - Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang:
A 1.9-mW SVM Processor With On-Chip Active Learning for Epileptic Seizure Control. 452-464 - Zhe Yuan, Yongpan Liu, Jinshan Yue, Yixiong Yang, Jingyu Wang, Xiaoyu Feng, Jian Zhao, Xueqing Li, Huazhong Yang:
STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS. 465-477 - Arvind Singh, Monodeep Kar, Venkata Chaitanya Krishna Chekuri, Sanu K. Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay:
Enhanced Power and Electromagnetic SCA Resistance of Encryption Engines via a Security-Aware Integrated All-Digital LDO. 478-493 - Fahim ur Rahman, Rajesh Pamula, Visvesh S. Sathe:
Computationally Enabled Minimum Total Energy Tracking for a Performance Regulated Sub-Threshold Microprocessor in 65-nm CMOS. 494-504 - Guiqiang Peng, Leibo Liu, Sheng Zhou, Shouyi Yin, Shaojun Wei:
A 2.92-Gb/s/W and 0.43-Gb/s/MG Flexible and Scalable CGRA-Based Baseband Processor for Massive MIMO Detection. 505-519
Volume 55, Number 3, March 2020
- Nan Sun, Qun Jane Gu:
Guest Editorial 2019 Custom Integrated Circuits Conference. 523-524 - Doohwan Jung, Sensen Li, Jong Seok Park, Tzu-Yuan Huang, Huan Zhao, Hua Wang:
A CMOS 1.2-V Hybrid Current- and Voltage-Mode Three-Way Digital Doherty PA With Built-In Phase Nonlinearity Compensation. 525-535 - Dongyi Liao, Yucai Zhang, Fa Foster Dai, Zhenqi Chen, Yanjie Wang:
An mm-Wave Synthesizer With Robust Locking Reference-Sampling PLL and Wide-Range Injection-Locked VCO. 536-546 - Hossein Jalili, Omeed Momeni:
A 230-GHz High-Power and Wideband Coupled Standing Wave VCO in 65-nm CMOS. 547-556 - Jae-Won Nam, Mike Shuo-Wei Chen:
A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. 557-566 - Yusang Chun, Tejasvi Anand:
An ISI-Resilient Data Encoding for Equalizer-Free Wireline Communication - Dicode Encoding and Error Correction for 24.2-dB Loss With 2.56 pJ/bit. 567-579 - Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Shahaboddin Moazzeni, Ralph Mason, Raleigh Smith:
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS. 580-591 - Amr Khashaba, Ahmed Elkholy, Karim M. Megawer, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu:
A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques. 592-601 - Yanlong Zhang, Arindam Sanyal, Xueyi Yu, Xing Quan, Kailin Wen, Xiyuan Tang, Gang Jin, Li Geng, Nan Sun:
A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction. 602-614 - Jun-Chau Chien:
A 1.8-GHz Near-Field Dielectric Plethysmography Heart-Rate Sensor With Time-Based Edge Sampling. 615-628 - Muya Chang, Li-Hsiang Lin, Justin Romberg, Arijit Raychowdhury:
OPTIMO: A 65-nm 279-GOPS/W 16-b Programmable Spatial-Array Processor with On-Chip Network for Solving Distributed Optimizations via the Alternating Direction Method of Multipliers. 629-638 - Luya Zhang, Ali M. Niknejad:
Design and Analysis of a Microwave-Optical Dual Modality Biomolecular Sensing Platform. 639-649 - Baibhab Chatterjee, Shreyas Sen, Charilaos Mousoulis, Dong-Hyun Seo, Anurag Kumar, Shovan Maity, Sean Scott, Daniel J. Valentino, Dallas T. Morisette, Dimitrios Peroulis:
A Wearable Real-Time CMOS Dosimeter With Integrated Zero-Bias Floating Gate Sensor and an 861-nW 18-Bit Energy-Resolution Scalable Time-Based Radiation to Digital Converter. 650-665 - Wenda Zhao, Shaolan Li, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. 666-679 - Yi Shen, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Xin Xin, Shubin Liu, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. 680-692 - Mingqiang Guo, Jiaji Mao, Sai-Weng Sin, He Gong Wei, Rui Paulo Martins:
A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration. 693-705 - Hamidreza Maghami, Pedram Payandehnia, Hossein Mirzaie, Ramin Zanbaghi, Hossein Zareie, Justin B. Goins, Siladitya Dey, Kartikeya Mayaram, Terri S. Fiez:
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. 706-718 - Xiaoyang Wang, Patrick P. Mercier:
A Dynamically High-Impedance Charge-Pump-Based LDO With Digital-LDO-Like Properties Achieving a Sub-4-fs FoM. 719-730 - Miguel E. Perez, Michael A. Sperling, John F. Bulzacchelli, Zeynep Toprak Deniz, Timothy E. Diemoz:
Distributed Network of LDO Microregulators Providing Submicrosecond DVFS and IR Drop Compensation for a 24-Core Microprocessor in 14-nm SOI CMOS. 731-743 - Wen-Chuen Liu, Pei Han Ng, Robert C. N. Pilawa-Podgurski:
A Three-Level Boost Converter With Full-Range Auto-Capacitor-Compensation Pulse Frequency Modulation. 744-755 - Reza Erfani, Fatemeh Marefat, Sudip Nag, Pedram Mohseni:
A 1-10-MHz Frequency-Aware CMOS Active Rectifier With Dual-Loop Adaptive Delay Compensation and >230-mW Output Power for Capacitively Powered Biomedical Implants. 756-766 - Abdullah Abdulslam, Patrick P. Mercier:
A Symmetric Modified Multilevel Ladder PMIC for Battery-Connected Applications. 767-780 - Zhong Tang, Yun Fang, Zheng Shi, Xiao-Peng Yu, Nianxiong Tan, Weiwei Pan:
A 1770-µm2 Leakage-Based Digital Temperature Sensor With Supply Sensitivity Suppression in 55-nm CMOS. 781-793 - Weiwei Shan, Shuai Zhang, Jiaming Xu, Minyi Lu, Longxing Shi, Jun Yang:
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit. 794-804 - Duhyun Jeon, Jong-Hak Baek, Yong-Duck Kim, Jaeseong Lee, Dong Kyue Kim, Byong-Deok Choi:
A Physical Unclonable Function With Bit Error Rate × 10-8 Based on Contact Formation Probability Without Error Correction Code. 805-816 - Zhen-Yu Liang, Hao-Hsuan Wei, Tsung-Te Liu:
A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm. 817-825 - Weiwei Shan, Wentao Dai, Liang Wan, Minyi Lu, Longxing Shi, Mingoo Seok, Jun Yang:
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System. 826-836 - Casey Hardy, Yogesh Ramadass, Kevin Scoones, Hanh-Phuc Le:
Erratum to "A Flying-Inductor Hybrid DC-DC Converter for 1-Cell and 2-Cell Smart-Cable Battery Chargers". 837
Volume 55, Number 4, April 2020
- Ken Takeuchi, Brian P. Ginsburg:
Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits. 843-845 - Umidjon Nurmetov, Tobias Fritz, Ernst Müllner, Christopher M. Dougherty, Michael Szelong, Franz Kreupl, Ralf Brederlow:
A CMOS Temperature Stabilized 2-D Mechanical Stress Sensor With 11-bit Resolution. 846-855 - Cheonhoo Jeon, Jahyun Koo, Kyongsu Lee, Minseob Lee, Su-Kyoung Kim, Sangbaie Shin, Sei Kwang Hahn, Jae-Yoon Sim:
A Smart Contact Lens Controller IC Supporting Dual-Mode Telemetry With Wireless-Powered Backscattering LSK and EM-Radiated RF Transmission Using a Single-Loop Antenna. 856-867 - Juan Sebastian Piedrahita Giraldo, Steven Lauwereins, Komail M. H. Badami, Marian Verhelst:
Vocell: A 65-nm Speech-Triggered Wake-Up SoC for 10- $\mu$ W Keyword Spotting and Speaker Verification. 868-878 - Jungwoon Park, Junyoung Jang, Geunhaeng Lee, Hyunmin Koh, Changhwan Kim, Tae Wook Kim:
A Time Domain Artificial Intelligence Radar System Using 33-GHz Direct Sampling for Hand Gesture Recognition. 879-888 - Min-Sun Keel, Young-Gu Jin, Youngchan Kim, Daeyun Kim, Yeomyung Kim, Myunghan Bae, Bumsik Chung, Sooho Son, Hogyun Kim, Taemin An, Sung-Ho Choi, Taesub Jung, Yonghun Kwon, Sungyoung Seo, Sae-Young Kim, Kwanghyuk Bae, Seung-Chul Shin, Myoungoh Ki, Seoung-Jae Yoo, Chang-Rok Moon, Hyunsurk Ryu, Joonseok Kim:
A VGA Indirect Time-of-Flight CMOS Image Sensor With 4-Tap 7- $\mu$ m Global-Shutter Pixel and Fixed-Pattern Phase Noise Self-Compensation. 889-897 - Injun Park, Woojin Jo, Chanmin Park, Byungchoul Park, Jimin Cheon, Youngcheol Chae:
A 640 $\times$ 640 Fully Dynamic CMOS Image Sensor for Always-On Operation. 898-907 - Yue Zha, Etienne Nowak, Jing Li:
Liquid Silicon: A Nonvolatile Fully Programmable Processing-in-Memory Processor With Monolithically Integrated ReRAM. 908-919 - Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany:
A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. 920-932 - Dong-Hyeon Park, Subhankar Pal, Siying Feng, Paul Gao, Jielun Tan, Austin Rovinski, Shaolin Xie, Chun Zhao, Aporva Amarnath, Timothy Wesley, Jonathan Beaumont, Kuan-Yu Chen, Chaitali Chakrabarti, Michael Bedford Taylor, Trevor N. Mudge, David T. Blaauw, Hun-Seok Kim, Ronald G. Dreslinski:
A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. 933-944 - Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew:
A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. 945-955 - Mu-Shan Lin, Tze-Chiang Huang, Chien-Chun Tsai, King-Ho Tam, Kenny Cheng-Hsiang Hsieh, Ching-Fang Chen, Wen-Hung Huang, Chi-Wei Hu, Yu-Chi Chen, Sandeep Kumar Goel, Chin-Ming Fu, Stefan Rusu, Chao-Chieh Li, Sheng-Yao Yang, Mei Wong, Shu-Chun Yang, Frank Lee:
A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. 956-966 - Longyang Lin, Saurabh Jain, Massimo Alioto:
Integrated Power Management for Battery-Indifferent Systems With Ultra-Wide Adaptation Down to nW. 967-976 - Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. 977-987 - Dong Yan, Xugang Ke, Dongsheng Brian Ma:
Direct 48-/1-V GaN-Based DC-DC Power Converter With Double Step-Down Architecture and Master-Slave AO2T Control. 988-998 - Lin Cheng, Xinyuan Ge, Wai Chiu Ng, Wing-Hung Ki, Jiawei Zheng, Tsz Fai Kwok, Chi-Ying Tsui, Ming Liu:
A 6.78-MHz Single-Stage Wireless Charger With Constant-Current Constant-Voltage Charging Technique. 999-1010 - Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun:
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. 1011-1022 - Burak Gönen, Shoubhik Karmakar, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
A Continuous-Time Zoom ADC for Low-Power Audio Applications. 1023-1031 - Chen-Kai Hsu, Timothy R. Andeen, Nan Sun:
A Pipeline SAR ADC With Second-Order Interstage Gain Error Shaping. 1032-1042 - Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang:
A 7-nm FinFET CMOS PLL With 388-fs Jitter and -80-dBc Reference Spur Featuring a Track-and-Hold Charge Pump and Automatic Loop Gain Control. 1043-1050 - Xiaolong Liu, Howard C. Luong:
A Fully Integrated 0.27-THz Injection-Locked Frequency Synthesizer With Frequency-Tracking Loop in 65-nm CMOS. 1051-1063 - Hechen Wang, Fa Foster Dai, Zhan Su, Yanjie Wang:
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver. 1064-1076 - Yoel Krupnik, Yevgeny Perelman, Itamar Levin, Yosi Sanhedrai, Roee Eitan, Ahmad Khairi, Yizhak Shifman, Yoni Landau, Udi Virobnik, Noam Dolev, Alon Meisler, Ariel Cohen:
112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels. 1077-1085 - Mayank Raj, Yohan Frans, Ping-Chuan Chiang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang:
Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. 1086-1095 - Nandish Mehta, Sen Lin, Bozhi Yin, Sajjad Moazeni, Vladimir Stojanovic:
A Laser-Forwarded Coherent Transceiver in 45-nm SOI CMOS Using Monolithic Microring Resonators. 1096-1107 - Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh:
A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET. 1108-1123 - Zeynep Toprak Deniz, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Timothy O. Dickson, Michael P. Beakes, Mounir Meghelli:
Errata Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS". 1124
Volume 55, Number 5, May 2020
- Hongtao Xu:
Introduction to the Special Section on the 2019 RFIC Symposium. 1127 - Li-Xuan Chuo